JP2021524998A - 垂直コンデンサを含む集積回路 - Google Patents

垂直コンデンサを含む集積回路 Download PDF

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Publication number
JP2021524998A
JP2021524998A JP2020563502A JP2020563502A JP2021524998A JP 2021524998 A JP2021524998 A JP 2021524998A JP 2020563502 A JP2020563502 A JP 2020563502A JP 2020563502 A JP2020563502 A JP 2020563502A JP 2021524998 A JP2021524998 A JP 2021524998A
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Japan
Prior art keywords
layer
integrated circuit
dielectric layer
silicon dioxide
vertical capacitor
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Pending
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JP2020563502A
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English (en)
Japanese (ja)
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JPWO2019217611A5 (https=
JP2021524998A5 (https=
Inventor
ボー シャンジェン
ボー シャンジェン
アール スミス パトリック
アール スミス パトリック
ティー グライダー ダグラス
ティー グライダー ダグラス
Original Assignee
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
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Publication of JP2021524998A publication Critical patent/JP2021524998A/ja
Publication of JPWO2019217611A5 publication Critical patent/JPWO2019217611A5/ja
Publication of JP2021524998A5 publication Critical patent/JP2021524998A5/ja
Priority to JP2025107196A priority Critical patent/JP2025123554A/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/795—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in lateral device isolation regions, e.g. STI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H10D84/813—Combinations of field-effect devices and capacitor only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/909—Microarchitecture
    • H10D84/929—Isolations
    • H10D84/931—FET isolation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2020563502A 2018-05-11 2019-05-09 垂直コンデンサを含む集積回路 Pending JP2021524998A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2025107196A JP2025123554A (ja) 2018-05-11 2025-06-25 垂直コンデンサを含む集積回路

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/977,712 US10622073B2 (en) 2018-05-11 2018-05-11 Integrated circuit including vertical capacitors
US15/977,712 2018-05-11
PCT/US2019/031417 WO2019217611A1 (en) 2018-05-11 2019-05-09 Integrated circuit including vertical capacitors

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2025107196A Division JP2025123554A (ja) 2018-05-11 2025-06-25 垂直コンデンサを含む集積回路

Publications (3)

Publication Number Publication Date
JP2021524998A true JP2021524998A (ja) 2021-09-16
JPWO2019217611A5 JPWO2019217611A5 (https=) 2022-05-24
JP2021524998A5 JP2021524998A5 (https=) 2022-05-24

Family

ID=68465262

Family Applications (2)

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JP2020563502A Pending JP2021524998A (ja) 2018-05-11 2019-05-09 垂直コンデンサを含む集積回路
JP2025107196A Pending JP2025123554A (ja) 2018-05-11 2025-06-25 垂直コンデンサを含む集積回路

Family Applications After (1)

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JP2025107196A Pending JP2025123554A (ja) 2018-05-11 2025-06-25 垂直コンデンサを含む集積回路

Country Status (5)

Country Link
US (2) US10622073B2 (https=)
EP (1) EP3791428A4 (https=)
JP (2) JP2021524998A (https=)
CN (1) CN112106195B (https=)
WO (1) WO2019217611A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102765313B1 (ko) * 2019-04-02 2025-02-07 삼성전자주식회사 수직 커패시터 구조 및 이를 포함하는 비휘발성 메모리 장치
CN111968983B (zh) * 2019-05-20 2023-10-17 联华电子股份有限公司 存储器元件的结构及其制造方法

Citations (15)

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US6083790A (en) * 1999-02-11 2000-07-04 Taiwan Semiconductor Manufacturing Company Ltd. Method for making y-shaped multi-fin stacked capacitors for dynamic random access memory cells
US6479341B1 (en) * 1998-03-02 2002-11-12 Vanguard International Semiconductor Corporation Capacitor over metal DRAM structure
US20030001208A1 (en) * 1998-02-26 2003-01-02 Micron Technology, Inc. Methods, structures, and circuits for transistors with gate-to-body capacitive coupling
US20030113967A1 (en) * 2000-11-27 2003-06-19 Derryl Allman Metal-insulator-metal capacitor formed by damascene processes between metal interconnect layers and method of forming same
US20040173869A1 (en) * 2002-11-15 2004-09-09 Stmicroelectronics S.R.L. Process for self-aligned manufacture of integrated electronic devices
US7232717B1 (en) * 2002-05-28 2007-06-19 O2Ic, Inc. Method of manufacturing non-volatile DRAM
JP2009099640A (ja) * 2007-10-15 2009-05-07 Renesas Technology Corp 半導体装置およびその製造方法
US20130076335A1 (en) * 2011-09-23 2013-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including a voltage divider and methods of operating the same
JP2014049735A (ja) * 2012-09-04 2014-03-17 Renesas Electronics Corp 半導体装置の製造方法
US20140220749A1 (en) * 2011-08-02 2014-08-07 Nxp B.V. A vertical mosfet transistor with a vertical capacitor region
JP2014229844A (ja) * 2013-05-27 2014-12-08 ルネサスエレクトロニクス株式会社 半導体装置
JP2016051822A (ja) * 2014-08-29 2016-04-11 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US20170025429A1 (en) * 2015-07-22 2017-01-26 United Microelectronics Corp. Semiconductor integrated device including capacitor and memory cell and method of forming the same
JP2017157772A (ja) * 2016-03-04 2017-09-07 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2017195270A (ja) * 2016-04-20 2017-10-26 株式会社フローディア 不揮発性半導体記憶装置

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US5495441A (en) * 1994-05-18 1996-02-27 United Microelectronics Corporation Split-gate flash memory cell
KR100297712B1 (ko) * 1998-07-23 2001-08-07 윤종용 고집적화를위한불휘발성메모리및그제조방법
US6518618B1 (en) * 1999-12-03 2003-02-11 Intel Corporation Integrated memory cell and method of fabrication
US6888755B2 (en) * 2002-10-28 2005-05-03 Sandisk Corporation Flash memory cell arrays having dual control gates per memory cell charge storage element
US20070231970A1 (en) * 2006-03-31 2007-10-04 Tsuyoshi Fukuo Cured mold compound spacer for stacked-die package
US8692306B2 (en) * 2012-01-05 2014-04-08 Taiwan Semiconductor Manufacturing Co., Ltd. Decoupling capacitor and method of making same
US8889484B2 (en) * 2012-10-02 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for a component package
US9508702B2 (en) * 2013-09-27 2016-11-29 Freescale Semiconductor, Inc. 3D device packaging using through-substrate posts
US9508701B2 (en) * 2013-09-27 2016-11-29 Freescale Semiconductor, Inc. 3D device packaging using through-substrate pillars
US9728510B2 (en) * 2015-04-10 2017-08-08 Analog Devices, Inc. Cavity package with composite substrate
US9502397B1 (en) * 2015-04-29 2016-11-22 Deca Technologies, Inc. 3D interconnect component for fully molded packages
US9984998B2 (en) * 2016-01-06 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Devices employing thermal and mechanical enhanced layers and methods of forming same
US20170278825A1 (en) * 2016-03-24 2017-09-28 Freescale Semiconductor, Inc. Apparatus and Methods for Multi-Die Packaging

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030001208A1 (en) * 1998-02-26 2003-01-02 Micron Technology, Inc. Methods, structures, and circuits for transistors with gate-to-body capacitive coupling
US6479341B1 (en) * 1998-03-02 2002-11-12 Vanguard International Semiconductor Corporation Capacitor over metal DRAM structure
US6083790A (en) * 1999-02-11 2000-07-04 Taiwan Semiconductor Manufacturing Company Ltd. Method for making y-shaped multi-fin stacked capacitors for dynamic random access memory cells
US20030113967A1 (en) * 2000-11-27 2003-06-19 Derryl Allman Metal-insulator-metal capacitor formed by damascene processes between metal interconnect layers and method of forming same
US7232717B1 (en) * 2002-05-28 2007-06-19 O2Ic, Inc. Method of manufacturing non-volatile DRAM
US20040173869A1 (en) * 2002-11-15 2004-09-09 Stmicroelectronics S.R.L. Process for self-aligned manufacture of integrated electronic devices
JP2009099640A (ja) * 2007-10-15 2009-05-07 Renesas Technology Corp 半導体装置およびその製造方法
US20140220749A1 (en) * 2011-08-02 2014-08-07 Nxp B.V. A vertical mosfet transistor with a vertical capacitor region
US20130076335A1 (en) * 2011-09-23 2013-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including a voltage divider and methods of operating the same
JP2014049735A (ja) * 2012-09-04 2014-03-17 Renesas Electronics Corp 半導体装置の製造方法
JP2014229844A (ja) * 2013-05-27 2014-12-08 ルネサスエレクトロニクス株式会社 半導体装置
JP2016051822A (ja) * 2014-08-29 2016-04-11 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US20170025429A1 (en) * 2015-07-22 2017-01-26 United Microelectronics Corp. Semiconductor integrated device including capacitor and memory cell and method of forming the same
JP2017157772A (ja) * 2016-03-04 2017-09-07 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2017195270A (ja) * 2016-04-20 2017-10-26 株式会社フローディア 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
US20200219566A1 (en) 2020-07-09
CN112106195A (zh) 2020-12-18
EP3791428A4 (en) 2021-06-16
JP2025123554A (ja) 2025-08-22
US11152068B2 (en) 2021-10-19
EP3791428A1 (en) 2021-03-17
US10622073B2 (en) 2020-04-14
WO2019217611A1 (en) 2019-11-14
US20190348119A1 (en) 2019-11-14
CN112106195B (zh) 2025-01-21

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