CN111919296A - 功率模块以及制造功率模块的方法 - Google Patents
功率模块以及制造功率模块的方法 Download PDFInfo
- Publication number
- CN111919296A CN111919296A CN201980022355.1A CN201980022355A CN111919296A CN 111919296 A CN111919296 A CN 111919296A CN 201980022355 A CN201980022355 A CN 201980022355A CN 111919296 A CN111919296 A CN 111919296A
- Authority
- CN
- China
- Prior art keywords
- power
- substrate
- prepackaged
- conductive material
- die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 103
- 239000004020 conductor Substances 0.000 claims abstract description 43
- 239000000463 material Substances 0.000 claims description 12
- 238000005245 sintering Methods 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 3
- 238000007650 screen-printing Methods 0.000 claims description 3
- 238000010292 electrical insulation Methods 0.000 description 7
- 230000017525 heat dissipation Effects 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 5
- 238000001816 cooling Methods 0.000 description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012777 electrically insulating material Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000003801 milling Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/115—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
- H01L2224/22—Structure, shape, material or disposition of high density interconnect preforms of a plurality of HDI interconnects
- H01L2224/221—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
- H01L2224/27312—Continuous flow, e.g. using a microsyringe, a pump, a nozzle or extrusion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
- H01L2224/2732—Screen printing, i.e. using a stencil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/8382—Diffusion bonding
- H01L2224/83825—Solid-liquid interdiffusion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1027—IV
- H01L2924/10272—Silicon Carbide [SiC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/1033—Gallium nitride [GaN]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13062—Junction field-effect transistor [JFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
公开了一种功率模块(1),该功率模块(1)包括:‑第一基板和第二基板(10),各个基板包括导电材料构图层(12);‑定位在基板之间的多个预包装功率单元(20),各个单元包括:○嵌入有至少一个功率管芯(21)的电绝缘芯(21),以及○在电绝缘芯(21)的相对侧的两个导电材料外层(23),所述外层分别连接到基板的各个构图层,其中,预包装功率单元的各个外层包括通过布置在电绝缘芯(21)中的连接来连接到功率管芯的相应触点(220)的接触焊盘(230),所述接触焊盘的表面积大于与其连接的功率管芯电触点的表面积。
Description
技术领域
本发明涉及一种包括两个基板以及定位在基板之间的多个预包装功率单元的功率模块,各个预包装功率单元包括至少一个功率管芯。本发明还涉及这种功率模块的制造方法。
背景技术
例如在许多不同的领域中(例如,汽车、航空、铁路工业中),诸如二极管或各种类型的功率晶体管(MOSFET、JFET、IGBT、HEMT)的功率管芯是用于电功率的控制和转换的功率模块的基本组件。与通常以横向方式构建的信号调理管芯相反垂直构造功率管芯。结果,管芯在其各侧具有电连接。
目前将功率管芯连接到其它组件(例如,在功率模块中)的最常见方式是通过使用诸如直接接合铜(DBC)基板的基板,其包括至少一侧覆盖有铜层的陶瓷板。功率管芯的一侧被焊接或烧结在基板上,在管芯的另一侧通过超声焊接在管芯金属化上的引线接合或带连接。
开关频率的不断增加允许整个转换器的体积减小。这种小型化导致功率集中在减小的体积中。因此,热密度进一步增加。所有这些演变会聚为需要功率模块的可靠性增加以及热增强。
为了增强包括多个功率管芯的功率模块中的热耗散,已经提出了包括两个冷却基板(例如,DBC)的功率模块,功率管芯被夹在这两个冷却基板之间。例如文献US6,072,240中就是这种情况,其公开了定位在两个基板之间的多个IGBT管芯。
这些功率模块的主要优点是其通过双面冷却来散热的良好能力。
然而,现有双面冷却解决方案并非没有缺点。首先,使用烧结技术,将管芯接合在两个基板之间需要在基板上和管芯上施加压力。由于管芯非常脆弱,所以必须小心地使压力在基板的表面上适当分布,以免破坏定位在其间的任何管芯。
其次,在各种类型的功率管芯之间(例如,在二极管和功率开关之间)管芯厚度通常不同。由于该厚度差异,第二基板无法直接接合到管芯的上侧。为了适应这些厚度变化,已提出了一些解决方案,其中基板非平面并且表现出凸出的区域或柱(例如文献US2011/0254177中)。然而,由于各个零件的尺寸公差,这种模块的设计和制造复杂。
还提出了这样的功率模块:通过烧结在管芯和基板上的凸块来形成管芯与第二基板之间的界面,凸块的尺寸适应管芯之间的厚度变化。在这种解决方案中,凸块还充当间隔物以便确保功能性电绝缘。如果基板仅分离开管芯的厚度(平均约0.5mm),则无法确保功能绝缘。此外,添加的垫片需要被焊接在管芯上和基板上,从而增加了焊料层,这将增加热应力并使导热性劣化。
然而,这些解决方案没有解决另一问题,该问题在于功率管芯电触点的非常有限的尺寸。例如,晶体管控制焊盘(栅极或基极)远小于功率焊盘。因此,将其连接到基板特别困难。特别是对于宽带隙器件,栅极连接需要高精度零件和准确对准,这又涉及昂贵的设备并带来高产风险。
鉴于此问题,上述解决方案目前仍未商用,并且文献中可见的双面模块限于类似IGBT芯片或二极管的大特征尺寸,并且不适于任何类型的功率管芯。
在C.DiMarino等人的出版物“Design of a novel,high-density,high-speed10kV SiC MOSFET module”(2017IEEE能源转换大会与展会(ECCE),2017年,第4003-4010页)中,通过扩大栅极焊盘以允许与钼垫片连接解决了SiC MOSFET的栅极焊盘的尺寸问题。然而,该解决方案需要对管芯金属化进行大量修改,由此有损高效热和电流传送。
发明内容
鉴于上文,本发明旨在提供一种具有高效冷却和高可靠性的功率模块。
本发明的另一目的在于提供一种具有双面冷却的功率模块,其管芯附接更容易,同时确保相对基板之间的所需电绝缘。
本发明的另一目的在于提供一种比现有技术更易于制造的功率模块。
因此,公开了一种功率模块,该功率模块包括:
-第一平面基板和第二平面基板,各个基板包括导热材料层和导电材料构图层,
-定位在第一平面基板和第二平面基板之间的多个预包装功率单元,各个预包装功率单元包括:
ο电绝缘芯,
ο嵌入在电绝缘芯中的至少一个功率管芯,各个功率管芯具有相对的电触点,以及
ο在电绝缘芯的相对侧的两个导电材料外层,所述外层分别连接到平面基板的各个导电材料构图层,
其中,预包装功率单元的各个导电材料外层包括通过布置在预包装功率单元的电绝缘芯中的连接来连接到功率管芯的相应电触点的接触焊盘,所述接触焊盘的表面积大于与之连接的功率管芯电触点的表面积。
在实施方式中,各个预包装功率单元还包括嵌入在电绝缘芯中的两个导电材料内层,各个内层被定位在功率管芯与相应外层之间,外层的厚度大于内层的厚度,
并且外层的所述接触焊盘与功率管芯的相应电触点之间的连接包括外层的所述接触焊盘与相应内层的接触焊盘之间的第一连接以及相应内层的所述接触焊盘与功率管芯的相应电触点之间的第二连接。
然后,导电材料内层的接触焊盘的表面积可大于与之连接的功率管芯电触点的表面积。
预包装功率单元的外层与内层之间的连接以及功率管芯的内层与电触点之间的连接可以是布置在电绝缘芯中的通孔。
在实施方式中,功率模块还在预包装功率单元的各个外层与基板的构图层之间包括导电和导热接合材料层,所述接合材料选自包括焊膏、烧结膏或导电膏的组。
根据实施方式,功率模块还可包括填充位于基板之间的空间以及位于预包装功率单元之间的空间的介电材料。
优选地,包含在不同预包装功率单元中的至少两个功率管芯具有作为功率管芯的相对侧上的电触点之间的最大距离测量的不同厚度,并且对应预包装功率单元具有在其相应两个导电材料外层之间测量的相等厚度。平面基板可以是直接接合铜基板、绝缘金属基板或活性金属钎焊基板。
在实施方式中,功率模块还包括安装在基板之一的导电材料构图层上的至少一个无源组件。
基板还可包括功率管芯的功率端子、输出端子和控制端子,所述端子电连接到导电材料构图层。
还公开了一种根据以上描述的功率模块的制造方法,该方法包括以下步骤:
-提供两个基板,各个基板包括具有接触焊盘的导电材料构图层和导热材料层,
-将预包装功率单元放置在两个基板之间,其中,各个预包装单元包括嵌入在电绝缘芯中并且连接到具有接触焊盘的导电材料外层的功率管芯,使得各个预包装功率单元的外层的接触焊盘与基板的构图层的接触焊盘匹配,
其中,接合材料存在于功率单元的导电材料外层上或导电材料构图层上,
-将基板和预包装功率单元接合在一起。
该方法可包括通过介电材料填充基板之间的剩余空间以及预包装功率单元之间的剩余空间的另一步骤。
该方法还可包括在接合步骤之前,将至少一个无源组件安装在基板的导电材料构图层之一上的步骤。
可通过丝网印刷或喷嘴沉积来施加接合材料。
该方法还可包括制造预包装功率单元,使得所有预包装功率单元具有相同的厚度的初步步骤。
由于附接在预包装功率单元的相对侧的两个基板,根据本发明的功率模块提供了良好的热耗散。在基板之间并入预包装功率单元允许确保所需电绝缘,因为功率单元充当基板之间的间隔物,并且还因为它们包括电绝缘材料芯。
另外,使用预包装功率单元使得可连接到功率管芯的小电焊盘,因为基板的接触焊盘可连接到起到扇出封装的作用的功率单元的扩大的接触焊盘。
为了进一步增强热耗散和电绝缘,功率模块在基板之间的空间以及预包装功率单元之间的空间也可由电绝缘和导热材料填充。
本发明的其它特征和优点将从以下参照附图作为非限制性示例给出的详细描述显而易见。
附图说明
[图1]
图1是根据本发明的实施方式的功率模块的示意性表示。
[图2a]
图2a是根据本发明的另一实施方式的功率模块的示意性表示。
[图2b]
图2b是图2a的功率模块的一部分的放大图。
[图3a]
图3a是根据本发明的另一实施方式的功率模块的示意图。
[图3b]
图3b是根据本发明的另一实施方式的功率模块的示意图。
[图4]
图4示意性地表示根据本发明的实施方式的制造方法的主要步骤。
具体实施方式
参照图1,现在将描述根据本发明的实施方式的功率模块1。
功率模块1包括两个基板10,各个基板10至少包括导热材料层11(也是电绝缘材料),其上设置有导电材料构图层12。例如,基板10可以是直接接合铜(DBC)基板,其中铜构图层12布置在形成导热和电绝缘层的陶瓷板11(例如,由氧化铝制成)上。根据其它示例,基板10可以是绝缘金属基板(IMS)或活性金属钎焊(AMB)基板。
功率模块1还包括定位在两个基板10之间的多个预包装功率单元20,其中,两个导电材料构图层12朝着彼此定位。各个预包装功率单元20至少包括电绝缘芯21,其中嵌入有至少一个功率管芯22。功率管芯可以是诸如MOSFET、JFET或IGBT、HEMT的二极管或晶体管。在实施方式中,功率管芯22由宽带隙半导体(即,带隙在2-4eV的范围内的半导体)制成。例如,功率管芯可在碳化硅SiC中或氮化镓GaN中制成。
功率管芯在其相对侧具有电触点220(图2b)。在实施方式中,功率管芯22是二极管并且具有两个相对的电触点220。在另一实施方式中,功率管芯22是晶体管并且具有三个电触点220,根据晶体管的类型包括栅极、源极和漏极或者栅极、发射极和集电极。功率管芯22也可具有数量大于三个的电触点。
预包装功率单元20的电绝缘芯21优选具有低热阻以提供更好的热耗散。电绝缘芯21可由FR-4玻璃环氧树脂、聚酰亚胺或者诸如HTCC(高温共烧陶瓷)或LTCC(低温共烧陶瓷)的陶瓷制成。
另外,预包装功率单元1还在电绝缘芯21的相对主表面上包括两个导电材料(例如,铜)外层23。因此,当单元1被定位在基板之间时,预包装功率单元1的两个外层23与基板10的相应导电层12接触。
通过蚀刻或铣削对各个外层23进行构图以与基板10的导电层12的图案匹配。为此,各个外层包括至少一个接触焊盘230,其被配置为当预包装功率单元被插入在基板10之间时与导电层之一的接触焊盘(未示出)匹配。此外,外层23的接触焊盘230或连接到第一接触焊盘并处于相同电位的同一层的另一接触焊盘也连接到功率管芯22的相应电触点220。
因此,在基板10的构图导电层12与功率管芯22之间建立连接。
因此,功率模块可包括集成在相应功率单元中的多个功率管芯22(各个功率单元可包括一个或更多个功率管芯),并且根据功率模块的所需拓扑来连接功率单元。例如,功率模块可以是逆变器或DC/DC转换器。
在图1中示意性地示出的实施方式中,预包装功率单元1的外层的接触焊盘230通过布置在电绝缘芯21中的通孔24连接到功率管芯的相应电触点。
在图2a和图2b中示意性地示出的另一实施方式中,预包装功率单元1还包括至少两个导电材料(例如,铜)内层25,各个层被嵌入在电绝缘芯21中并被定位在功率管芯与相应外层23之间。在这种情况下,各个内层25包括通过布置在电绝缘芯21中的通孔240连接到功率管芯的相应电触点的至少一个接触焊盘250,并且外层23的接触焊盘230通过布置在电绝缘芯21中的其它通孔241连接到相应内层25的接触焊盘。因此,外层23的接触焊盘230通过定位在其间的内层25连接到功率管芯的电触点。
优选地,外层的接触焊盘230的表面积大于与其连接的功率管芯电触点220的表面积。因此,由于外层的扩大的接触焊盘230,使用预包装功率单元允许扩大功率管芯的接触表面积。
在预包装功率单元20还包括具有相应接触焊盘250的导电材料内层25的实施方式中,内层25的接触焊盘250的表面积大于与其连接的功率管芯的电触点的表面积,并且可小于也与其连接的外层的接触焊盘230的表面积或具有相同的表面积。
因此,在任何情况下功率管芯的电触点与外层23接触焊盘230之间的表面积增加。
这使得预包装功率单元2与基板10的组装和连接更容易,并且还允许向管芯22传输高功率。
在预包装功率单元20包括导电材料内层25的实施方式中,外层的厚度可大于内层25的厚度(例如,至少大五倍或十倍),以便增加向功率管芯的功率传输。根据非限制性实施方式,内层25可具有约30-35μm的厚度,外层23可具有约400μm的厚度。
为了适应足够的功率传输,将功率管芯电触点与内层接触焊盘连接的通孔240的密度可为至少20通孔/mm2(例如,30通孔/mm2),例如通孔深度与钻头直径之比为1:2.5。
由于外层的接触焊盘的表面积更重要,将内层的接触焊盘250与外层的接触焊盘连接的通孔241的密度可等于或低于30通孔/mm2;例如,通孔深度与钻头直径之比为1:1。
各个预包装功率单元通过烧结、焊接或液体扩散接合技术附接到模块1的基板10,如下面将更详细描述的。因此,模块1还在预包装功率单元1的各个外层23与基板的导电层12之间包括诸如焊膏、烧结膏(例如,银烧结膏)或导电膏的接合材料层30。
由于各种功率管芯的厚度可为可变的(该厚度是功率管芯的相对电触点之间的距离),所以同一功率模块1并且包含变化厚度的功率管芯的所有预包装功率单元优选具有相同的厚度(作为功率单元的外层23之间的距离测量)。为了适应功率管芯之间的厚度变化,功率单元可具有恒定厚度的电绝缘芯,其被确定为足以嵌入任何功率管芯并确保两个基板10之间的足够电隔离。
因此,电绝缘芯21的厚度被确定为嵌入最大厚度的功率管芯并在基板之间提供电隔离的最小厚度。因此,功率管芯的厚度变化由功率单元补偿,因此功率模块的设计和制造更容易。
功率单元的厚度超过功率管芯还允许在基板10之间创建足够的空间以在它们之间提供所需电绝缘。
如例如图3a和图3b中所示,功率模块1还可包括附加无源组件40(例如,去耦电容器或栅极电阻器),其可被限制到基板之一的一个导电层12。
功率模块1还包括端子,所述端子可以是焊接在导电层12上的一个或更多个引线框架的一部分。所述端子包括管芯的功率端子50、输出端子51和控制端子52。驱动器可被焊接在导电层之一上并连接到控制端子,或者可连同它们意在控制的功率管芯一起被并入功率单元中以便减小驱动器与功率管芯之间的距离。
最后,功率模块1优选地还包括填充基板10之间的间隙以及功率单元与包含在模块中的其它组件之间的间隙的介电材料60。其可以是FR-4玻璃环氧树脂、聚对二甲苯或有机硅。优选地,介电材料具有大于至少1W/(m.K)的热导率,以便增强热耗散,同时还增加基板10之间的电绝缘。
参照图4,现在将说明上述功率模块1的制造方法。
该方法包括:第一步骤100,提供具有电绝缘导热材料层11和导电材料构图层12的两个基板10。通过铣削或蚀刻来进行构图。在实施方式中,诸如电容器的至少一个无源组件可例如通过焊接附接到基板之一。还可在执行步骤200之后进行无源组件的安装。
在第二步骤200期间,根据以上描述的多个预包装功率单元20被定位在基板之间,使得基板10的各个构图层12面向功率单元的外层23,并且使得构图层的接触焊盘与外层23的接触焊盘匹配。
与将功率管芯直接定位在基板上相比,此步骤更易于执行,因为预包装功率单元的外部接触焊盘(由外层的接触焊盘形成)比功率管芯的电触点大。
优选地,在步骤200之前,将接合材料30施加在外层23和基板的构图层12中的至少一个的接触焊盘上。优选地,将接合材料施加在外层和构图层12二者的接触焊盘上。接合材料可以是焊膏或烧结膏或导电膏。其可通过丝网印刷或喷嘴沉积施加。
然后,该方法包括步骤300:将基板与预包装功率单元20接合。在烧结的情况下,可通过热将两个基板压在一起。由于通过预封装单元来确保两个基板之间的距离,所以不存在倾斜或表面上压力不平衡的风险。
在焊接的情况下,由焊膏的相变导致的表面张力可能破坏基板关于预包装功率单元的各个接触焊盘的定位。在这种情况下,可使用附加定位销(未示出)来将基板和功率单元的组装保持就位。
支撑至少一个端子的引线框架也可通过焊接或烧结附接到至少一个基板,以用于提供至少一些模块端子。也可在预包装功率单元与基板接合之前执行该引线框架的接合。
可选地,在步骤400期间,可通过插入介电填充材料来填充基板之间的剩余间隙以及组件(功率单元和/或无源组件)之间的剩余间隙,以便增强基板之间的电绝缘和热耗散。
Claims (15)
1.一种功率模块,该功率模块包括:
-第一平面基板和第二平面基板,各个基板包括导热材料的层和导电材料的构图层,
-定位在所述第一平面基板和所述第二平面基板之间的多个预包装功率单元,各个预包装功率单元包括:
○电绝缘芯,
○嵌入在所述电绝缘芯中的至少一个功率管芯,各个功率管芯具有相对的电触点,以及
○在所述电绝缘芯的相对侧的导电材料的两个外层,所述外层分别连接到平面基板的导电材料的各个构图层,
其中,预包装功率单元的导电材料的各个外层包括通过布置在所述预包装功率单元的所述电绝缘芯中的连接来连接到所述功率管芯的相应电触点的接触焊盘,所述接触焊盘的表面积大于与其连接的功率管芯电触点的表面积。
2.根据权利要求1所述的功率模块,其中,各个预包装功率单元还包括嵌入在所述电绝缘芯中的导电材料的两个内层,各个内层被定位在所述功率管芯与相应的外层之间,所述外层的厚度大于所述内层的厚度,
并且外层的所述接触焊盘与所述功率管芯的相应电触点之间的连接包括所述外层的所述接触焊盘与相应内层的接触焊盘之间的第一连接以及相应内层的所述接触焊盘与所述功率管芯的相应电触点之间的第二连接。
3.根据权利要求2所述的功率模块,其中,导电材料的所述内层的所述接触焊盘的表面积大于与其连接的功率管芯电触点的表面积。
4.根据权利要求1或2所述的功率模块,其中,预包装功率单元的外层与内层之间的连接以及功率管芯的内层与电触点之间的连接是布置在所述电绝缘芯中的通孔。
5.根据前述权利要求中的任一项所述的功率模块,该功率模块还包括预包装功率单元的各个外层与基板的所述构图层之间的导电和导热接合材料的层,所述接合材料选自包括焊膏、烧结膏或导电膏的组。
6.根据前述权利要求中的任一项所述的功率模块,该功率模块还包括填充位于所述基板之间的空间以及位于所述预包装功率单元之间的空间的介电材料。
7.根据前述权利要求中的任一项所述的功率模块,其中,包含在不同预包装功率单元中的至少两个功率管芯具有作为所述功率管芯的相对侧上的电触点之间的最大距离测量的不同厚度,并且对应的预包装功率单元具有在其相应的导电材料的两个外层之间测量的相等厚度。
8.根据前述权利要求中的任一项所述的功率模块,其中,平面基板是直接接合铜基板、绝缘金属基板或活性金属钎焊基板。
9.根据前述权利要求中的任一项所述的功率模块,该功率模块还包括安装在所述基板之一的导电材料的所述构图层上的至少一个无源组件。
10.根据前述权利要求中的任一项所述的功率模块,其中,所述基板还包括所述功率管芯的功率端子、输出端子和控制端子,所述端子电连接到导电材料的所述构图层。
11.一种用于制造根据前述权利要求中的任一项所述的功率模块的方法,该方法包括以下步骤:
-提供两个基板,各个基板包括具有接触焊盘的导电材料的构图层和导热材料的层,
-将预包装功率单元放置在所述两个基板之间,其中,各个预包装单元包括嵌入在电绝缘芯中并且连接到具有接触焊盘的导电材料的外层的功率管芯,使得各个预包装功率单元的外层的所述接触焊盘与所述基板的构图层的接触焊盘匹配,
其中,接合材料存在于所述功率单元的导电材料的所述外层上或导电材料的所述构图层上,
-将所述基板和预包装功率单元接合在一起。
12.根据权利要求11所述的方法,该方法还包括通过介电材料填充所述基板之间的剩余空间以及所述预包装功率单元之间的剩余空间的步骤。
13.根据权利要求11或12所述的方法,该方法还包括在接合步骤之前,将至少一个无源组件安装在所述基板的导电材料的所述构图层之一上的步骤。
14.根据权利要求11至13中的任一项所述的方法,其中,通过丝网印刷或喷嘴沉积来施加所述接合材料。
15.根据权利要求11至14中的任一项所述的方法,该方法还包括制造所述预包装功率单元以使得所有所述预包装功率单元具有相同的厚度的初步步骤。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP18305374.3A EP3547367A1 (en) | 2018-03-30 | 2018-03-30 | Power module incorporating pre-packed power cells |
EP18305374.3 | 2018-03-30 | ||
PCT/JP2019/009551 WO2019188153A1 (en) | 2018-03-30 | 2019-03-05 | Power module and method for manufacturing power module |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111919296A true CN111919296A (zh) | 2020-11-10 |
CN111919296B CN111919296B (zh) | 2024-06-14 |
Family
ID=61965881
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201980022355.1A Active CN111919296B (zh) | 2018-03-30 | 2019-03-05 | 功率模块以及制造功率模块的方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US11217571B2 (zh) |
EP (1) | EP3547367A1 (zh) |
JP (1) | JP6935976B2 (zh) |
CN (1) | CN111919296B (zh) |
WO (1) | WO2019188153A1 (zh) |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101136396A (zh) * | 2006-08-30 | 2008-03-05 | 株式会社电装 | 包括两片带有多个半导体芯片和电子元件的衬底的功率电子封装件 |
US20080054425A1 (en) * | 2006-08-29 | 2008-03-06 | Denso Corporation | Power electronic package having two substrates with multiple electronic components |
US20090160046A1 (en) * | 2007-12-21 | 2009-06-25 | Infineon Technologies Ag | Electronic device and method |
US20090236749A1 (en) * | 2008-03-18 | 2009-09-24 | Infineon Technologies Ag | Electronic device and manufacturing thereof |
DE102008040906A1 (de) * | 2008-07-31 | 2010-02-04 | Robert Bosch Gmbh | Leiterplatine mit elektronischem Bauelement |
CN101989582A (zh) * | 2009-07-31 | 2011-03-23 | 全懋精密科技股份有限公司 | 嵌埋半导体芯片的封装基板 |
JP2011222554A (ja) * | 2010-04-02 | 2011-11-04 | Denso Corp | 半導体チップ内蔵配線基板 |
US20130307156A1 (en) * | 2012-05-15 | 2013-11-21 | Infineon Technologies Ag | Reliable Area Joints for Power Semiconductors |
US20160293579A1 (en) * | 2015-04-03 | 2016-10-06 | Globalfoundries Inc. | Integration structures for high current applications |
CN107039357A (zh) * | 2015-11-30 | 2017-08-11 | 英飞凌科技奥地利有限公司 | 芯片保护封壳和方法 |
CN206595255U (zh) * | 2017-01-24 | 2017-10-27 | 比亚迪股份有限公司 | 一种功率模块 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2741697B2 (ja) * | 1990-07-17 | 1998-04-22 | 本田技研工業株式会社 | 半導体装置 |
US6072240A (en) | 1998-10-16 | 2000-06-06 | Denso Corporation | Semiconductor chip package |
DE10221082A1 (de) * | 2002-05-11 | 2003-11-20 | Bosch Gmbh Robert | Halbleiterbauelement |
JP4385324B2 (ja) * | 2004-06-24 | 2009-12-16 | 富士電機システムズ株式会社 | 半導体モジュールおよびその製造方法 |
JP4409380B2 (ja) * | 2004-07-22 | 2010-02-03 | 本田技研工業株式会社 | 電子回路装置 |
US7999369B2 (en) | 2006-08-29 | 2011-08-16 | Denso Corporation | Power electronic package having two substrates with multiple semiconductor chips and electronic components |
FR2956423B1 (fr) * | 2010-02-16 | 2014-01-10 | Soprema | Dispositif de fixation de plaques ou de panneaux sur une couverture et couverture composite resultante |
JP5732880B2 (ja) * | 2011-02-08 | 2015-06-10 | 株式会社デンソー | 半導体装置及びその製造方法 |
US9041183B2 (en) * | 2011-07-19 | 2015-05-26 | Ut-Battelle, Llc | Power module packaging with double sided planar interconnection and heat exchangers |
EP3226014B1 (en) * | 2016-03-30 | 2024-01-10 | Mitsubishi Electric R&D Centre Europe B.V. | Method for estimating a level of damage or a lifetime expectation of a power semiconductor module comprising at least one die |
US10937731B2 (en) * | 2016-07-27 | 2021-03-02 | Hitachi, Ltd. | Semiconductor module and method for manufacturing semiconductor module |
EP3547538B1 (en) * | 2018-03-26 | 2021-08-11 | Mitsubishi Electric R & D Centre Europe B.V. | A device and a method for controlling the switching of at least a first power semiconductor switch |
EP3584833B1 (en) * | 2018-06-19 | 2021-09-01 | Mitsubishi Electric R&D Centre Europe B.V. | Power module with improved alignment |
US11515273B2 (en) * | 2019-07-26 | 2022-11-29 | Sandisk Technologies Llc | Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same |
US11393780B2 (en) * | 2019-07-26 | 2022-07-19 | Sandisk Technologies Llc | Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same |
US11270963B2 (en) * | 2020-01-14 | 2022-03-08 | Sandisk Technologies Llc | Bonding pads including interfacial electromigration barrier layers and methods of making the same |
US11171097B2 (en) * | 2020-01-28 | 2021-11-09 | Sandisk Technologies Llc | Bonded assembly containing metal-organic framework bonding dielectric and methods of forming the same |
-
2018
- 2018-03-30 EP EP18305374.3A patent/EP3547367A1/en active Pending
-
2019
- 2019-03-05 JP JP2020559684A patent/JP6935976B2/ja active Active
- 2019-03-05 CN CN201980022355.1A patent/CN111919296B/zh active Active
- 2019-03-05 WO PCT/JP2019/009551 patent/WO2019188153A1/en active Application Filing
- 2019-03-05 US US16/977,172 patent/US11217571B2/en active Active
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080054425A1 (en) * | 2006-08-29 | 2008-03-06 | Denso Corporation | Power electronic package having two substrates with multiple electronic components |
CN101136396A (zh) * | 2006-08-30 | 2008-03-05 | 株式会社电装 | 包括两片带有多个半导体芯片和电子元件的衬底的功率电子封装件 |
US20090160046A1 (en) * | 2007-12-21 | 2009-06-25 | Infineon Technologies Ag | Electronic device and method |
US20090236749A1 (en) * | 2008-03-18 | 2009-09-24 | Infineon Technologies Ag | Electronic device and manufacturing thereof |
DE102008040906A1 (de) * | 2008-07-31 | 2010-02-04 | Robert Bosch Gmbh | Leiterplatine mit elektronischem Bauelement |
CN101989582A (zh) * | 2009-07-31 | 2011-03-23 | 全懋精密科技股份有限公司 | 嵌埋半导体芯片的封装基板 |
JP2011222554A (ja) * | 2010-04-02 | 2011-11-04 | Denso Corp | 半導体チップ内蔵配線基板 |
US20130307156A1 (en) * | 2012-05-15 | 2013-11-21 | Infineon Technologies Ag | Reliable Area Joints for Power Semiconductors |
US20160293579A1 (en) * | 2015-04-03 | 2016-10-06 | Globalfoundries Inc. | Integration structures for high current applications |
CN107039357A (zh) * | 2015-11-30 | 2017-08-11 | 英飞凌科技奥地利有限公司 | 芯片保护封壳和方法 |
CN206595255U (zh) * | 2017-01-24 | 2017-10-27 | 比亚迪股份有限公司 | 一种功率模块 |
Also Published As
Publication number | Publication date |
---|---|
JP2021510937A (ja) | 2021-04-30 |
EP3547367A1 (en) | 2019-10-02 |
WO2019188153A1 (en) | 2019-10-03 |
JP6935976B2 (ja) | 2021-09-15 |
US20210043613A1 (en) | 2021-02-11 |
CN111919296B (zh) | 2024-06-14 |
US11217571B2 (en) | 2022-01-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107452707B (zh) | 含热、电性能改善的再分布结构的芯片载体及半导体器件 | |
KR102182189B1 (ko) | 전력 오버레이 구조 및 그 제조 방법 | |
US5637922A (en) | Wireless radio frequency power semiconductor devices using high density interconnect | |
US9064869B2 (en) | Semiconductor module and a method for fabrication thereof by extended embedding technologies | |
KR20140113473A (ko) | 전력 오버레이 구조 및 그 제조 방법 | |
CN108735692B (zh) | 半导体装置 | |
US9385107B2 (en) | Multichip device including a substrate | |
CN112368830A (zh) | 电力组件、功率模块、用于制造功率模块和电力组件的方法 | |
WO2019187400A1 (en) | Pre-packed power cell, power module and method for manufacturing pre-packed power cell | |
US20180040562A1 (en) | Elektronisches modul und verfahren zu seiner herstellung | |
CN114097076A (zh) | 半导体封装、电子装置及半导体封装的制造方法 | |
CN111919296B (zh) | 功率模块以及制造功率模块的方法 | |
JP2021082714A (ja) | 半導体装置 | |
CN113632223B (zh) | 具有厚导电层的电力组件 | |
CN111244061A (zh) | 氮化镓设备的封装结构 | |
US11450623B2 (en) | Semiconductor device | |
US11915986B2 (en) | Ceramic semiconductor device package with copper tungsten conductive layers | |
CN113764357B (zh) | 导电模块的封装结构 | |
WO2023017708A1 (ja) | 半導体装置 | |
US20230369160A1 (en) | Semiconductor Device Package Thermally Coupled to Passive Element | |
US20240128197A1 (en) | Assemblies with embedded semiconductor device modules and related methods | |
KR20230136459A (ko) | 전력 반도체 모듈 및 전력 반도체 모듈의 제조 방법 | |
Böttcher et al. | Concepts for realizing High-Voltage Power Modules by Embedding of SiC Semiconductors | |
CN115397090A (zh) | 齿形板 | |
WO2024086573A1 (en) | Assemblies with embedded semiconductor device modules and related methods |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant |