CN111902944A - 竖直纳米线半导体装置和其制造方法 - Google Patents

竖直纳米线半导体装置和其制造方法 Download PDF

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CN111902944A
CN111902944A CN201980021545.1A CN201980021545A CN111902944A CN 111902944 A CN111902944 A CN 111902944A CN 201980021545 A CN201980021545 A CN 201980021545A CN 111902944 A CN111902944 A CN 111902944A
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nanowire
conductive layer
layer
semiconductor device
vertical
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洪瑛
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Priority claimed from PCT/KR2019/002515 external-priority patent/WO2019182264A1/ko
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  • Recrystallisation Techniques (AREA)

Abstract

本发明涉及一种用于纳米线半导体装置的制造方法。制造方法包括以下步骤：在衬底上形成晶种层；在晶种层上形成多层，第一导电层、半导体硅层以及第二导电层以所述次序沉积在多层中；使多层图案化以在衬底上形成竖直纳米线；通过热处理使纳米线结晶；形成覆盖纳米线的绝缘层；形成围绕由纳米线的半导体硅层界定的沟道区的栅极；以及形成电连接到栅极、第一导电层以及第二导电层的金属接垫。

Description

竖直纳米线半导体装置和其制造方法
技术领域
本公开涉及一种Si纳米线半导体装置和其制造方法，且更特定来说，涉及一种使用竖直半导体纳米线的半导体装置和其制造方法。
背景技术
高性能半导体提高电子产品的质量且带来成本效益。半导体装置需要具有高迁移率(mobility)和高可靠性(reliability)，特定来说，需要通过具有某些特性来减小特性分散(characteristic dispersion)。
有源矩阵有机发光二极管(active-matrix organic light-emitting diode；AM-OLED)显示器已主要应用为最近的智能手机的移动显示器。作为这种AM-OLED显示器的像素开关元件，即使在高度集成下，具有高电荷迁移率和高可靠性的低温多晶硅薄膜晶体管(low temperature polycrystalline siliconthin film transistor；LTPS TFT)也是合适的。
准分子激光退火(Excimer Laser Annealing；ELA)主要用于硅的结晶以制造低温多晶硅薄膜晶体管(LTPS TFT)。当将这种LTPS TFT应用于大面积显示器时，可能不能保持一定水平的晶粒均匀性(crystal grain uniformity)，且良率(yield)低。
发明内容
技术问题
提供一种通过使用MIC技术来形成<111>取向的高质量Si纳米线的方法。
还提供一种使用Si纳米线的半导体装置和其制造方法。
问题的技术解决方案
根据本公开的一方面，一种制造半导体装置的方法包含：
在衬底上形成晶种层(seed layer)；
在所述晶种层上形成多层，第一导电层、半导体层、第二导电层依序堆叠在所述多层中；
通过使所述多层图案化在所述衬底上方形成竖直纳米线；
通过热处理使所述竖直纳米线结晶；
形成覆盖所述竖直纳米线的绝缘层；
由所述竖直纳米线的所述半导体层形成围绕沟道区域的栅极；
以及形成电连接到所述栅极、所述第一导电层以及所述第二导电层的金属接垫。
所述方法可进一步包含：在所述衬底上方形成层间介电(interlayerdielectric；ILD)层，所述ILD层覆盖所述竖直纳米线且具有对应于所述第一导电层、所述第二导电层以及所述栅极的多个接触孔；以及在所述ILD层上形成分别对应于所述栅极、所述第一导电层以及所述第二导电层的多个金属接垫。
所述晶种层可由选自由以下组成的群组中的至少一种形成：NiOx、NiCxOy、NiNxOy、NiCxNyOz、NiCxOy:H、NiNxOy:H、NiCxNyOz:H、NixSiy以及NixGey。
所述第一导电层、所述第二导电层以及所述竖直纳米线可包含Si、SiGe以及Ge中的一种。
所述第一导电层和所述第二导电层可以是硅导电层，且所述半导体层可以是硅层。
所述多层可包含具有p型半导体层和n型导电层的第一多层，以及具有n型半导体层和p型导电层的第二多层。
可通过同时使所述第一多层和所述第二多层图案化来形成第一竖直纳米线和第二竖直纳米线。
根据本公开的另一方面，一种通过所述方法来制造的半导体装置包含：
衬底；
源极区域或漏极区域中的第一导电层，形成于所述衬底上方；
沟道区域的半导体纳米线，在所述第一导电层上相对于所述衬底竖直地直立；
漏极区域或源极区域的第二导电层，设置在所述半导体纳米线的顶部上；
栅极，围绕所述竖直纳米线的所述沟道区域；以及
栅极绝缘层，位于所述沟道区域与所述栅极之间。
所述第一导电层、所述第二导电层以及所述竖直纳米线可包含Si、SiGe以及Ge中的一种。
第一导电层和第二导电层可以是硅导电层，且半导体纳米线可以是单晶晶粒硅纳米线。
金属层可形成于第二导电层上，且NiSi2接触层可设置在第二导电层与金属层之间。
ILD层可形成于所述衬底上方，所述ILD层覆盖所述竖直纳米线且具有对应于所述第一导电层、所述第二导电层以及所述栅极的多个接触孔，且分别对应于所述栅极、所述第一导电层以及所述第二导电层的多个金属接垫可形成于所述ILD层上。
竖直纳米线可具有圆形或多边形横截面。
第一导电层和第二导电层可从半导体纳米线的下部部分延伸到每一接触孔正下方的部分。
半导体纳米线以及第一导电层和第二导电层的晶体可在<111>方向上取向。
公开的有利效果
根据实例实施例，提供一种制造半导体纳米线沟道(其中晶体在<111>取向上生长)的方法，以及通过应用所述方法来制造CMOS的方法。根据实例实施例，可通过在大面积衬底上制造高性能LSI、存储器、传感器以及类似物来实施面板上系统(system on panel；SOP)。根据上文所描述的实例实施例，不单独需要用于形成导电层的离子注入(Ionimplantation)工艺，且也不需要现有激活(activation)工艺。因此，根据实例实施例，可获得具有高迁移率、高可靠性以及低产品到产品(product-to-product)特性分散的高良率半导体装置。
附图说明
图1到图12绘示根据实例实施例的制造竖直纳米线半导体装置的工艺的流程。
图13是根据实例实施例的用于解释竖直纳米线半导体装置的基本结构的视图。
具体实施方式
在下文中，将参考附图详细描述本公开的实例实施例。然而，本公开的实施例可修改成各种形式，且本公开的范围不应理解为受限于下文所描述的实施例。本公开的实施例可解译为提供以向本领域的技术人员进一步彻底地解释本公开的精神。在图中相同的附图标号标示相同的元件。示意性地绘制图中的各种元件和区域。因此，本公开的精神不受限于附图中所绘制的相对大小或间隔。尽管术语第一、第二等可在本文中用于描述各种元件，但这些元件不应受限于这些术语。这些术语仅用于将一个元件与另一元件区分开来。举例来说，在不脱离本公开的范围的情况下，可将第一元件称为第二元件，且相反，可将第二元件称为第一元件。
本文中使用的术语仅出于描述特定实施例的目的，且并不意图限制实例实施例。如本文中所使用，除非上下文另外明确指示，否则单数形式也意图包含复数形式。应进一步理解，当用于本说明书中时，术语“包括(comprises)”和/或“具有(have)”指定存在所陈述的特征、整数、步骤、操作、元件和/或组件，但不排除存在或添加一或多个其它特征、整数、步骤、操作、元件、组件和/或其群组。
除非另有定义，否则本文中所使用的所有术语(包含技术和科学术语)都具有与实例实施例所属领域的技术人员通常所理解相同的含义。应进一步理解，应将术语(例如常用词典中所定义的那些术语)解译为具有与其在相关技术的上下文中的意义一致的意义，且不应在理想化或过度形式化的意义上进行解译，除非在本文中明确地这样定义。
当某一实施例可以不同方式实施时，特定处理次序可与所描述次序不同地进行。举例来说，连续描述的两个工艺可实质上同时进行或可以与所描述次序相反的次序进行。
因此，将预期图示的形状因例如制造技术和/或容差而有所变化。因此，实例实施例不应理解为限于本文中所示出的区的特定形状，而是可包含(例如)由制造引起的形状偏差。如本文中所使用，术语“和/或(and/or)”包含相关联的所列项中的一个或多个的任何和所有组合。如本文中所使用的术语“衬底(substrate)”可意味着衬底自身或包含衬底和形成于其表面上的预定层或膜的堆叠结构。如本文中所使用，“衬底的表面(the surface ofthe substrate)”可意味着衬底自身的暴露表面，或形成于衬底上的预定层或膜的外表面。描述为“在……上方(above)”或“在……上(on)”之物不仅可包含直接在……上接触的那些，且还可包含在……上方非接触的那些。
在下文中，将参考附图描述根据实例实施例的制造包含竖直纳米线晶体管的CMOS装置的方法。
一种根据实例实施例的纳米线晶体管包含：衬底；源极区域或漏极区域中的第一导电层，形成于所述衬底上方；沟道区域中的半导体纳米线，在所述第一导电层上竖直地直立；漏极区域或源极区域中的第二导电层，设置在所述纳米线的顶部上；栅极，围绕所述竖直纳米线；以及栅极绝缘层，位于所述沟道区域与所述栅极之间。
一种根据实例实施例的制造纳米线晶体管的方法，包含：在衬底上形成晶种层(seed layer)；在所述晶种层上形成多层，第一导电层、半导体硅层以及第二导电层依序堆叠在所述多层中；通过使所述多层图案化在所述衬底上方形成纳米线；通过热处理使所述纳米线结晶；形成覆盖所述第一导电层的绝缘层；由所述纳米线的半导体层形成围绕沟道区域的栅极；以及形成电连接到所述第二导电层的金属接垫。
在下文中，将描述如上文所描述的根据实例实施例的制造CMOS的方法。通过理解以下技术内容，可容易地推导出竖直硅纳米线晶体管的结构和其制造方法。在以下实施例中，将描述通过使用非晶硅作为半导体材料来制造CMOS装置的方法作为实例。
如图1中所绘示，缓冲层(101)和晶种层(102)依序形成于衬底(100)上。
可通过已通过前一工艺形成的堆叠结构的最顶部介电层(top-mostdielectriclayer)来提供缓冲层(101)。缓冲层(101)可由例如绝缘材料形成，例如SiO2、SiNx、SiONx或AlOx。
缓冲层(101)上的晶种层(102)可包含选自由NiOx、NiCxOy、NiNxOy、NiCxNyOz、NiCxOy:H、NiNxOy:H、NiCxNyOz:H、NixSiy以及NixGey组成的群组中的至少一种作为Ni类氧化物。
如图2中所绘示，多层(ML)形成于晶种层(102)上，所述多层(ML)包含呈非晶态的第一硅导电层(102)、硅半导体层(104)、第二硅导电层(105)以及第二硅导电层(105)上的金属层(106)。举例来说，多层(ML)可具有n+a-Si/p a-Si/n+a-Si/TiN的堆叠结构，以用于获得具有p型硅沟道以及在p型硅沟道上和p型硅沟道下面的n型硅导电层的P型金属氧化物半导体(PMOS)晶体管。
如图3中所绘示，通过将光致抗蚀剂(photoresist；PR)掩模施加到第一晶体管的区域(例如，定义为衬底上方的PMOS晶体管区域的第一晶体管(TR1)的区域)来使多层(ML)图案化。可通过现有照相方法来进行多层(ML)的图案化。归因于多层(ML)的图案化，仅在第一晶体管(TR1)的区域中保留第一多层(ML1)，且在其余部分中暴露衬底(100)上的晶种层(102)。
如图4中所绘示，用于形成第二晶体管的第二多层(ML2)(例如，定义为第二晶体管(TR2)的区域的一部分中的N型金属氧化物半导体半导体(NMOS)晶体管)形成于衬底(100)上方。第二多层(ML2)可具有p+a-Si/na-Si/p+a-Si/TiN的堆叠结构。第二多层(ML2)可通过类似于形成第一多层(ML1)的工艺的工艺获得，且可具有其中第一硅导电层(107)、硅半导体层(108)、第二硅导电层(109)以及金属层(110)从底部堆叠的结构。
如图5中所绘示，同时使第一多层(ML1)和第二多层(ML2)图案化以在第一硅和第二硅导电层(103,107)上形成用于竖直第一晶体管和竖直第二晶体管的第一硅纳米线(W1)和第二硅纳米线(W2)。这里，向下进行图案化直到硅半导体层(104,108)两者，且从图案化排除在其下面的第一硅导电层(103,107)两者。因此，第一硅导电层(103,107)延伸到第一和第二硅纳米线(W1,W2)的外部，且在稍后将描述的ILD层的对应接触孔正下方延伸。
第一和第二硅纳米线(W1,W2)可具有圆柱体形状，且根据另一实施例，可具有矩形柱形状或多边形柱形状。这种硅纳米线的特定结构或形状不限制各种实例实施例的技术范围。
如图6中所绘示，通过低温热处理，通过进行金属诱导结晶(metalinducedcrystallization；MIC)使第一和第二硅纳米线(W1,W2)结晶。在这一结晶工艺中，晶种层的Ni与Si反应以产生NiSi2，且NiSi2到达第二硅导电层(106,109)(所述第二硅导电层(106,109)是第一和第二硅纳米线(W1,W2)的最顶部部分)以在第二硅导电层与金属层之间形成NiSi2接触层(102')。
结晶纳米线具有在(111)方向上的晶体取向。在这种热处理之后，可通过使用HNO3、HF或类似物的湿法清洁来去除可能保留在单晶晶粒硅纳米线的外圆周表面上的NiSi2。
如图7中所绘示，第一绝缘层(111)在衬底(100)上方在第一硅导电层(103,107)上形成为预设厚度。可通过形成和回蚀例如聚酰亚胺(polyimide；PI)或高密度等离子体(high-density plasma；HDP)氧化物层的有机绝缘体的方法来制造第一绝缘层(111)。这里，第一绝缘层(111)仅覆盖第一和第二硅纳米线(W1,W2)的下部部分，且其厚度根据将形成于后续工艺中的栅极的下部边界的位置来设定。
如图8中所绘示，栅极绝缘层(112)和栅极(113)形成于第一和第二硅纳米线(W1,W2)的侧面上。这一工艺涉及绝缘材料和栅极材料的沉积和图案化工艺。这里，栅极绝缘层(112)可由SiO2形成，且栅极(113)可由MoW形成。在这一情况下，栅极绝缘层(112)和栅极(113)处于不完整状态，且还同样覆盖第一和第二硅纳米线(W1,W2)的上部部分。此外，作为用于栅极(113)的外部连接的端子的接垫(113a)设置在栅极(113)下面，且在与衬底(100)的平面平行的方向上延伸预设长度。
如图9中所绘示，在衬底(100)上方以预设厚度形成第二绝缘层(114)作为平坦化层。第二绝缘层(114)的顶部表面位于第一和第二硅纳米线(W1,W2)的接触层(102')下。第二绝缘层(114)用作掩模以用于去除保留在第一和第二硅纳米线(W1,W2)的上部部分处的栅极绝缘层(112)和栅极(113)的不需要的部分。可通过形成和回蚀例如聚酰亚胺(PI)或HDP氧化物层的有机绝缘体来制造如上文所描述的具有调整后的高度或厚度的第二绝缘层(114)。
如图10中所绘示，通过各向同性蚀刻(isotropic etch)来去除栅极(113)和栅极绝缘层(112)的未由第二绝缘层(114)覆盖的暴露部分，从而完全暴露第二硅导电层(106,110)两者以及所述第二硅导电层(106,110)下面的接触层(102')，所述接触层(102')是第一和第二纳米线(W1,W2)的上部部分。在这一工艺中，不完整的栅极(113)完整了。
如图11中所绘示，具有多个接触孔(115a,115b,115c)(116a,116b,116c)的ILD(115)形成于衬底(100)上方。ILD(115)通过第一硅纳米线(W1)来覆盖包含第一晶体管且通过第二硅纳米线(W2)来覆盖包含硅纳米线晶体管的CMOS半导体装置。
如图12中所绘示，金属接垫(117a,117b,117c)(118a,118b,118c)形成于ILD(115)上，以通过接触孔(115a,115b,115c)(116a,116b,116c)电连接到第一和第二硅导电层以及其下的第一晶体管和第二晶体管的栅极。
在这一工艺之后，可根据将应用的电子装置的设计来进行额外工艺。
如图13中示意性地绘示，上文通过以上实施例所描述的纳米线半导体装置包含单晶晶粒硅纳米线以及围绕所述单晶晶粒硅纳米线的栅极，所述单晶晶粒硅纳米线是在衬底上方平行布置的源极与漏极之间的竖直沟道。这里，单晶晶粒硅纳米线具有在(111)方向上生长的晶体结构。
当通过MIC来实现单晶晶粒硅纳米线的晶体生长时，可施加由NiOx、NiCxOy、NiNxOy、NiCxNyOz、NiCxOy:H、NiNxOy:H、NiCxNyOz:H、NixSiy、NixGey或类似物形成的非晶层作为结晶催化剂层。可根据ALD方法来沉积这种催化剂层。在以上实施例的描述中，对应于沟道的硅半导体层可掺杂有n型掺杂剂或p型掺杂剂，且根据另一实施例，可由本征硅形成。
用于使非晶硅结晶的MIC热处理可在普通加热炉(furnace)中进行或可在应用电磁场的加热炉(furnace)中进行。在竖直硅纳米线提供沟道的情况下，诱导结晶的NiSi2上升到第二硅导电层的最顶部表面、上升到表面，且接触金属层以充当接触层。在实例实施例中所描述的硅纳米线不仅可应用于制造晶体管，且还可应用于制造存储器装置和二极管。
在以上实施例的描述中，一个晶体管包含一个纳米线。然而，根据另一实施例，一个晶体管可包含多个纳米线且因此具有多沟道结构。
此外，在如上文所描述的半导体装置中，第一导电层和第二导电层可具有不同掺杂类型，且因此，可制造具有p+-i-n+or n+-i-p+的结构的隧穿场效应晶体管(tunnelingfield effect transistor)。
在上述实施例中，应用硅作为半导体材料，但可应用除硅以外的SiGe、Ge或类似物作为半导体材料。
根据本公开的另一实施例，在如上文所描述的方法的基础上，可在多晶硅衬底或异质衬底上方制造硅太阳能电池，可通过制造3D堆叠结构来制造3D堆叠存储器，且可在一个衬底上方集成各种类型的装置。
已参考在图中所绘示的实施例描述根据本公开的实施例的制造半导体装置的方法以帮助理解本公开，但这仅是实例。本领域的技术人员应理解，来自所述实例的各种修改和其它等效实施例是可能的。因此，本公开的技术范围应由所附权利要求书界定。

Claims (15)

1.一种制造纳米线半导体装置的方法，所述方法包括：
在衬底上形成晶种层；
在所述晶种层上形成第一导电层、半导体层、第二导电层依序堆叠在其中的多层；
通过图案化所述多层来在所述衬底上方形成竖直纳米线；
通过热处理来使所述竖直纳米线结晶；
形成覆盖所述竖直纳米线的绝缘层；
由所述竖直纳米线的所述半导体层形成围绕沟道区域的栅极；以及
形成电连接到所述栅极、所述第一导电层以及所述第二导电层的金属接垫。
2.根据权利要求1所述的制造纳米线半导体装置的方法，还包括：
在所述衬底上方形成层间介电层，所述层间介电层覆盖所述竖直纳米线且具有对应于所述第一导电层、所述第二导电层以及所述栅极的多个接触孔；以及
在所述层间介电层上形成分别对应于所述栅极、所述第一导电层以及所述第二导电层的多个金属接垫。
3.根据权利要求1所述的制造纳米线半导体装置的方法，其中所述晶种层由选自由以下组成的群组中的至少一种形成：NiOx、NiCxOy、NiNxOy、NiCxNyOz、NiCxOy:H、NiNxOy:H、NiCxNyOz:H、NixSiy以及NixGey。
4.根据权利要求2所述的制造纳米线半导体装置的方法，其中所述晶种层由选自由以下组成的群组中的至少一种形成：NiOx、NiCxOy、NiNxOy、NiCxNyOz、NiCxOy:H、NiNxOy:H、NiCxNyOz:H、NixSiy以及NixGey。
5.根据权利要求1所述的制造纳米线半导体装置的方法，其中所述第一导电层、所述第二导电层以及所述竖直纳米线包含硅、硅锗以及锗中的一种。
6.根据权利要求2所述的制造纳米线半导体装置的方法，其中所述第一导电层、所述第二层以及所述竖直纳米线包含硅、硅锗以及锗中的一种。
7.根据权利要求5所述的制造纳米线半导体装置的方法，其中所述多层包含具有p型沟道和n型导电层的第一多层以及具有n型沟道和p型导电层的第二多层。
8.根据权利要求7所述的制造纳米线半导体装置的方法，其中通过同时图案化所述第一多层和所述第二多层来形成用于P型金属氧化物半导体半导体装置的第一纳米线和用于N型金属氧化物半导体半导体装置的第二纳米线。
9.根据权利要求1所述的制造纳米线半导体装置的方法，其中所述多层包含具有p型沟道和n型导电层的第一多层以及具有n型沟道和p型导电层的第二多层。
10.一种竖直纳米线半导体装置，通过根据权利要求1或权利要求2所述的方法来制造，所述竖直纳米线半导体装置包括：
衬底；
源极区域或漏极区域中的第一导电层，形成于所述衬底上方；
沟道区域的半导体纳米线，在所述第一导电层上相对于所述衬底竖直地直立；
漏极区域或源极区域的第二导电层，设置在所述半导体纳米线的顶部上；
栅极，围绕所述竖直纳米线的所述沟道区域；以及
栅极绝缘层，位于所述沟道区域与所述栅极之间。
11.根据权利要求10所述的竖直纳米线半导体装置，其中所述晶种层由选自由以下组成的群组中的至少一种形成：NiOx、NiCxOy、NiNxOy、NiCxNyOz、NiCxOy:H、NiNxOy:H、NiCxNyOz:H、NixSiy以及NixGey。
12.根据权利要求10所述的竖直纳米线半导体装置，其中所述第一导电层、所述第二导电层以及所述半导体纳米线包含硅、硅锗以及锗中的一种。
13.根据权利要求11所述的竖直纳米线半导体装置，其中所述第一导电层、所述第二导电层以及所述半导体纳米线包含硅、硅锗以及锗中的一种。
14.根据权利要求10所述的竖直纳米线半导体装置，其中所述半导体纳米线包含用于P型金属氧化物半导体半导体装置的第一纳米线和用于N型金属氧化物半导体半导体装置的第二纳米线。
15.根据权利要求11所述的竖直纳米线半导体装置，其中所述P型金属氧化物半导体半导体装置和所述N型金属氧化物半导体半导体装置中的每一个具有多沟道结构，所述多沟道结构具有多个纳米线。
CN201980021545.1A 2018-03-23 2019-03-05 竖直纳米线半导体装置和其制造方法 Pending CN111902944A (zh)

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