CN111902943A - 用于制造单粒纳米线的方法以及用于利用所述单粒纳米线制造半导体装置的方法 - Google Patents

用于制造单粒纳米线的方法以及用于利用所述单粒纳米线制造半导体装置的方法 Download PDF

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CN111902943A
CN111902943A CN201980021414.3A CN201980021414A CN111902943A CN 111902943 A CN111902943 A CN 111902943A CN 201980021414 A CN201980021414 A CN 201980021414A CN 111902943 A CN111902943 A CN 111902943A
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semiconductor
nanowire
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CN111902943B (zh
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洪瑛
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  • Recrystallisation Techniques (AREA)

Abstract

本发明公开一种用于利用半导体纳米线制造半导体装置的方法。半导体制造方法通过执行以下各项来在衬底上形成横向延伸的单粒半导体纳米线：在衬底上形成平行于衬底横向延伸的半导体纳米线的步骤；形成用以覆盖半导体纳米线的覆盖层的步骤；图案化覆盖层以形成沟槽的步骤，沟槽通过其内壁暴露半导体纳米线的一个端部；形成与半导体纳米线的端部部分接触的催化材料层的步骤；以及通过热处理进行的金属诱导结晶(MIC)。

Description

用于制造单粒纳米线的方法以及用于利用所述单粒纳米线制 造半导体装置的方法
技术领域
本公开涉及一种制造单晶粒纳米线的方法以及一种使用所述单晶粒纳米线制造半导体装置的方法。
背景技术
高性能半导体装置提高电子产品的质量并带来成本方面的好处。这种半导体装置需要具有高迁移率和可靠性的半导体沟道，且确切地说，由于半导体沟道具有某些特性，因此有必要减小特性扩散。
有源矩阵有机发光二极管(active-matrix organic light-emitting diode，AM-OLED)显示器主要应用于最近的智能手机的移动装置。作为这种AM-OLED显示器的像素开关元件，即使在高度整合的情况下仍具有高迁移率和高可靠性的低温多晶硅薄膜晶体管(lowtemperature polycrystalline silicon thin film transistor，LTPS TFT)为合适的。
准分子激光退火(Excimer Laser Annealing，ELA)主要应用于制造低温多晶硅薄膜晶体管(LTPS TFT)以用于硅的结晶。LTPS TFT的缺点为其在应用于大面积显示器时难以维持一定的晶粒均匀度，且良率较低。
发明内容
技术问题
示范性实施例提出一种使用MIC技术制造朝向<111>方向的高质量单晶粒纳米线的方法。
示范性实施例提出一种制造其中晶粒相对于衬底在横向方向上生长的单晶粒纳米线的方法，以及一种应用所述单晶粒纳米线的半导体装置的方法。
问题的技术解决方案
根据示范性实施例，一种制造单晶粒纳米线的方法包含：在衬底上形成待结晶的非晶形沟道材料层；
图案化沟道材料层以在衬底上形成在横向方向上延伸的半导体纳米线；
形成覆盖半导体纳米线的上部的覆盖层；
图案化覆盖层和纳米线以形成暴露半导体纳米线的一个端部的侧表面的沟槽；
形成与半导体纳米线的一个端部的侧表面接触的催化剂材料层；以及
利用热处理执行金属诱导结晶(metal induced crystallization，MIC)，以使半导体纳米线在纳米线的长度方向上从半导体纳米线的与催化剂材料接触的一个端部结晶。
根据另一示范性实施例，一种制造纳米线半导体元件的方法包含：
在衬底上形成包含非晶形沟道材料层、非晶形导电半导体层以及金属层的多层膜；
图案化多层膜以在定义为晶体管区的部分中形成至少一个多层块，所述至少一个多层块包含纳米线沟道材料层、条型导电半导体层以及金属层；
形成覆盖多层块的覆盖层；
在覆盖层上形成具有内壁的沟槽，其中所述沟槽暴露沟道材料层的一个端部；
图案化覆盖层和沟道材料层以暴露沟道材料层的一个端部；
在覆盖层上且在沟槽内部形成催化剂材料层以使催化剂材料层与暴露于沟槽的内壁的沟道材料层的一个端部接触；
热处理多层膜以使沟道材料层结晶；以及
在移除覆盖金属层的覆盖层之后图案化金属层和导电半导体层，以形成与半导体材料层对应的源极和漏极以及源极电极和漏极电极。
根据示范性实施例，非晶形沟道材料层可由从由以下组成的群组中选出的任一个形成：Si、SiGe以及Ge。
根据示范性实施例，催化剂材料层可由从由以下组成的群组中选出的至少一个材料形成：Ni、NiOx、NiCxOy、NiNxOy、NiCxNyOz、NiCxOy:H、NiNxOy:H、NiCxNyOz:H、NixSiy以及NixGey。
根据示范性实施例，非晶形沟道材料层可由含有p型杂质或n型杂质的本征半导体材料或非本征半导体材料形成。
根据示范性实施例，形成多层块包含：
形成包含p型纳米线沟道材料层、n型导电半导体层以及金属层的第一多层块；以及
形成包含n型纳米线沟道材料层、p型导电半导体层以及金属层的第二多层块。
公开内容的有利效应
示范性实施例提出一种制造其中晶体在<111>方向上生长的横向半导体纳米线沟道的方法，以及一种通过应用所述横向半导体纳米线沟道来制造例如CMOS的半导体的方法。这一示范性实施例可通过在大面积衬底上制造高性能LSI、存储器、传感器等来实现系统面板(system on panel，SOP)。根据这一示范性实施例，并不需要用于形成导电层(例如源极/漏极)的离子注入和独立激活过程。因此，根据示范性实施例，有可能获得具有高迁移率、高可靠性以及小产品间特性分布的高良率半导体装置。
附图说明
图1到图7依序示出根据示范性实施例的横向纳米线半导体装置的制造过程。
图8示出根据示范性实施例的具有横向纳米线沟道的晶体管的示意性横截面结构。
图9到图28依序示出根据另一示范性实施例的制造具有横向纳米线沟道的半导体装置的过程。
具体实施方式
下文中将参考附图详细描述本发明的概念的优选实施例。然而，本发明的概念的实施例可以各种形式修改，且本发明的概念的范围不应解释为受限于下文所描述的实施例。本发明概念的实施例优选地解译为经提供以向所属领域的普通技术人员更充分地解释本发明概念。相同符号一直意指相同元件。此外，示意性地绘制图中的各种元件和区域。因此，本发明概念不受限于附图中所绘制的相对大小或间隔。
例如第一和第二的术语可用于描述各种组件，但所述组件并不受限于所述术语。仅出于区分一个组件与其它组件的目的使用术语。举例来说，在不脱离本发明概念的范围的情况下，第一组件可称为第二组件，且相反地，第二组件可称为第一组件。
本申请案中使用的术语仅用于描述特定实施例，且并不意欲限制本发明的概念。除非另外指定，否则单数形式的术语可包含复数形式。在本申请案中，例如“包含”或“具有”的表述意欲指示在说明书中描述的特征、数目、步骤、动作、组件、部分或其组合的存在，且应理解，并未预先地排除一个或多个其它特征或数目、操作、组件、部分或其组合的存在或添加的可能性。
除非另外定义，否则本文中所使用的所有术语(包含技术术语和科学术语)具有与本发明概念所属的领域的普通技术人员通常所理解的含义相同的含义。另外，按照词典中的定义，常用术语应解译为具有与所述术语在与其相关的技术的内容背景中的含义一致的含义，且应理解，除非本文中明确定义，否则所述术语不应以过于正式的意义解释。
当实施例可以不同方式实施时，特定处理次序可以与所描述次序不同地执行。举例来说，连续描述的两个过程可实质上同时执行或可以与所描述次序相反的次序执行。
举例来说，在附图中，取决于制造技术和/或公差，可预期所示出形状的变型。因此，本发明的实施例不应解释为受限于本说明书中示出的区的特定形状，且例如，应包含因制造过程引起的形状变化。如本文中所使用的所有术语“和/或”包含所提及组件中的一个或多个的每一个组合。另外，如本文中所使用的术语“衬底”可指衬底本身，或包含衬底与形成在其表面上的预定层或膜的层合结构。另外，在本说明书中，“衬底的表面”可意指衬底本身的暴露表面，或形成在衬底上的预定层或膜的外部表面。此外，描述为“上部”或“在…上”可不仅包含在正上方接触且还可包含在上方并不接触。
下文中，参考附图，制造过程图展示制造根据示范性实施例的横向半导体纳米线(lateral semiconductor nano-wire)的基本概念。
在下文所描述的图1到图7中，每一图中的(a)为横截面图，且每一图中的(b)为平面图。
如图1中所示，缓冲层(11)形成在衬底(10)上。缓冲层(11)可由例如SiO2或SiNx、SiONx、AlOx以及类似物的材料形成。
可通过已通过前一过程形成的多层结构的最顶部介电层(top-most dielectriclayer)来提供缓冲层(10)。
如图2中所示，待结晶的非晶形材料层(12)形成在缓冲层(11)上。非晶形材料层可由掺杂有p型杂质或n型杂质的本征半导体(intrinsic semiconductor)材料或非本征半导体(non-intrinsic semiconduc)材料形成。半导体材料层可由以下组成的群组中选出的任一个形成：Si、SiGe以及Ge，且在本发明实施例中，非晶形材料层(12)由非晶硅(a-Si)形成。根据另一实施例，非晶形材料层(12)可具有多层结构(multi-layered structure)，在多层结构中，p型半导体材料层与n型半导体材料层依序堆叠。
如图3中所示，非晶形材料层(12)经图案化以形成待平行地用作半导体装置的沟道的多个纳米线(12')。此处，纳米线(12')可用作多个晶体管、二极管以及传感器的沟道，且根据另一实施例，可针对一个半导体装置仅形成一个纳米线(12')。
如图4中所示，使用例如SiO2的绝缘材料来在纳米线(12')上形成覆盖层(13)。这一覆盖层(13)是用于使后续过程中形成的催化剂材料层与纳米线(12)分隔开并允许其部分地接触的保护层(protecting layer)。此处，在重复地沉积非晶形材料层/绝缘隔离层之后，多层非晶形材料层/绝缘层图案化，且执行图4的过程以形成多层纳米线。
如图5中所示，覆盖层(13)和纳米线(12')图案化为彼此正交，且仅暴露纳米线(12')的一个端部的侧截面的沟槽(14)形成至预定深度。。沟槽(14)可在缓冲层(11)的表面下方延伸预定深度。此时，可确定沟槽(140)的相对于缓冲层(11)的深度，使得待随后描述的催化剂材料层(15,图6)的表面定位在缓冲层(11)的表面下方且催化剂材料层(15)下方的弯曲部分从纳米线(12')的侧截面(12")向下偏离。沟槽(14)可形成为沿着纳米线(12')的布置方向正交于纳米线(12')的长度方向延伸。因此，多个纳米线(12')的一个端部的侧截面(12")暴露于沟槽(14)的细长的内壁(14a)。此处，侧截面(12")具有粗糙度较小的平滑表面为重要的，且垂直于侧截面(12")的法线(normal line)定向为平行于纳米线(12')的延伸方向为重要的。
此处，当仅一个纳米线(12')形成在衬底(10)上时，可应用与纳米线(12')的仅一个端部对应的沟槽。
如图6中所示，催化剂材料层(15)形成在覆盖层(13)上。催化剂材料层(15)具有几纳米的厚度，且同样形成在沟槽(14)内部。此处，催化剂材料层(15)在沟槽(14)的内壁(14a)处与纳米线(12')的一个端部的侧截面(12")接触。
如图7中所示，通过热处理执行金属诱导结晶(MIC)以使纳米线(12)的非晶硅(a-Si)结晶，从而形成单晶粒多晶硅(p-Si)。这种热处理可以在炉(furnace)中执行，且此时，可对炉施加电磁场(electromagnetic field)。根据热处理，通过与催化剂材料层反应来在纳米线(12')的一个侧截面(12")上产生NiSi2，且这种NiSi2诱导非晶硅的晶体生长同时沿着纳米线的长度方向行进。
利用如上文所描述的概念制造的单晶粒纳米线可应用于各种半导体装置，且取决于对应半导体装置的设计，有可能通过常规后续过程来制造所需半导体装置。
图8示出根据示范性实施例的具有横向纳米线沟道的晶体管的示意性横截面结构。
在图8中所示的纳米线晶体管中，缓冲层(21)形成在衬底(20)上，且纳米线沟道(22)形成为在缓冲层(21)上平行于衬底(20)的平面。
漏极区或源极区的第一导电层(23a)形成在纳米线沟道(22)的一个侧面上，且源极区或漏极区的第二导电层(23b)形成在纳米线沟道(22)的另一侧面上。
栅极(28)形成在第一导电层(23a)与第二导电层(23b)之间的沟道区上，且栅极绝缘层(27)形成在栅极(28)下方。
纳米线(22)为其中晶体在<111>方向上生长的单晶粒半导体，且这种单晶粒半导体可应用为各种半导体装置的组件。
下文中，将描述使用上述纳米线制造方法来制造CMOS半导体装置的方法的示范性实施例。
下文中，将基于上文所提及的示范性实施例来描述制造CMOS的方法。通过理解以下技术内容，可容易地推导出横向纳米线晶体管(lateral nano-wire transistor)的结构及其制造方法。在以下实施例中，将示范性地描述使用非晶硅作为半导体材料来制造硅纳米线CMOS装置的方法。
如图9中所示，缓冲层(101)形成在衬底(100)上。可通过已通过前一过程形成的多层结构的最顶部介电层(top-most dielectric layer)来提供缓冲层(101)。缓冲层(101)可由例如绝缘材料形成，所述绝缘材料例如SiO2、SiNx、SiONx或AlOx。
如图10中所示，形成多层膜(ML)，其包含处于缓冲层(101)上的呈非晶态的硅沟道材料层(102)和导电半导体层(103)以及处于导电半导体层(103)上的金属层(104)。
举例来说，多层膜(ML)可具有p a-Si/n+a-Si/TiN的多层结构，以用于获得具有p型硅沟道和处于p型硅沟道上的两侧上的n型导电半导体层的PMOS晶体管。
如图11中所示，在定义为第一晶体管的第一晶体管(T1)的区中，例如衬底上的PMOS晶体管区，通过经由应用光刻胶(photoresist，PR)掩模的常规图案化方法图案化多层膜(ML)来形成第一多层块(ML1)。通过图案化多层膜(ML)，第一多层块(ML1)仅保留在第一晶体管(T1)的区中，且其余部分中的衬底(100)上的缓冲层(101)暴露。此时，第一多层块(ML1)的每一层(确切地说，硅沟道材料层(102))具有纳米线形状作为p型沟道，且导电半导体层(103)和其上的金属层(104)也具有细窄条形的形状。
如图12中所示，在衬底(100)上的定义为第二晶体管(T2)的区域的部分中，用于形成第二晶体管(例如NMOS晶体管)的第二多层块(ML2)以与第一多层块(ML1)相同的形状形成。第二多层块(ML2)可具有用于NMOS晶体管的n a-Si/p+a-Si/TiN的多层结构。这一第二多层块(ML2)可通过与形成第一多层块(ML1)的过程类似的过程来获得，且具有其中纳米线硅沟道材料层(105)作为n型沟道且呈条形形状的导电半导体层(106)和金属层(107)从底部开始堆叠的结构。
如图13中所示，完全覆盖第一和第二多层块(ML1,ML2)的覆盖层(108)由例如SiO2的绝缘材料形成。
如图14中所示，如上文所描述的沟槽(109)形成在覆盖层(108)中。此时，沟槽(109)可形成为以与图5中所示的沟槽(14)相同的形状在缓冲层(101)的表面下方延伸预定深度，但在这一实施例的图中，为方便起见，展示沟槽(109)的底部形成为仅达到缓冲层(101)的表面。通过这种方式，可延伸到缓冲层(101)的沟槽(109)同时形成在第一多层块(ML1)和第二多层块(ML2)的一个侧面(图中在左边)上，且此时，第一多层块(ML1)和第二多层块(ML2)中的每一个的硅沟道材料层(102,105)的一个端部的侧截面(102a,105a)暴露于沟槽(109)的内侧表面(109a)。
如图15中所示，催化剂材料层(110)通过ALD方法或类似方法以几纳米的厚度形成在覆盖层(108)的表面上且形成在沟槽(109)的内部中。
催化剂材料可以是从由以下组成的群组中选出的任一个：Ni、NiOx、NiCxOy、NiNxOy、NiCxNyOz、NiCxOy:H、NiNxOy:H、NiCxNyOz:H、NixSiy以及NixGey。
在形成催化剂材料层(110)之后，利用热处理(heat treatment)执行金属诱导结晶(MIC)。热处理可以在炉(furnace)中执行，且可对炉施加电磁场。通过这种热处理，非晶形导电层(103)和非晶形半导体层(102)结晶以获得单晶粒的多晶导电层(103)和多晶半导体层(102)。
如图16中所示，在利用热处理获得多晶半导体层(102)之后，通过蚀刻来移除金属层104上的层合物。在图16中，表示出催化剂材料层(110)和催化剂材料层(110)下方的覆盖层(108)一起移除，且根据另一实施例，仅移除催化剂材料层109，且催化剂材料层109下方的覆盖层(108)可保持原样。
如图17中所示，导电半导体层(103,106)以及金属层(104,107)在对应的第一晶体管(T1)区和第二晶体管(T2)区中图案化，使得源极或漏极(103a,106a)、漏极或源极(103c,106c)以及源极电极或漏极电极(104a,107a)以及漏极电极或源极电极(104c,107c)形成在每一区中。
如图18中所示，栅极绝缘层(110)形成在源极电极或漏极电极(104a,107a)以及漏极电极或源极电极(104c,107c)上，且栅极(111,112)分别在第一晶体管(T1)和第二晶体管(T2)中的每一个的对应位置处形成在栅极绝缘层(110)上。
如图19中所示，覆盖整个晶体管结构的ILD层(116)形成在栅极(111,112)上。在ILD层(116)中，与第一晶体管(T1)和第二晶体管(T2)的源极、栅极以及漏极对应的多个接触孔(111a,111b,111c)(112a,112b,112c)由后续图案化工艺形成。
如图20中所示，通过接触孔(111a,111b,111c)(112a,112b,112c)电连接到其下方的源极电极或漏极电极(104a,107a)、漏极电极或源极电极(104c,107c)以及第一和第二晶体管(T1,T2)的栅极(104b,107b)的金属衬垫(113a,113b,113c)(114a,114b,114c)形成在ILD层(116)上，且钝化层(115)覆盖金属衬垫(113a,113b,113c)(114a,114b,114c)的上部。
在这一过程之后，可根据将应用的电子装置的设计来执行额外过程。
通过上述实施例示范性地描述的纳米线半导体装置具有单晶粒纳米线沟道，其中晶粒在平行于衬底安置的源极与漏极之间在横向方向上生长。当这种纳米线以薄鳍片形状形成时，可获得所谓的FIN晶体管。通过使用金属催化剂的MIC，这些纳米线具有在<111>方向上生长的单晶结构。
如果硅纳米线的晶体生长取决于MIC，那么可应用具有几纳米的厚度的由从由以下组成的群组中选出的至少一个形成的非晶形膜作为结晶催化剂层：NiOx、NiCxOy、NiNxOy、NiCxNyOz、NiCxOy:H、NiNxOy:H、NiCxNyOz:H、NixSiy以及NixGey。这种催化剂层的形成可通过ALD方法来沉积。在上述实施例的描述中，与沟道对应的硅沟道材料层可掺杂有已知n型非硫材料或p型非硫材料，且根据另一实施例，可由本征硅形成。
用于非晶硅的结晶的MIC热处理可以在炉(furnace)中执行，且可以利用电磁场(electromagnetic field)在炉(furnace)中执行。示范性实施例中描述的制造半导体纳米线的方法可应用于制造除晶体管之外的存储器装置和二极管的方法。
在上文所描述的实施例中，已描述应用硅作为源极区和漏极区中的导电层和沟道区的半导体材料的实例，但除硅之外，半导体材料可由SiGe、Ge以及类似物形成。
在上述实施例中，与纳米线沟道对应的栅极仅形成在一个侧面上。然而，通过修改上文所描述的过程中的一些，有可能获得例如具有完全包围纳米线的栅极全环栅极(gateall around gate)的纳米线晶体管的半导体装置。
根据另一示范性实施例，可基于上述方法获得多沟道(Multi-channel)环绕栅极纳米线晶体管半导体元件。
图21到图25示出具有环绕栅极的纳米线晶体管的制造过程的一部分。在每一图中，(a)为示意性竖直横截面图，且(b)为示意性透视图。
在图21中，包含多晶半导体层(102)、导电半导体层(103)以及金属层(104)的多层块(ML1)通过上文所描述的过程形成在衬底(100)上。图21对应于在上文所描述的实施例的描述中提及的图16。这一多层块(ML1)用于一个晶体管，且根据另一实施例，如在上文所描述的实施例中，可提供多个多层块。
如图22中所示，通过同时图案化多层块(ML1)的金属层(104)和金属层(104)下方的导电半导体层(103)，形成源极或漏极(103aa)和漏极或源极(103c)以及源极电极或漏极电极(104a)和漏极电极或源极电极(104c)。
如图23中所示，通过选择性蚀刻缓冲层(102)，与两侧上的源极区与漏极区之间的沟道区对应的缓冲层(101)的一部分蚀刻至预定深度，以形成空腔(101a)，使得多晶半导体层(102)的沟道区从装置板(100)浮置以形成桥形状的多晶半导体层(102)。
如图24中所示，通过ALD方法或类似方法形成包围多晶半导体层(102)的栅极绝缘层(110)。栅极绝缘层(110)也形成在空腔(101a)内部。
如图25中所示，在通过ALD方法或类似方法将栅极材料沉积在栅极绝缘层(110)上且图案化栅极材料之后，形成包围多晶半导体层(102)的沟道的环绕栅极(111a)。根据ALD方法，膜形成在暴露的多层结构的所有表面上，且所需材料膜可形成在空腔(101a)中。
在执行上述过程之后，通过通常已知额外过程完成目标半导体装置。
同时，在上文所描述的实施例中，已引入具有单一沟道的半导体装置，且可通过应用上文所描述的过程来制造多沟道半导体装置。
根据另一示范性实施例，通过应用上文所描述的图4和图5的过程的迭代过程，可形成多层纳米线堆叠。
如图26中所示，包含由待结晶材料制成的非晶形材料层(12)和覆盖非晶形材料层(12)的绝缘层(16)的夹层结构的堆叠形成在衬底(10)上的缓冲层(11)上。
如图27中所示，夹层结构的堆叠经图案化以形成其中多个纳米线(12')多重堆叠的多层纳米线(multi-layered nano-wire，MLN)。
如图28中所示，形成覆盖纳米线多层的覆盖层(13)，且通过如上文所描述的过程形成沟槽(14)。这一过程对应于上文所描述的图5中的过程。此后，通过图6和图7的过程获得多层多晶纳米线，且通过后续过程获得目标半导体装置。
根据另一示范性实施例，可基于上述方法在多晶硅衬底或非均质衬底上制造硅太阳能电池，且可通过制造3D堆叠结构来制造3D堆叠存储器，且各种装置可整合在单一衬底上。
为更好地理解，已参考图中所示的实施例描述根据本发明的一实施例的制造半导体装置的方法，但这仅为示范性的，且所属领域的普通技术人员将了解，由此可进行各种修改和等效的其它实施例。因此，本发明的真实技术防范范围应通过随附权利要求书确定。

Claims (12)

1.一种制造半导体纳米线的方法，所述方法包括：
在衬底上形成非晶形沟道材料层；
图案化所述沟道材料层以在所述衬底上形成在横向方向上延伸的半导体纳米线；
形成覆盖所述半导体纳米线的上部的覆盖层；
图案化所述覆盖层和所述纳米线以形成暴露所述半导体纳米线的一个端部的侧表面的沟槽；
形成与所述半导体纳米线的所述侧表面接触的催化剂材料层；以及
利用热处理执行金属诱导结晶(MIC)，以使所述半导体纳米线在所述纳米线的长度方向上从所述半导体纳米线的与所述催化剂材料接触的一个端部结晶。
2.根据权利要求1所述的制造半导体纳米线的方法，其中所述沟道材料层由以下组成的群组中选出的任一个形成：Si、SiGe以及Ge。
3.根据权利要求2所述的制造半导体纳米线的方法，其中所述催化剂材料层由以下组成的群组中选出的至少一个材料形成：Ni、NiOx、NiCxOy、NiNxOy、NiCxNyOz、NiCxOy:H、NiNxOy:H、NiCxNyOz:H、NixSiy以及NixGey。
4.根据权利要求3所述的制造半导体纳米线的方法，还包括在所述衬底与所述沟道材料层之间形成缓冲层。
5.根据权利要求1所述的制造半导体纳米线的方法，其中所述沟道材料层由本征半导体材料或非本征半导体材料形成。
6.一种制造纳米线半导体元件的方法，所述方法包括：
在衬底上形成包含非晶形沟道材料层、非晶形导电半导体层以及金属层的多层膜；
图案化所述多层膜以在定义为晶体管区的部分中形成至少一个多层块，所述至少一个多层块包含纳米线沟道材料层、条型导电半导体层以及金属层；
形成覆盖所述多层块的覆盖层；
形成在所述覆盖层上具有内壁的沟槽，其中所述沟槽暴露所述沟道材料层的一个端部的侧表面；
在所述覆盖层上且在所述沟槽内部形成催化剂材料层以使所述催化剂材料层与暴露于所述沟槽的所述内壁的所述沟道材料层的所述一个端部的所述侧表面接触；
热处理所述多层膜以使所述沟道材料层结晶；以及
在移除覆盖所述金属层的所述覆盖层之后图案化所述金属层和所述导电半导体层，以形成与所述半导体材料层对应的源极和漏极以及源极电极和漏极电极。
7.根据权利要求6所述的制造纳米线半导体元件的方法，其中形成所述多层块包括：
形成包含p型纳米线沟道材料层、n型导电半导体层以及金属层的第一多层块；以及
形成包含n型纳米线沟道材料层、p型导电半导体层以及金属层的第二多层块。
8.根据权利要求6所述的制造纳米线半导体元件的方法，其中所述沟道材料层由以下组成的群组中选出的任一个形成：Si、SiGe以及Ge。
9.根据权利要求8所述的制造纳米线半导体元件的方法，其中所述催化剂材料层由以下组成的群组中选出的至少一个材料形成：Ni、NiOx、NiCxOy、NiNxOy、NiCxNyOz、NiCxOy:H、NiNxOy:H、NiCxNyOz:H、NixSiy以及NixGey。
10.根据权利要求6所述的制造纳米线半导体元件的方法，其中所述催化剂材料层由以下组成的群组中选出的至少一个材料形成：Ni、NiOx、NiCxOy、NiNxOy、NiCxNyOz、NiCxOy:H、NiNxOy:H、NiCxNyOz:H、NixSiy以及NixGey。
11.根据权利要求6所述的制造纳米线半导体元件的方法，其中所述沟道材料层由本征半导体材料或非本征半导体材料形成。
12.根据权利要求7所述的制造纳米线半导体元件的方法，其中所述沟道材料层由本征半导体材料或非本征半导体材料形成。
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