CN111863711A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
CN111863711A
CN111863711A CN201910356555.2A CN201910356555A CN111863711A CN 111863711 A CN111863711 A CN 111863711A CN 201910356555 A CN201910356555 A CN 201910356555A CN 111863711 A CN111863711 A CN 111863711A
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Prior art keywords
contact hole
layer
dielectric layer
forming
gate
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CN201910356555.2A
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CN111863711B (zh
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金吉松
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201910356555.2A priority Critical patent/CN111863711B/zh
Priority to US16/537,158 priority patent/US10964593B2/en
Publication of CN111863711A publication Critical patent/CN111863711A/zh
Priority to US17/189,611 priority patent/US11508726B2/en
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Publication of CN111863711B publication Critical patent/CN111863711B/zh
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Abstract

一种半导体结构及其形成方法，形成方法包括：提供基底，基底上形成有栅极结构，栅极结构两侧的基底内形成有源漏掺杂层，栅极结构露出的基底上形成有初始介质层，初始介质层覆盖栅极结构顶部，源漏掺杂层顶部的初始介质层内形成有与源漏掺杂层电连接的源漏接触孔插塞；去除部分厚度初始介质层，形成介质层，露出源漏接触孔插塞的部分侧壁；至少在介质层露出的源漏接触孔插塞侧壁上形成刻蚀停止层；以相邻源漏接触孔插塞侧壁上的刻蚀停止层为横向停止位置，刻蚀栅极结构顶部的介质层，形成露出栅极结构顶部的栅极接触孔；在栅极接触孔内形成与栅极结构电连接的栅极接触孔插塞。本发明实施例有利于增大形成有源栅极接触孔插塞的工艺窗口。

Description

半导体结构及其形成方法
技术领域
本发明实施例涉及半导体制造领域，尤其涉及一种半导体结构及其形成方法。
背景技术
随着集成电路制造技术的不断发展，人们对集成电路的集成度和性能的要求变得越来越高。为了提高集成度，降低成本，元器件的关键尺寸不断变小，集成电路内部的电路密度越来越大，这种发展使得晶圆表面无法提供足够的面积来制作所需要的互连线。
为了满足关键尺寸缩小过后的互连线所需，目前不同金属层或者金属层与基底的导通是通过互连结构实现的。互连结构包括互连线和形成于接触开口内的接触孔插塞。接触孔插塞与半导体器件相连接，互连线实现接触孔插塞之间的连接，从而构成电路。
晶体管结构内的接触孔插塞包括位于栅极结构表面的栅极接触孔插塞，用于实现栅极结构与外部电路的连接，还包括位于源漏掺杂层表面的源漏接触孔插塞，用于实现源漏掺杂层与外部电路的连接。
目前，为实现晶体管面积的进一步缩小，引入了有源栅极接触孔插塞(ContactOver Active Gate，COAG)工艺。与传统的栅极接触孔插塞位于隔离区域的栅极结构上方相比，COAG工艺能够把栅极接触孔插塞做到有源区(Active Area，AA)的栅极结构上方，从而进一步节省芯片的面积。
发明内容
本发明实施例解决的问题是提供一种半导体结构及其形成方法，增大形成COAG的工艺窗口。
为解决上述问题，本发明实施例提供一种半导体结构的形成方法，包括：提供基底，所述基底上形成有栅极结构，所述栅极结构两侧的基底内形成有源漏掺杂层，所述栅极结构露出的基底上形成有初始介质层，所述初始介质层覆盖所述栅极结构顶部，所述源漏掺杂层顶部的初始介质层内形成有源漏接触孔插塞，所述源漏接触孔插塞与所述源漏掺杂层电连接；去除部分厚度的所述初始介质层，形成介质层，露出所述源漏接触孔插塞的部分侧壁；至少在所述介质层所露出的源漏接触孔插塞的侧壁上形成刻蚀停止层；以相邻所述源漏接触孔插塞侧壁上的刻蚀停止层为侧向刻蚀停止位置，刻蚀所述栅极结构顶部的介质层，形成露出所述栅极结构顶部的栅极接触孔；在所述栅极接触孔内形成栅极接触孔插塞，所述栅极接触孔插塞与所述栅极结构电连接。
相应的，本发明实施例还提供一种半导体结构，包括：基底；栅极结构，位于所述基底上；源漏掺杂层，位于所述栅极结构两侧的基底内；介质层，位于所述栅极结构露出的基底上，所述介质层覆盖所述栅极结构顶部；源漏接触孔插塞，位于所述源漏掺杂层顶部的所述介质层内，所述源漏接触孔插塞和所述源漏掺杂层电连接，且所述源漏接触孔插塞顶部高于所述介质层顶部；刻蚀停止层，至少位于所述介质层所露出的源漏接触孔插塞的侧壁上；栅极接触孔，位于相邻所述源漏接触孔插塞侧壁上的刻蚀停止层之间的介质层内，所述栅极接触孔露出所述栅极结构顶部。
与现有技术相比，本发明实施例的技术方案具有以下优点：
本发明实施例形成露出所述源漏接触孔插塞部分侧壁层的介质层后，至少在所述介质层所露出的源漏接触孔插塞的侧壁上形成刻蚀停止层，所述刻蚀停止层能够在后续形成栅极接触孔的步骤中，定义所述栅极接触孔刻蚀工艺的侧向刻蚀停止位置，防止所述栅极接触孔刻蚀工艺对所述源漏接触孔插塞造成损耗，从而降低了形成栅极接触孔的难度，相应地，后续在所述栅极接触孔内形成栅极接触孔插塞后，所述刻蚀停止层能够定义源漏接触孔插塞与栅极接触孔插塞之间的间距以及实现两者之间的隔离，从而在防止栅极接触孔插塞与所述源漏接触孔插塞发生短接的问题的同时，使所述栅极接触孔插塞能够形成于相邻所述源漏接触孔插塞之间，有利于增大形成有源栅极接触孔插塞(Contact OverActive Gate，COAG)的工艺窗口。
附图说明
图1至图7是一种半导体结构的形成方法中各步骤对应的结构示意图；
图8至图18是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
具体实施方式
目前形成的COAG的工艺窗口较小、工艺难度较大。现结合一种半导体结构的形成方法分析工艺窗口较小、工艺难度较大的原因。
参考图1至图7，示出了一种半导体结构的形成方法中各步骤对应的结构示意图。
参考图1，提供基底1，所述基底1上形成有栅极结构2，所述栅极结构2的顶部上形成有自对准停止层3，所述栅极结构2两侧的基底1内形成有源漏掺杂层4，所述栅极结构2露出的基底1上形成有底部介质层5，所述底部介质层5露出所述自对准停止层3顶部，所述源漏掺杂层4顶部的底部介质层5内形成有源漏接触孔插塞6，所述源漏接触孔插塞6与源漏掺杂层4电连接。
参考图2，去除部分厚度的所述源漏接触孔插塞6，在所述底部介质层5内形成凹槽(图未示)；在所述凹槽中形成保护层7。
参考图3，形成顶部介质层8，覆盖所述自对准停止层3、保护层7和底部介质层5；在所述顶部介质层8上形成具有掩膜开口9的硬掩膜层10。
参考图4，以所述硬掩膜层10为掩膜，刻蚀部分厚度的所述顶部介质层8，在所述顶部介质层8中形成沟槽11。
参考图5，以所述硬掩膜层10为部分掩膜，刻蚀部分所述源漏接触孔插塞6顶部的顶部介质层8和保护层7，形成露出源漏接触孔插塞6顶部的通孔12。
参考图6，形成所述通孔12后，以所述硬掩膜层10为部分掩膜，刻蚀部分所述栅极结构2顶部的顶部介质层8和自对准停止层3，形成露出所述栅极结构2顶部的栅极接触孔13。
参考图7，形成填充所述栅极接触孔13、通孔12和沟槽11的导电材料层(未标示)，位于所述栅极接触孔13内的导电材料层用于作为栅极接触孔插塞14，所述栅极接触孔插塞14与栅极结构2电连接，位于所述通孔12内的导电材料层用于作为通孔互连结构15，所述通孔互连结构15与源漏接触孔插塞6电连接，位于所述沟槽11内的导电材料层用于作为互连线16，所述互连线16与栅极接触孔插塞14以及通孔互连结构15电连接。
所述形成方法中采用双大马士革工艺形成所述栅极接触孔插塞14，即在同一步骤中形成所述栅极接触孔插塞14、通孔互连结构15以及所述互连线16，有利于形成多层高密度的金属连线从而使集成电路更先进更高效，而且，互连线16的延伸方向通常与栅极结构2的延伸方向相垂直，通过双大马士革工艺能够精确定位所述通孔12的形成位置。
但是，双大马士革工艺为对掩膜材料以及刻蚀工艺的要求比较高，工艺难度和复杂度比较大。比如说：所述形成方法在形成通孔12的步骤中，需满足以下条件：为保证硬掩膜层10能够起到部分刻蚀掩膜的作用，通孔刻蚀工艺对保护层7和硬掩膜层10的刻蚀选择比较大，同时，为保证自对准停止层3能够起到通孔刻蚀工艺的自对准作用，通孔刻蚀工艺对保护层7和自对准停止层3的刻蚀选择比也较大；在形成栅极接触孔13的步骤中，需满足以下条件：为保证硬掩膜层10能够起到部分刻蚀掩膜的作用，栅极接触孔刻蚀工艺对自对准停止层3和硬掩膜层10的刻蚀选择比较大，同时，为保证保护层7对源漏接触孔插塞6的保护作用，栅极接触孔刻蚀工艺对自对准停止层3和保护层7的刻蚀选择比也较大。
在实际工艺中，硬掩膜层10、保护层7以及自对准停止层3的材料通常难以同时满足以上所有条件，形成栅极接触孔13的工艺难度较大，相应的，形成COAG的工艺窗口较小。例如：硬掩膜层10的材料通常为氮化钛，自对准停止层3的材料通常为氮化硅，保护层7的材料通常为碳化硅。氮化硅材料与碳化硅材料中的任一种材料和氮化钛材料的刻蚀选择比都比较大，能够保证硬掩膜层10在通孔刻蚀工艺和栅极接触孔刻蚀工艺中起到相应的掩膜作用；氮化硅材料和碳化硅材料的刻蚀选择比也比较大，能够保证栅极接触孔刻蚀工艺对保护层7的损耗较小；但是，碳化硅材料和氮化硅材料的刻蚀选择比较小，通孔刻蚀工艺容易对自对准停止层3产生损耗，进而容易导致通孔互连结构15与不需电连接的栅极结构2之间的距离过近，通孔互连结构15与栅极结构2发生短接问题的概率较高，从而导致工艺窗口、生产良率的降低。
为了解决所述技术问题，本发明实施例中刻蚀停止层能够在形成栅极接触孔的步骤中，定义栅极接触孔刻蚀工艺的侧向刻蚀停止位置，防止栅极接触孔刻蚀工艺对源漏接触孔插塞造成损耗，降低了形成栅极接触孔的难度，后续在栅极接触孔内形成栅极接触孔插塞后，刻蚀停止层也能够定义源漏接触孔插塞与栅极接触孔插塞之间的间距以及实现两者之间的隔离，从而在防止栅极接触孔插塞与源漏接触孔插塞发生短接问题的同时，使栅极接触孔插塞能够形成于相邻源漏接触孔插塞之间，有利于增大形成有源栅极接触孔插塞的工艺窗口。
为使本发明实施例的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图8至图18是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
参考图8，提供基底50，所述基底50上形成有栅极结构51，所述栅极结构51两侧的基底50内形成有源漏掺杂层52，所述栅极结构51露出的基底50上形成有初始介质层53，所述初始介质层53覆盖所述栅极结构51顶部，所述源漏掺杂层52顶部的初始介质层53内形成有源漏接触孔插塞54，所述源漏接触孔插塞54与所述源漏掺杂层52电连接。
所述基底50用于为后续工艺制程提供工艺平台。
本实施例中，所述基底50用于形成鳍式场效应晶体管(FinFET)。因此，所述基底包括衬底501以及凸出于所述衬底501的鳍部502。在其他实施例中，当所述基底用于形成平面型场效应晶体管时，所述基底相应仅包括衬底。
本实施例中，所述衬底501为硅衬底。在其他实施例中，所述衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料，所述衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。所述衬底的材料可以是适宜于工艺需要或易于集成的材料。
本实施例中，所述鳍部502与衬底501的材料相同，所述鳍部502的材料为硅。在其他实施例中，所述鳍部的材料还可以是锗、锗化硅、碳化硅、砷化镓或镓化铟等适宜于形成鳍部的半导体材料。
本实施例中，所述鳍部502露出的衬底501上还形成有隔离层55，覆盖鳍部502的部分侧壁。所述隔离层55用于对相邻器件之间起到隔离作用。
本实施例中，所述隔离层55的材料为氧化硅。在其他实施例中，所述隔离层的材料还可以是氮化硅或氮氧化硅等其他绝缘材料。
所述栅极结构51用于控制半导体器件工作时，导电沟道的开启或关断。
本实施例中，采用后栅(gate-last)工艺形成所述栅极结构51，所述栅极结构51相应为金属栅结构，所述栅极结构51包括高k栅介质层(图未示)以及位于所述高k栅介质层上的栅电极层(图未示)。
本实施例中，所述高k栅介质层的材料为高k介质材料；其中，高k介质材料是指相对介电常数大于氧化硅相对介电常数的介电材料。具体地，所述高k栅介质层的材料为HfO2。在其他实施例中，所述高k栅介质层的材料还可以选自ZrO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO或Al2O3等。
所述栅电极层的材料为Al、Cu、Ag、Au、Pt、Ni、Ti或W。本实施例中，所述栅电极层的材料为W。
本实施例中，沿鳍部502的延伸方向，位于鳍部502边缘处的栅极结构51用于作为伪栅(dummy gate)。相应地，后续伪栅顶部不需形成栅极接触孔插塞。
本实施例中，栅极结构51的侧壁上还形成有侧墙56。侧墙56用于定义源漏掺杂层52的形成区域，侧墙56还用于在工艺制程中保护栅极结构51的侧壁。
所述侧墙56的材料可以为氧化硅、氮化硅、氮氧化硅、碳化硅、碳氮氧化硅、碳氧化硅、氮化硼和碳氮化硼中的一种或多种，所述侧墙56可以为单层结构或叠层结构。本实施例中，所述侧墙56为叠层结构。具体地，侧墙56为ONO(Oxide Nitride Oxide，氧化物-氮化物-氧化物)结构，侧墙56包括位于所述栅极结构51侧壁上的第一侧墙(图未示)、位于第一侧墙侧壁上的第二侧墙(图未示)以及位于所述第二侧墙侧壁上的第三侧墙(图未示)。相应地，第一侧墙的材料为氧化硅，第二侧墙的材料为氮化硅，第三侧墙的材料为氧化硅。
本实施例中，所述源漏掺杂层52位于所述栅极结构51两侧的鳍部502内。
当形成NMOS晶体管时，所述源漏掺杂层52包括掺杂有N型离子的应力层，所述应力层的材料为Si或SiC，所述应力层为NMOS晶体管的沟道区提供拉应力作用，从而有利于提高NMOS晶体管的载流子迁移率，其中，所述N型离子为P离子、As离子或Sb离子。当形成PMOS晶体管时，所述源漏掺杂层52包括掺杂有P型离子的应力层，所述应力层的材料为Si或SiGe，所述应力层为PMOS晶体管的沟道区提供压应力作用，从而有利于提高PMOS晶体管的载流子迁移率，其中，所述P型离子为B离子、Ga离子或In离子。
本实施例中，相邻的栅极结构51共用一个源漏掺杂层52。
本实施例中，所述基底50上还形成有覆盖栅极结构51侧壁、以及栅极结构51所露出基底50的接触孔刻蚀阻挡层(Contact Etch Stop Layer，CESL)59。
在形成源漏接触孔插塞54的刻蚀工艺中，接触孔刻蚀阻挡层59用于定义该刻蚀工艺的纵向刻蚀停止位置，减小源漏掺杂层52在该刻蚀工艺中受损的概率。因此，源漏接触孔插塞54还贯穿源漏掺杂层52上的接触孔刻蚀阻挡层59。
本实施例中，所述接触孔刻蚀阻挡层59的材料为氮化硅。
本实施例中，所述基底50上还形成有底部介质层57，露出所述栅极结构51的部分侧壁。具体地，所述底部介质层57露出所述源漏掺杂层52顶部。所述底部介质层57用于实现相邻器件之间、以及相邻栅极结构51之间的隔离。
为此，所述底部介质层57的材料为介电材料，例如氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅和碳氮氧化硅中的一种或多种。本实施例中，所述底部介质层57的材料为氧化硅。
本实施例中，所述基底50上还形成有顶部介质层60，覆盖所述底部介质层57且露出所述栅极结构51的顶部。
所述顶部介质层60与所述底部介质层57构成层间介质层(InterLayerDielectric，ILD)，从而实现相邻器件之间的隔离。所述顶部介质层60还用于为形成源漏接触孔插塞54提供工艺平台。
为此，所述顶部介质层60的材料为介电材料，例如氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅和碳氮氧化硅中的一种或多种。本实施例中所述顶部介质层60与底部介质层57的材料相同，所述顶部介质层60的材料为氧化硅。
所述初始介质层53用于实现源漏接触孔插塞54和后续栅极接触孔插塞之间的电隔离，所述初始介质层53还用于为形成所述源漏接触孔插塞54、以及后续形成栅极接触孔插塞提供工艺平台。
为此，初始介质层53的材料也为介电材料。本实施例中，为提高工艺兼容性初始介质层53与顶部介质层60的材料相同，初始介质层53的材料为氧化硅。
所述源漏接触孔插塞54用于实现所述源漏掺杂层52与其他互连结构或外部电路的电连接。
本实施例中，源漏接触孔插塞54的材料为铜。铜的电阻率较低，有利于改善后段RC的信号延迟，提高芯片的处理速度，同时还有利于降低源漏接触孔插塞54的电阻，相应降低了功耗。在其他实施例中，接触孔插塞的材料还可以为钨或钴。
形成所述源漏接触孔插塞54的步骤通常包括：刻蚀所述初始介质层53、相邻所述栅极结构51侧壁之间的层间介质层，形成露出所述源漏掺杂层52顶部的源漏接触孔(图未示)；在所述源漏接触孔内形成导电材料层(图未示)，所述导电材料层还覆盖初始介质层53的顶部；以所述初始介质层53顶面为停止位置，平坦化所述导电材料层，剩余导电材料层作为所述源漏接触孔插塞54。
本实施例中，所述底部介质层57露出的栅极结构51侧壁上还形成有自对准停止层58。形成所述源漏接触孔插塞54的刻蚀工艺中，相邻栅极结构51侧壁上的自对准停止层58用于定义沿垂直于栅极结构51侧壁方向上的刻蚀停止位置，从而实现该刻蚀工艺的自对准，进而能够形成所述源漏接触孔插塞54。相应地，所述源漏接触孔插塞54为自对准接触孔插塞。
所述自对准停止层58的材料可以为氮化硅、氧化铝、氮化铝或NDC(Nitride DopedCarbon)。所述层间介质层和初始介质层53与所述材料均具有较大的刻蚀选择比，从而能够保证所述自对准停止层58能够起到相应的工艺效果。本实施例中，所述自对准停止层58的材料为氮化硅。氮化硅材料为半导体工艺中常用的材料，有利于提高工艺兼容性。
在其他实施例中，还可以在所述栅极结构顶部形成自对准停止层。相应地，所述自对准停止层和所述侧墙可以在形成源漏接触孔的刻蚀工艺中，实现该刻蚀工艺的自对准。
参考图9，去除部分厚度的所述初始介质层53，形成介质层61，露出所述源漏接触孔插塞54的部分侧壁。
所述介质层61露出源漏接触孔插塞54的部分侧壁，从而为后续形成刻蚀停止层作准备。
所述介质层61顶部至所述源漏接触孔插塞54顶部的距离不宜过小，也不宜过大。如果所述距离过小，则所述介质层61露出的源漏接触孔插塞54的高度过小，后续在介质层61露出的源漏接触孔插塞54侧壁上形成刻蚀停止层后，容易导致刻蚀停止层的高度相应过小，所述刻蚀停止层难以起到定义后续栅极接触孔刻蚀工艺的侧向停止位置的作用；如果所述距离过大，则所述初始介质层53去除量相应过大，容易增加工艺风险、降低稳定性，例如：容易导致刻蚀速率均一性较差，进而导致所述介质层61顶面的平坦度较差，而且，容易导致所述介质层61的厚度过小，后续在介质层61内形成与栅极结构51电连接的栅极接触孔插塞后，所述栅极接触孔插塞的高度也过小。为此，本实施例中，所述介质层61顶部至源漏接触孔插塞54顶部的距离为50埃米至300埃米。
本实施例中，采用干法刻蚀工艺刻蚀去除部分厚度的初始介质层53。干法刻蚀工艺具有各向异性刻蚀的特性，有利于精确控制初始介质层53的刻蚀量，使介质层61顶部至源漏接触孔插塞54顶部的距离满足工艺需求，且有利于提高介质层61顶面的形貌质量。
参考图10，至少在所述介质层61所露出的源漏接触孔插塞54的侧壁上形成刻蚀停止层62。
所述刻蚀停止层62能够在后续形成栅极接触孔的刻蚀工艺中，定义该刻蚀工艺的侧向刻蚀停止位置，防止栅极接触孔刻蚀工艺对源漏接触孔插塞54造成损耗，降低了形成栅极接触孔的难度，相应地，后续在栅极接触孔内形成栅极接触孔插塞后，刻蚀停止层62能够定义源漏接触孔插塞54与栅极接触孔插塞之间的间距以及实现两者之间的隔离，因此，通过刻蚀停止层62，能够在防止后续栅极接触孔插塞与源漏接触孔插塞54发生短接问题的同时，使栅极接触孔插塞能够形成于相邻源漏接触孔插塞54之间，从而增大了形成有源栅极接触孔插塞的工艺窗口；而且，与采用双大马士革的方案形成COAG的方案相比，本实施例的工艺步骤简单、工艺难度低，有利于简化流程。
其中，所述侧向刻蚀停止位置指的是：后续形成栅极接触孔的刻蚀步骤中，沿平行于所述基底50表面方向的刻蚀停止位置。
为保证刻蚀停止层62能够起到定义栅极接触孔刻蚀工艺的侧向刻蚀停止位置的作用，刻蚀停止层62材料为与介质层61材料具有较大刻蚀选择性的材料。刻蚀停止层62的材料可以为氮化硅或碳化硅。介质层61与所述材料的刻蚀选择比较大，有利于保证刻蚀停止层62用于定义侧向刻蚀停止位置的作用。
本实施例中，所述刻蚀停止层62的材料为氮化硅。氮化硅材料为半导体工艺中常用的材料，工艺兼容性高。
在其他实施例中，当栅极结构顶部形成有自对准停止层时，后续形成栅极接触孔的步骤中，刻蚀栅极结构顶部的介质层后，还包括：刻蚀栅极结构顶部的自对准停止层。相应地，为保证刻蚀停止层用于定义栅极接触孔刻蚀工艺的侧向刻蚀停止位置的作用，刻蚀自对准停止层的步骤中，自对准停止层的材料与刻蚀停止层材料的刻蚀选择比大于或等于5：1。
本实施例中，所述刻蚀停止层62保形覆盖介质层61所露出的源漏接触孔插塞54的顶部和侧壁、以及介质层61的顶部。其中，位于所述源漏接触孔插塞54顶部的刻蚀停止层62能够在后续工艺中保护所述源漏接触孔插塞54的顶部；位于所述介质层61顶部的刻蚀停止层62能够在后续形成栅极接触孔插塞的平坦化工艺中，定义平坦化工艺的停止位置。
本实施例中，采用原子层沉积(Atomic Layer Deposition，ALD)工艺形成刻蚀停止层62。原子层沉积工艺包括进行多次的原子层沉积循环，以形成所需厚度的薄膜。通过选用原子层沉积工艺，有利于提高刻蚀停止层62的厚度均一性和致密度，且使刻蚀停止层62的厚度能够得到精确控制；此外，原子层沉积工艺的间隙填充性能和阶梯覆盖性好，相应提高了刻蚀停止层62在介质层61顶部、以及介质层61所露出的源漏接触孔插塞54顶部和侧壁的保形覆盖能力。
所述刻蚀停止层62不宜过薄，也不宜过厚。如果所述刻蚀停止层62过薄，不仅容易导致所述刻蚀停止层62的厚度小于后续栅极接触孔刻蚀工艺的对准偏差，而且容易导致所述刻蚀停止层62在后续栅极接触孔刻蚀工艺中，被过早的去除，上述两种情况均会导致所述刻蚀停止层62用于定义栅极接触孔刻蚀工艺的横向停止位置的效果不佳；如果所述刻蚀停止层62过厚，不仅容易造成工艺时间和材料的浪费，还容易导致相邻源漏接触孔插塞54侧壁上的刻蚀停止层62之间的剩余空间过小，或者，容易导致相邻源漏接触孔插塞54侧壁上的刻蚀停止层62相接触，从而增加后续形成栅极接触孔的工艺难度。为此，本实施例中，所述刻蚀停止层62的厚度为50埃米至300埃米。
参考图11至图12，以相邻所述源漏接触孔插塞54侧壁上的刻蚀停止层62为侧向刻蚀停止位置，刻蚀所述栅极结构51顶部的介质层61，形成露出所述栅极结构51顶部的栅极接触孔200(如图12所示)。
刻蚀所述栅极结构51顶部的介质层61的步骤中，所述刻蚀停止层62能够定义刻蚀工艺的侧向刻蚀停止位置，即使栅极接触孔刻蚀工艺出现对准偏差(overlay shift)时，也难以对源漏接触孔插塞54造成损耗，因此，能够防止所述栅极接触孔200露出源漏接触孔插塞54，从而防止后续栅极接触孔插塞与源漏接触孔插塞54发生短接的问题，降低了形成栅极接触孔200的工艺难度，同时使栅极接触孔能够形成于相邻所述源漏接触孔插塞54之间，即后续栅极接触孔插塞能够形成于有源区的栅极结构51上方，从而增大了形成有源栅极接触孔插塞的工艺窗口；而且，与采用双大马士革的方案形成COAG的方案相比，本实施例的工艺步骤简单、工艺难度低，有利于简化流程、节约成本。
本实施例中，形成所述栅极接触孔200的步骤包括：
如图11所示，形成覆盖所述刻蚀停止层62的掩膜层64。本实施例中，所述掩膜层64的材料为光刻胶。
本实施例中，形成所述掩膜层64之前，还包括：形成覆盖所述刻蚀停止层62的平坦化层63。所述平坦化层63用于提供平坦的表面，从而为形成所述掩膜层64做准备。
本实施例中，所述平坦化层63的材料为旋涂碳(spin on carbon，SOC)材料。相应地，采用旋涂工艺形成所述平坦化层63。
如图12所示，图形化所述掩膜层64，在掩膜层64中形成掩膜开口100；以掩膜层64为掩膜，以相邻源漏接触孔插塞54侧壁上的刻蚀停止层62为横向停止位置，刻蚀所述掩膜开口100露出的介质层61，形成所述栅极接触孔200。
本实施例中，所述掩膜层64的材料为光刻胶，图形化所述掩膜层64的工艺相应为光刻工艺。
本实施例中，采用干法刻蚀工艺刻蚀所述掩膜开口100露出的所述介质层61。干法刻蚀工艺为各向异性刻蚀工艺，且具有较好的剖面控制特性，有利于使所述栅极接触孔200的剖面满足工艺要求。
本实施例中，刻蚀所述掩膜开口100露出的所述介质层61之前，还包括：依次刻蚀所述掩膜开口100露出的平坦化层63和所述栅极结构51顶部的介质层61顶部的刻蚀停止层62。
具体地，通过调整所述干法刻蚀工艺的刻蚀气体类型和工艺参数，从而在同一刻蚀机台中，刻蚀所述平坦化层63、刻蚀停止层62以及所述介质层61。
结合参考图13，形成所述栅极接触孔200后，还包括：去除所述掩膜层64和平坦化层63。具体地，采用灰化工艺去除所述掩膜层64和平坦化层63。
在其他实施例中，当栅极结构顶部形成有自对准停止层时，形成所述栅极接触孔的步骤还包括：刻蚀栅极结构顶部的介质层后，刻蚀所述自对准停止层。
参考图14至图18，在所述栅极接触孔200内形成栅极接触孔插塞66(如图18所示)，所述栅极接触孔插塞66与所述栅极结构51电连接。所述栅极接触孔插塞66用于实现栅极结构51与其他互连结构或外部电路的电连接。
由前述可知，所述栅极接触孔200露出所述源漏接触孔插塞54的概率较小，因此，所述栅极接触孔插塞66能够形成于相邻源漏接触孔插塞54之间，且所述栅极接触孔插塞66与源漏接触孔插塞54发生短接问题的概率较低，从而增大了形成有源栅极接触孔插塞(COAG)的工艺窗口。
与栅极接触孔插塞位于隔离区的栅极结构上方的方案相比，本实施例所述栅极接触孔插塞66形成于有源区的栅极结构51上方，因此，省去了栅极结构51位于隔离区的部分，有利于节省芯片的面积，实现芯片尺寸的进一步缩小。
本实施例中，所述栅极接触孔插塞66的材料为铜。铜的电阻率较低，有利于改善后段RC的信号延迟，提高芯片的处理速度，同时还有利于降低所述栅极接触孔插塞66的电阻，相应降低了功耗。在其他实施例中，所述栅极接触孔插塞的材料还可以为钨或钴。
本实施例中，形成所述栅极接触孔插塞66的步骤包括：如图14所示，形成填充所述栅极接触孔200的导电材料层65，所述导电材料层65还覆盖所述源漏接触孔插塞54和介质层61顶部的刻蚀停止层62；如图15所示和图16所示，图15是俯视图，图16是图15沿AA1割线的剖面图，以所述介质层61顶部的刻蚀停止层62顶面为停止位置，对导电材料层65进行第一平坦化处理。
本实施例中，采用电镀(Electroplating，ECP)工艺形成所述导电材料层65。在其他实施例中，还可以采用化学气相沉积工艺形成所述导电材料层。
本实施例中，采用化学机械研磨工艺进行所述第一平坦化处理，有利于提高后续栅极接触孔插塞顶面的平坦度。其中，进行所述第一平坦化处理的步骤中，还对所述源漏接触孔插塞54顶面和侧壁上的刻蚀停止层62、以及源漏接触孔插塞54进行平坦化处理。
本实施例中，进行所述第一平坦化处理的步骤中，所述介质层61顶部的刻蚀停止层62能够定义平坦化处理的停止位置，有利于提高所述第一平坦化处理后，所述导电材料层65和源漏接触孔插塞54顶部的平坦度。
需要说明的是，结合参考图17至图18，图17是基于图15的俯视图，图18是图17沿AA1割线的剖面图，形成所述栅极接触孔插塞66的步骤还包括：进行所述第一平坦化处理后，以所述介质层61顶面为停止位置，对导电材料层65进行第二平坦化处理，剩余导电材料层65用于作为所述栅极接触孔插塞66。其中，进行第二平坦化处理的步骤中，去除了介质层61顶部的刻蚀停止层62。
为方便示意和描述，仅在图17中示意出了一根栅极接触孔插塞66和与该栅极接触孔插塞66相邻的两根源漏接触孔插塞54。在其他实施例中，根据实际工艺，所述栅极接触孔插塞和源漏接触孔插塞的数量还可以为其他数值。
本实施例中，以所述栅极接触孔插塞66包围所述源漏接触孔插塞54的部分侧壁为例。在其他实施例中，根据实际工艺需求，所述栅极接触孔插塞和源漏接触孔插塞还可以为其他形状。
所述刻蚀停止层62材料的介电常数通常大于介质层61材料的介电常数，通过所述第二平坦化处理，从而去除所述介质层61顶部的刻蚀停止层62，有利于减小所述刻蚀停止层62对互连结构之间寄生电容的影响。
本实施例中，进行所述第二平坦化处理的步骤中，还对所述源漏接触孔插塞54进行了平坦化处理。
具体地，采用化学机械研磨工艺进行第二平坦化处理，有利于提高源漏接触孔插塞54、栅极接触孔插塞66以及介质层61顶面的平坦度和高度一致性。
本实施例中，以去除所述介质层61顶部的刻蚀停止层62为例。在其他实施例中，由于所述刻蚀停止层的材料为介电材料，根据实际工艺需求，也可以不进行第二平坦化处理，从而省去去除介质层顶部的刻蚀停止层的步骤；相应地，在第一平坦化处理后，剩余所述导电材料层用于作为所述栅极接触孔插塞。
相应的，本发明还提供一种半导体结构。参考图13，示出了本发明半导体结构一实施例的结构示意图。
所述半导体结构包括：基底50；栅极结构51，位于所述基底50上；源漏掺杂层52，位于所述栅极结构51两侧的基底50内；介质层61，位于所述栅极结构51露出的基底50上，所述介质层61覆盖所述栅极结构51顶部；源漏接触孔插塞54，位于所述源漏掺杂层52顶部的所述介质层61内，所述源漏接触孔插塞54和所述源漏掺杂层52电连接，且所述源漏接触孔插塞54顶部高于所述介质层61顶部；刻蚀停止层62，至少位于所述介质层61所露出的源漏接触孔插塞54的侧壁上；栅极接触孔200，位于相邻所述源漏接触孔插塞54侧壁上的刻蚀停止层62之间的介质层61内，所述栅极接触孔200露出所述栅极结构51顶部。
所述栅极接触孔200用于为栅极接触孔插塞的形成提供空间位置。
形成所述栅极接触孔200制程通常包括刻蚀所述栅极结构51顶部的介质层61的步骤，所述刻蚀停止层62能够定义该刻蚀工艺的侧向刻蚀停止位置，即使栅极接触孔刻蚀工艺出现对准偏差时，也难以对源漏接触孔插塞54造成损耗，从而降低了形成栅极接触孔的难度，相应地，后续在所述栅极接触孔200内形成栅极接触孔插塞后，所述刻蚀停止层62能够定义源漏接触孔插塞54和栅极接触孔插塞之间的间距、以及实现两者之间的隔离，从而防止栅极接触孔插塞与源漏接触孔插塞54发生短接的问题，同时使栅极接触孔200能够形成于相邻源漏接触孔插塞54之间，即后续栅极接触孔插塞能够形成于有源区的栅极结构51上方，从而增大了形成有源栅极接触孔插塞的工艺窗口。
其中，侧向刻蚀停止位置指的是：形成所述栅极接触孔200的刻蚀步骤中，沿平行于所述基底50表面方向的刻蚀停止位置。
本实施例中，半导体结构为鳍式场效应晶体管。因此，基底包括衬底501以及凸出于衬底501的鳍部502。在其他实施例中，当半导体结构为平面型场效应晶体管时，基底相应仅包括衬底。
本实施例中，衬底501为硅衬底。在其他实施例中，衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料，衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。衬底的材料可以是适宜于工艺需要或易于集成的材料。
本实施例中，鳍部502与衬底501的材料相同，鳍部502的材料为硅。在其他实施例中，鳍部的材料还可以是锗、锗化硅、碳化硅、砷化镓或镓化铟等适宜于形成鳍部的半导体材料。
半导体结构还包括：隔离层55，位于鳍部502露出的衬底501上，隔离层55覆盖鳍部502的部分侧壁。隔离层55用于对相邻器件之间起到隔离作用。
本实施例中，所述隔离层55的材料为氧化硅。在其他实施例中，所述隔离层的材料还可以是氮化硅或氮氧化硅等其他绝缘材料。
本实施例中，所述栅极结构51为金属栅结构，所述栅极结构51包括高k栅介质层(图未示)以及位于所述高k栅介质层上的栅电极层(图未示)。
本实施例中，所述高k栅介质层的材料为高k介质材料。具体地，所述高k栅介质层的材料为HfO2。在其他实施例中，所述高k栅介质层的材料还可以选自ZrO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO或Al2O3等。
所述栅电极层的材料为Al、Cu、Ag、Au、Pt、Ni、Ti或W。本实施例中，所述栅电极层的材料为W。
所述半导体结构还包括：侧墙56，位于栅极结构51的侧壁上。侧墙56用于定义源漏掺杂层52的形成区域，侧墙56还用于保护栅极结构51的侧壁。所述侧墙56的材料可以为氧化硅、氮化硅、氮氧化硅、碳化硅、碳氮氧化硅、碳氧化硅、氮化硼和碳氮化硼中的一种或多种，侧墙56可以为单层结构或叠层结构。本实施例中，侧墙56为叠层结构。具体地，侧墙56为ONO结构。
本实施例中，所述源漏掺杂层52位于所述栅极结构51两侧的鳍部502内。
当半导体结构为NMOS晶体管时，源漏掺杂层52包括掺杂有N型离子的应力层，应力层的材料为Si或SiC，应力层为NMOS晶体管的沟道区提供拉应力作用，从而有利于提高NMOS晶体管的载流子迁移率，其中，N型离子为P离子、As离子或Sb离子。当半导体结构为PMOS晶体管时，源漏掺杂层52包括掺杂有P型离子的应力层，应力层的材料为Si或SiGe，应力层为PMOS晶体管的沟道区提供压应力作用，从而有利于提高PMOS晶体管的载流子迁移率，其中，P型离子为B离子、Ga离子或In离子。
本实施例中，相邻的栅极结构51共用一个源漏掺杂层52。
本实施例中，沿所述鳍部502的延伸方向上，位于所述鳍部502边缘的栅极结构51用于作为伪栅。相应地，所述伪栅顶部未形成栅极接触孔。
本实施例中，所述半导体结构还包括：接触孔刻蚀阻挡层59，覆盖所述栅极结构51侧壁、以及所述栅极结构51和源漏接触孔插塞54所露出的基底50。
所述接触孔刻蚀阻挡层59用于在形成源漏接触孔插塞54的刻蚀工艺中，定义源漏接触孔刻蚀工艺的纵向刻蚀停止位置，减小源漏掺杂层52在该刻蚀工艺中受损的概率。本实施例中，所述接触孔刻蚀阻挡层59的材料为氮化硅。
本实施例中，所述半导体结构还包括：底部介质层57，覆盖所述栅极结构51的部分侧壁。具体地，所述底部介质层57露出所述源漏掺杂层52顶部。
所述底部介质层57用于实现相邻器件之间的隔离。为此，所述底部介质层57的材料为介电材料，例如氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅和碳氮氧化硅中的一种或多种。本实施例中，底部介质层57的材料为氧化硅。
本实施例中，所述半导体结构还包括：顶部介质层60，覆盖所述底部介质层57且露出所述栅极结构51的顶部。所述顶部介质层60与所述底部介质层57构成层间介质层，从而实现相邻器件之间的隔离。
为此，所述顶部介质层60的材料为介电材料，例如氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅和碳氮氧化硅中的一种或多种。本实施例中所述顶部介质层60与底部介质层57的材料相同，所述顶部介质层60的材料为氧化硅。
介质层61用于实现源漏接触孔插塞54和栅极接触孔插塞之间的电隔离，介质层61还用于为形成源漏接触孔插塞54和栅极接触孔200提供工艺平台。
为此，所述介质层61的材料也为介电材料。本实施例中，为提高工艺兼容性，所述介质层61与顶部介质层60的材料相同，其材料为氧化硅。
所述介质层61顶部至源漏接触孔插塞54顶部的距离不宜过小，也不宜过大。如果所述距离过小，则介质层61露出的源漏接触孔插塞54的高度过小，位于介质层61露出的源漏接触孔插塞54侧壁上的刻蚀停止层62的高度相应过小，所述刻蚀停止层62难以起到定义栅极接触孔刻蚀工艺的横向停止位置的作用；如果所述距离过大，则介质层61的厚度相应过小，后续在栅极接触孔200内形成栅极接触孔插塞后，栅极接触孔插塞的高度也过小。为此，本实施例中，所述介质层61顶部至源漏接触孔插塞54顶部的距离为50埃米至300埃米。
所述源漏接触孔插塞54用于实现所述源漏掺杂层52与其他互连结构或外部电路的电连接。
本实施例中，所述源漏接触孔插塞54的材料为铜，有利于改善后段RC的信号延迟，提高芯片的处理速度，同时还有利于降低源漏接触孔插塞54的电阻，相应降低了功耗。在其他实施例中，所述接触孔插塞的材料还可以为钨或钴。
本实施例中，所述半导体结构还包括：自对准停止层58，位于所述底部介质层57露出的栅极结构51侧壁上。
形成所述源漏接触孔插塞54的源漏接触孔刻蚀工艺中，相邻栅极结构51侧壁上的自对准停止层58用于定义沿垂直于栅极结构51侧壁方向上的刻蚀停止位置，从而实现源漏接触孔刻蚀工艺的自对准，进而能够形成所述源漏接触孔插塞54。相应地，所述源漏接触孔插塞54为自对准接触孔插塞(SAC)。
自对准停止层58的材料可以为氮化硅、氧化铝、氮化铝或NDC。所述层间介质层和初始介质层53中的任一种材料与所述材料均具有较大的刻蚀选择比，从而能够保证所述自对准停止层58能够起到相应的工艺效果。本实施例中，自对准停止层58的材料为氮化硅。氮化硅材料为半导体工艺中常用的材料，有利于提高工艺兼容性。
在其他实施例中，所述自对准停止层还可以位于栅极结构顶部。相应地，所述自对准停止层和侧墙可以实现源漏接触孔刻蚀工艺的自对准。
所述刻蚀停止层62用于定义形成栅极接触孔200的刻蚀工艺中，沿垂直于所述栅极结构51侧壁方向上的刻蚀停止位置。
为保证刻蚀停止层62能够起到定义栅极接触孔刻蚀工艺的横向停止位置的作用，刻蚀停止层62的材料为与介质层61材料具有较大刻蚀选择性的材料。
所述刻蚀停止层62的材料可以为氮化硅或碳化硅。所述介质层61与所述材料的刻蚀选择比较大，有利于保证所述刻蚀停止层62用于定义侧向刻蚀停止位置的作用。本实施例中，所述刻蚀停止层62的材料为氮化硅。氮化硅材料为半导体工艺中常用的材料，工艺兼容性高。
在其他实施例中，当所述半导体结构包括位于栅极结构顶部的自对准停止层时，相应地，形成栅极接触孔的步骤中，刻蚀所述栅极结构顶部的介质层后，还包括：刻蚀所述栅极结构顶部的自对准停止层。在该实施例中，为保证所述刻蚀停止层用于定义栅极接触孔刻蚀工艺的横向停止位置的作用，所述刻蚀停止层的材料还需要满足：刻蚀所述自对准停止层的步骤中，所述自对准停止层的材料与所述刻蚀停止层材料的刻蚀选择比大于或等于5：1。
本实施例中，所述刻蚀停止层62保形覆盖介质层61所露出的源漏接触孔插塞54的顶部和侧壁、以及介质层61的顶部。
其中，位于所述源漏接触孔插塞54顶部的刻蚀停止层62能够在工艺制程中保护源漏接触孔插塞54的顶部；位于所述介质层61顶部的刻蚀停止层62能够在后续形成栅极接触孔插塞的平坦化工艺中，定义平坦化工艺的停止位置。
刻蚀停止层62不宜过薄，也不宜过厚。如果所述刻蚀停止层62过薄，不仅容易导致刻蚀停止层62的厚度小于形成栅极接触孔200刻蚀工艺的对准偏差，而且容易导致刻蚀停止层62在该刻蚀工艺中被过早的去除，上述两种情况均会降低刻蚀停止层62用于定义栅极接触孔刻蚀工艺的侧向刻蚀停止位置的效果；如果所述刻蚀停止层62过厚，不仅容易造成工艺时间和材料的浪费，还容易导致相邻源漏接触孔插塞54侧壁上的刻蚀停止层62之间的剩余空间过小，或者，容易导致相邻源漏接触孔插塞54侧壁上的刻蚀停止层62相接触，从而增加形成栅极接触孔200的工艺难度。为此，本实施例中，刻蚀停止层62的厚度为50埃米至300埃米。
所述半导体结构可以采用前述实施例所述的形成方法所形成，也可以采用其他形成方法所形成。对本实施例所述半导体结构的具体描述，可参考前述实施例中的相应描述，本实施例在此不再赘述。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (18)

1.一种半导体结构的形成方法，其特征在于，包括：
提供基底，所述基底上形成有栅极结构，所述栅极结构两侧的基底内形成有源漏掺杂层，所述栅极结构露出的基底上形成有初始介质层，所述初始介质层覆盖所述栅极结构顶部，所述源漏掺杂层顶部的初始介质层内形成有源漏接触孔插塞，所述源漏接触孔插塞与所述源漏掺杂层电连接；
去除部分厚度的所述初始介质层，形成介质层，露出所述源漏接触孔插塞的部分侧壁；
至少在所述介质层所露出的源漏接触孔插塞的侧壁上形成刻蚀停止层；
以相邻所述源漏接触孔插塞侧壁上的刻蚀停止层为侧向刻蚀停止位置，刻蚀所述栅极结构顶部的介质层，形成露出所述栅极结构顶部的栅极接触孔；
在所述栅极接触孔内形成栅极接触孔插塞，所述栅极接触孔插塞与所述栅极结构电连接。
2.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述刻蚀停止层的步骤中，所述刻蚀停止层保形覆盖所述介质层所露出的源漏接触孔插塞的顶部和侧壁、以及所述介质层的顶部。
3.如权利要求2所述的半导体结构的形成方法，其特征在于，形成所述栅极接触孔插塞的步骤包括：形成填充所述栅极接触孔的导电材料层，所述导电材料层还覆盖所述源漏接触孔插塞和介质层顶部的刻蚀停止层；以所述介质层顶部的刻蚀停止层顶面为停止位置，对所述导电材料层进行第一平坦化处理。
4.如权利要求3所述的半导体结构的形成方法，其特征在于，形成所述栅极接触孔插塞的步骤还包括：进行所述第一平坦化处理后，以所述介质层顶面为停止位置，对所述导电材料层和刻蚀停止层进行第二平坦化处理。
5.如权利要求3所述的半导体结构的形成方法，其特征在于，采用化学机械研磨工艺进行所述第一平坦化处理。
6.如权利要求4所述的半导体结构的形成方法，其特征在于，采用化学机械研磨工艺进行所述第二平坦化处理。
7.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述介质层的步骤中，所述介质层顶部至所述源漏接触孔插塞顶部的距离为50埃米至300埃米。
8.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述刻蚀停止层的步骤中，所述刻蚀停止层的厚度为50埃米至300埃米。
9.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述栅极接触孔的步骤包括：形成覆盖所述刻蚀停止层的掩膜层；图形化所述掩膜层，在所述掩膜层中形成掩膜开口；以所述掩膜层为掩膜，以相邻所述源漏接触孔插塞侧壁上的刻蚀停止层为侧向刻蚀停止位置，刻蚀所述掩膜开口露出的所述介质层，形成所述栅极接触孔；
形成所述栅极接触孔后，还包括：去除所述掩膜层。
10.如权利要求1所述的半导体结构的形成方法，其特征在于，所述栅极结构顶部还形成有自对准停止层；
形成所述栅极接触孔的步骤还包括：刻蚀所述栅极结构顶部的介质层后，刻蚀所述自对准停止层；
刻蚀所述自对准停止层的步骤中，所述自对准停止层的材料与所述刻蚀停止层材料的刻蚀选择比大于或等于5：1。
11.如权利要求1所述的半导体结构的形成方法，其特征在于，所述刻蚀停止层的材料为氮化硅或碳化硅。
12.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述刻蚀停止层的工艺包括原子层沉积工艺。
13.如权利要求1所述的半导体结构的形成方法，其特征在于，采用干法刻蚀工艺去除部分厚度的所述初始介质层。
14.一种半导体结构，其特征在于，包括：
基底；
栅极结构，位于所述基底上；
源漏掺杂层，位于所述栅极结构两侧的基底内；
介质层，位于所述栅极结构露出的基底上，所述介质层覆盖所述栅极结构顶部；
源漏接触孔插塞，位于所述源漏掺杂层顶部的所述介质层内，所述源漏接触孔插塞和所述源漏掺杂层电连接，且所述源漏接触孔插塞顶部高于所述介质层顶部；
刻蚀停止层，至少位于所述介质层所露出的源漏接触孔插塞的侧壁上；
栅极接触孔，位于相邻所述源漏接触孔插塞侧壁上的刻蚀停止层之间的介质层内，所述栅极接触孔露出所述栅极结构顶部。
15.如权利要求14所述的半导体结构，其特征在于，所述刻蚀停止层保形覆盖所述介质层所露出的源漏接触孔插塞的顶部和侧壁、以及所述介质层的顶部。
16.如权利要求14所述的半导体结构，其特征在于，所述介质层顶部至所述源漏接触孔插塞顶部的距离为50埃米至300埃米。
17.如权利要求14所述的半导体结构，其特征在于，所述源漏接触孔插塞侧壁上的所述刻蚀停止层的厚度为50埃米至300埃米。
18.如权利要求14所述的半导体结构，其特征在于，所述刻蚀停止层的材料为氮化硅或碳化硅。
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