CN111681959A - 用于制作半导体器件的方法 - Google Patents

用于制作半导体器件的方法 Download PDF

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Publication number
CN111681959A
CN111681959A CN201910688687.5A CN201910688687A CN111681959A CN 111681959 A CN111681959 A CN 111681959A CN 201910688687 A CN201910688687 A CN 201910688687A CN 111681959 A CN111681959 A CN 111681959A
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Prior art keywords
dielectric layer
layer
forming
nitrogen
plasma
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CN111681959B (zh
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吴少均
潘昇良
林焕哲
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开涉及用于制作半导体器件的方法。一种方法包括：在第一半导体区域之上形成第一高k电介质层；在第二半导体区域之上形成第二高k电介质层；形成第一金属层，所述第一金属层包括位于所述第一高k电介质层之上的第一部分和位于所述第二高k电介质层之上的第二部分；在所述第一金属层的所述第二部分之上形成蚀刻掩模；以及蚀刻所述第一金属层的所述第一部分。所述蚀刻掩模保护所述第一金属层的所述第二部分。使用亚稳态等离子体来灰化所述蚀刻掩模。然后在所述第一高k电介质层之上形成第二金属层。

Description

用于制作半导体器件的方法
技术领域
本公开涉及用于制作半导体器件的方法。
背景技术
金属氧化物半导体(MOS)器件是集成电路中的基本构建元件。MOS器件的最新发展包括形成替换栅极，替换栅极包括高k栅极电介质和位于高k栅极电介质之上的金属栅极电极。替换栅极的形成通常涉及在高k栅极电介质层之上沉积高k栅极电介质层和金属层，并且然后执行化学机械抛光(CMP)以去除高k栅极电介质层和金属层的多余部分。金属层的剩余部分形成金属栅极。
在MOS器件的常规形成方法中，当对高k电介质层进行氨处理时，可以通过执行热退火工艺来改变MOS器件的阈值电压。尽管可以改变阈值电压，但无法将阈值电压调整到预期值，必须通过采用不同的功函数金属和调整功函数金属的厚度来实现进一步的调整。
发明内容
根据本公开的一个实施例，提供了一种用于制作半导体器件的方法，包括：在第一半导体区域之上形成第一高k电介质层；在第二半导体区域之上形成第二高k电介质层；形成第一金属层，所述第一金属层包括位于所述第一高k电介质层之上的第一部分和位于所述第二高k电介质层之上的第二部分；在所述第一金属层的所述第二部分之上形成蚀刻掩模；蚀刻所述第一金属层的所述第一部分，其中，所述蚀刻掩模保护所述第一金属层的所述第二部分；使用亚稳态等离子体来灰化所述蚀刻掩模；以及在所述第一高k电介质层之上形成第二金属层。
根据本公开的另一实施例，提供了一种用于制作半导体器件的方法，包括：在高k电介质层之上形成金属层；在所述金属层之上形成底部抗反射涂层BARC；在所述BARC之上形成光致抗蚀剂；图案化所述光致抗蚀剂；使用经图案化的光致抗蚀剂作为蚀刻掩模来蚀刻所述BARC；以及使用亚稳态等离子体去除所述BARC，其中，所述亚稳态等离子体是由以下工艺生成的，所述工艺包括：将氮和氦导入喷头的第一输入端以生成等离子体；过滤以从所述等离子体中去除离子，其中氮自由基和氦自由基留在所述等离子体中；以及将氢导入所述喷头的第二输入端，其中氢与所述氮自由基和所述氦自由基混合。
根据本公开的又一实施例，提供了一种用于制作半导体器件的方法，包括：在衬底上形成第一高k电介质层和第二高k电介质层，其中，所述第一高k电介质层和所述第二高k电介质层由相同的高k电介质材料形成；使用第一亚稳态等离子体工艺在所述第一高k电介质层上执行第一处理工艺，其中氮、氢和氦用作工艺气体，并且所述氮具有第一流速；使用第二亚稳态等离子体工艺在所述第二高k电介质层上执行第二处理工艺，其中氮、氢和氦用作工艺气体，并且所述氮具有第二流速；以及分别在所述第一高k电介质层和所述第二高k电介质层之上形成第一金属层和第二金属层。
附图说明
当结合附图阅读时，从以下具体实施方式中可以最好地理解本公开的各方面。应注意，根据工业中的标准实践，各种特征未按比例绘制。实际上，为了清楚讨论，可以任意增大或减小各种特征的尺寸。
图1-6、7A、7B和8-16图示了根据一些实施例的形成鳍式场效应晶体管(FinFET)的中间阶段的透视图和截面视图。
图17图示了根据一些实施例的用于灰化和同时调整FinFET的阈值电压的生产工具和处理工艺。
图18图示了根据一些实施例的作为氮流速的函数的平带电压。
图19和20比较了根据一些实施例的在分别使用常规电感耦合等离子体(ICP)处理和亚稳态等离子体处理时对FinFET的平带电压的影响。
图21图示了根据一些实施例的通过具有不同氮流速的亚稳态等离子体处理的高k电介质层中的氢浓度。
图22图示了根据一些实施例的用于形成FinFET的工艺流程。
具体实施方式
以下公开提供了用于实施本发明的不同特征的许多不同实施例或示例。为简化本公开，以下描述了组件和布置的具体示例。当然，这些只是示例，并非是要进行限制。例如，在以下描述中的在第二特征上或之上形成第一特征可以包括第一特征和第二特征直接接触形成的实施例，并且还可以包括可以在第一特征和第二特征之间形成附加特征的实施例，使得第一特征和第二特征可以不直接接触。此外，在各种示例中，本公开可以重复参考数字和/或字母。这种重复的目的是为了简单和清晰，并且本身并不指示所讨论的各种实施例和/或配置之间的关系。
此外，为了便于描述，可以在本文中使用空间相关术语，例如“下层”、“下方”、“下”、“上层”、“上”等，以描述一个元素或特征与另一个(多个)元素或特征的关系，如图中所示。除了图中所描绘的定向外，空间相关术语旨在涵盖使用或操作中的器件的不同定向。装置可以以其他方式定向(旋转90度或以其他定向)，并且本文所使用的空间相对描述符也可以相应地解释。
根据各种实施例提供了具有替换栅极的晶体管以及调整晶体管的阈值电压的方法。根据一些实施例图示了形成晶体管的中间阶段。讨论了一些实施例的一些变型。在整个各种视图和说明性实施例中，使用相同的参考数字来指定相同的元素。根据一些实施例，鳍式场效应晶体管(FinFET)的形成被用作解释本公开的构思的示例。其他类型的晶体管(例如平面晶体管和栅极环绕式(GAA)晶体管也可以采用本发明的构思。
根据本公开的一些实施例，利用用于去除底部抗反射涂层(BARC)(BARC用于图案化栅极电介质层顶部上的层(其可以是金属层，例如功函数金属))的灰化工艺来调整FinFET的阈值电压。调整用于去除BARC的氮流速，以将对应的FinFET的阈值调整为期望值。
图1-6、7A、7B和8-16图示了根据本公开的一些实施例的形成鳍式场效应晶体管(FinFET)的中间阶段的截面视图和透视图。这些图中所示的工艺也在图22所示的工艺流程400中得到了示意性的反映。
在图1中，提供了衬底20。衬底20可以是半导体衬底，例如体半导体衬底、绝缘体上的半导体(SOI)衬底等，其可以是掺杂的(例如，用p型或n型掺杂剂)或未掺杂的。半导体衬底20可以是晶圆10的一部分，例如硅晶圆。通常，SOI衬底是形成在绝缘体层上的半导体材料的层。例如，绝缘体层可以是埋置氧化物(BOX)层、氧化硅层等。绝缘体层被提供在衬底上，通常是硅或玻璃衬底。还可以使用诸如多层或梯度衬底之类的其他衬底。在一些实施例中，半导体衬底20的半导体材料可以包括硅；锗；包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体；或其组合。
进一步参考图1，在衬底20中形成阱区域22。在图22所示的工艺流程400中，相应的工艺如工艺402所示。根据本公开的一些实施例，阱区域22是通过将n型杂质(其可以是磷、砷、锑等)植入衬底20而形成的n型阱区域。根据本公开的其他实施例，阱区域22是通过将p型杂质(其可以是硼、铟等)植入衬底20而形成的p型阱区域。所产生的阱区域22可以延伸至衬底20的顶表面。n型或p型杂质浓度可以等于或小于1018cm-3，例如在约1017cm-3到约1018cm-3之间。
参考图2，形成隔离区域24以从衬底20的顶表面延伸到衬底20中。隔离区域24在下文中也被替代地称为浅沟槽隔离(STI)区域。在图22所示的工艺流程400中，相应的工艺如工艺404所示。衬底20的在相邻的STI区域24之间的部分被称为半导体条带26。为了形成STI区域24，在半导体衬底20上形成衬垫氧化物层28和硬掩模层30，并且然后将其图案化。衬垫氧化物层28可以是由氧化硅形成的薄膜。根据本公开的一些实施例，在热氧化工艺中形成衬垫氧化物层28，其中半导体衬底20的顶表面层被氧化。衬垫氧化物层28起半导体衬底20和硬掩模层30之间的粘合层的作用。衬垫氧化物层28还可以起用于蚀刻硬掩模层30的蚀刻停止层的作用。根据本公开的一些实施例，硬掩模层30由氮化硅形成，例如，使用低压化学气相沉积(LPCVD)。根据本公开的其他实施例，硬掩模层30是通过硅的热氮化或等离子体增强化学气相沉积(PECVD)形成的。在硬掩模层30上形成光致抗蚀剂(未显示)，并且然后将其图案化。然后使用图案化光致抗蚀剂作为蚀刻掩模对硬掩模层30进行图案化，以形成如图2所示的硬掩模30。
接下来，将图案化硬掩模层30用作蚀刻掩模来蚀刻衬垫氧化物层28和衬底20，然后用(多种)电介质材料填充衬底20中所产生的沟槽。执行平坦化工艺(例如化学机械抛光(CMP)工艺或机械研磨工艺)以去除电介质材料的多余部分，并且(多种)电介质材料的剩余部分是STI区域24。STI区域24可以包括内衬电介质(未显示)，其可以为通过衬底20的表面层的热氧化而形成的热氧化物。该内衬电介质还可以是使用例如原子层沉积(ALD)、高密度等离子体化学气相沉积(HDPCVD)或化学气相沉积(CVD)形成的沉积的氧化硅层、氮化硅层等。STI区域24还可以包括内衬氧化物之上的电介质材料，其中电介质材料可以使用可流动化学气相沉积(FCVD)、旋涂等形成。根据一些实施例，内衬电介质之上的电介质材料可以包括氧化硅。
硬掩模30的顶表面和STI区域24的顶表面可以大体上相互齐平。半导体条带26位于相邻的STI区域24之间。根据本公开的一些实施例，半导体条带26是原始衬底20的部分，并且因此半导体条带26的材料与衬底20的材料相同。根据本公开的替代实施例，半导体条带26是通过蚀刻衬底20在STI区域24之间的部分以形成凹槽，并执行外延以在凹槽中再生长另一种半导体材料而形成的替换条带。因此，半导体条带26带由不同于衬底20的半导体材料形成。根据一些实施例，半导体条带26带由硅锗、硅碳或III-V化合物半导体材料形成。
参考图3，STI区域24是凹陷的，使得半导体条带26的顶部部分突出高于STI区域24的剩余部分的顶表面24A，以形成突出鳍部36。在如图22所示的工艺流程400中，相应的工艺如工艺406所示。可以使用干法蚀刻工艺来执行蚀刻，其中例如HF3和NH3用作蚀刻气体。在蚀刻工艺期间，可以生成等离子体。还可以包括氩。根据本公开的替代实施例，使用湿法蚀刻工艺执行STI区域24的凹陷。例如，蚀刻化学品可以包括HF。
在以上所示的实施例中，可以通过任何适合的方法对鳍部进行图案化。例如，可以使用一种或多种光刻工艺(包括双图案化或多图案化工艺)对鳍部进行图案化。通常，双图案化或多图案化工艺结合了光刻和自对准工艺，允许图案被创建有例如比使用单直接光刻工艺所能获得的节距更小的节距。例如，在一个实施例中，在衬底之上形成牺牲层并使用光刻工艺来图案化。使用自对准工艺沿着图案化牺牲层形成间隔体。然后去除牺牲层，并且剩余的间隔体或芯轴(mandrel)可以用于图案化鳍部。
参考图4，虚设栅极堆叠38被形成为在(突出)鳍部36的顶表面和侧壁上延伸。在图22所示的工艺流程400中，相应的工艺如工艺408所示。虚设栅极堆叠38可以包括虚设栅极电介质40和位于虚设栅极电介质40之上的虚设栅极电极42。例如，可以使用多晶硅形成虚设栅极电极42，并且还可以使用其他材料。虚设栅极堆叠38中的每个还可以包括位于虚设栅极电极42之上的一个(或多个)硬掩模层44。硬掩模层44可以由氮化硅、氧化硅、氮碳化硅或其多层形成。虚设栅极堆叠38可以跨过单一或多个突出的鳍部36和STI区域24。虚设栅极堆叠38的纵向方向还与突出鳍部36的纵向方向垂直。
接下来，在虚设栅极堆叠38的侧壁上形成栅极间隔体46。在图22所示的工艺流程400中，相应的工艺还如工艺408所示。根据本公开的一些实施例，栅极间隔体46由(一个或多个)电介质材料(例如氮化硅、碳氮化硅等)形成，并且可以具有单层结构或包括多个电介质层的多层结构。
然后执行蚀刻工艺，以蚀刻突出鳍部36的未被虚设栅极堆叠38和栅极间隔体46覆盖的部分，从而产生图5所示的结构。在图22所示的工艺流程400中，相应的工艺如工艺410所示。凹槽可以是各向异性的，并且因此鳍部36的直接位于虚设栅极堆叠38和栅极间隔体46下面的部分受到保护，并且没有被蚀刻。根据一些实施例，凹陷的半导体条带26的顶表面可以低于STI区域24的顶表面24A。相应地形成凹槽50。凹槽50包括位于虚设栅极堆叠38的相对侧上的部分以及位于突出鳍部36的剩余部分之间的部分。
接下来，外延区域(源极/漏极区域)52是通过选择性地(通过外延)在凹槽50中生长半导体材料而形成的，从而产生图6中的结构。在图22所示的工艺流程400中，相应的工艺如工艺412所示。根据所产生的FinFET是p型FinFET还是n型FinFET，p型或n型杂质可以用外延过程进行原位掺杂。例如，当所产生的FinFET是p型FinFET时，可以生长硅锗硼(SiGeB)、硅硼(SiB)等。相反地，当所产生的FinFET是n型FinFET时，可以生长硅磷(SiP)、硅碳磷(SiCP)等。根据本公开的替代实施例，外延区域52包含III-V化合物半导体，例如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、其组合或其多层。在用外延区域52填充凹槽50之后，外延区域52的进一步外延生长导致外延区域52水平扩展，并形成刻面。外延区域52的进一步生长也可以使得相邻的外延区域52彼此合并。可以生成空隙(气隙)53。根据本公开的一些实施例，外延区域52的形成可以在外延区域52的顶表面仍然呈波浪形时完成，或者当合并的外延区域52的顶表面已成为平面时完成，这是通过在外延区域52上进行进一步生长来实现的，如图6所示。
在外延步骤之后，外延区域52可以进一步植入p型或n型杂质以形成源极和漏极区域，该源极和漏极区域也使用参考数字52表示。根据本公开的替代实施例，当外延区域52分别在外延期间原位掺杂n型和p型杂质时，跳过植入工艺。
图7A图示了在形成接触蚀刻停止层(CESL)58和层间电介质(ILD)60之后的结构的透视图。在图22所示的工艺流程400中，相应的工艺如工艺414所示。CESL 58可以由氧化硅、氮化硅、碳氮化硅等形成，并且可以使用CVD、ALD等形成。ILD 60可以包括使用例如FCVD、旋涂、CVD或另一种沉积方法形成的电介质材料。ILD 60可以由含氧电介质材料形成，该含氧电介质材料可以为基于氧化硅的材料，该基于氧化硅的材料是使用正硅酸四乙酯(TEOS)氧化物(作为前体)、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂磷硅酸盐玻璃(BPSG)等形成的。可以执行平坦化工艺，例如CMP工艺或机械研磨工艺，以使ILD 60的顶表面、虚设栅极堆叠38和栅极间隔体46彼此齐平。
图7B图示了在同一衬底20上并且在同一管芯和同一晶片中形成第一FinFET和第二FinFET的中间结构的截面视图。第一FinFET和第二FinFET中的任一个可以对应于从包含图7A中的线7B-7B的竖直平面获得的截面视图。第一FinFET形成在器件区域100中，并且第二FinFET形成在器件区域200中。第一FinFET和第二FinFET的阈值电压可以彼此不同。根据本公开的一些实施例，第一FinFET和第二FinFET两者都是n型FinFET或p型FinFET。根据本公开的替代实施例，第一FinFET是n型FinFET，并且第二FinFET是p型FinFET。替代地，第一FinFET是p型FinFET，并且第二FinFET是n型FinFET。在所讨论的示例中，图示了n型场效应晶体管和p型场效应晶体管的形成，同时还考虑了FinFET的其他组合。
为了将第一FinFET中的特征与第二FinFET中的特征区分开，可以使用图7A中的对应特征的参考数字加上数字100来表示第一FinFET中的特征，并且可以使用图7A中的对应特征的参考数字加上数字200来表示第二FinFET中的特征。例如，图7B中的源极/漏极区域152和252对应于图7A中的源极/漏极区域52，并且图7B中的栅极间隔体146和246对应于图7A中的栅极间隔体46。第一FinFET和第二FinFET中的对应特征可以在普通工艺中形成。
在形成图7A和7B所示的结构后，用金属栅极和替换栅极电介质来替换包括硬掩模层44、虚设栅极电极42和虚设栅极电介质40的虚设栅极堆叠，如图8至16所示的工艺所示。在图8至16中，图示了STI区域24的顶表面124A和224A，并且半导体鳍部136和236分别突出高于顶表面124A和224A。
为了形成替换栅极，去除图7A和7B中所示的硬掩模层44、虚设栅极电极42和虚设栅极电介质40，从而形成图8中所示的开口147和247。在图22所示的工艺流程400中，相应的工艺如工艺416所示。突出鳍部136和236的顶表面和侧壁分别暴露于开口147和247。
接下来，参考图9，形成了分别延伸到开口147和247中的栅极电介质154/156和254/256。在图22所示的工艺流程400中，相应的工艺如工艺418所示。根据本公开的一些实施例，栅极电介质包括界面层(IL)154和254，IL 154和254分别形成在突出鳍部136和236的暴露表面上。IL 154和254可以包括氧化物层，例如氧化硅层，所述氧化物层是通过突出鳍部136和236的热氧化、化学氧化工艺或沉积工艺形成的。栅极电介质还可以包括位于对应的IL 154和254之上的高k电介质层156和256。高k电介质层156和256可以由高k电介质材料形成，例如氧化铪、氧化镧、氧化铝、氧化锆等。高k电介质材料的介电常数(k值)高于3.9，并且可以高于约7.0，有时高达21.0或更高。高k电介质层156和256是上层的，并且可以接触相应的下层IL 154和254。高k电介质层156和256被形成为共形层，并且分别在突出鳍部136和236的侧壁以及栅极间隔体146和246的顶表面和侧壁上延伸。根据本公开的一些实施例，使用ALD或CVD形成高k电介质层156和256。
进一步参考图9，形成了金属层。在图22所示的工艺流程400中，相应的工艺如工艺420所示。金属层包括器件区域100中的部分162和器件区域200中的部分262，并且部分162和262被称为含金属层。通过沉积形成含金属层162和262。可以使用共形沉积方法(例如ALD或CVD)来执行沉积，使得含金属层262(及每一子层)的水平部分的水平厚度和竖直部分的竖直厚度大体上彼此相等。例如，水平厚度T1和竖直厚度T2的差值可以小于任一厚度T1和T2的约20％或10％。根据本公开的一些实施例，含金属层162和262延伸到开口147和247(图8)中，并且包括ILD 60之上的部分。
含金属层162和262可以包括p型功函数金属层，例如TiN层。根据本公开的一些实施例，含金属层162和262中的每个都是单层，例如TiN层。根据其他实施例，含金属层162和262中的每个都是复合层，包括由不同材料形成的多个层。例如，含金属层162和262中的每个可以分别包括TiN层、TaN层和另一TiN层。
底部抗反射涂层(BARC)66形成在含金属层162和262上。在图22所示的工艺流程400中，相应的工艺如工艺422所示。根据本公开的一些实施例，BARC 66由光致抗蚀剂形成，光致抗蚀剂被烘烤并因此交联。接下来，施加光致抗蚀剂68并将其图案化，使得光致抗蚀剂68在器件区域100中的部分被去除，并且光致抗蚀剂68在器件区域200中的部分保留。在图22所示的工艺流程400中，相应的工艺如工艺424所示。
图10图示了一种蚀刻工艺，其中光致抗蚀剂剂68用作蚀刻掩模。在蚀刻工艺中，去除BARC 66在器件区域100中的部分。在图22所示的工艺流程400中，相应的工艺如工艺426所示。在随后的工艺中，如图11所示，去除光致抗蚀剂68，并且显露底层BARC 66。
然后执行蚀刻工艺以蚀刻含金属层162。在图22所示的工艺流程400中，相应的工艺如工艺428所示。结果，显露出高k电介质层156。所产生的结构如图12所示。在蚀刻工艺期间，BARC 66用为蚀刻掩模来保护含金属层262。根据本公开的一些实施例，通过湿法蚀刻来执行蚀刻工艺。例如，当含金属层162由TiN形成时，蚀刻化学品可以包括化学溶液，包括氨(NH3)、过氧化氢(H2O2)和水。根据替代的实施例，可以使用干法蚀刻工艺。
图13图示了通过灰化工艺去除BARC 66，在灰化工艺中生成等离子体，如箭头67所表示的。在图22所示的工艺流程400中，相应的工艺如工艺430所示。用于灰化BARC 66的生产工具300如图17所示。生产工具300被配置为例如通过电感耦合等离子体(ICP)生成等离子体。此外，晶圆10置于晶圆保持器302之上，晶圆保持器302可以是电动卡盘(E-Chuck)。喷头304位于晶圆10之上，在晶圆10中等离子体由工艺气体生成。等离子体包括离子和自由基，离子和自由基通过喷头304过滤，使得自由基通过喷头304中的孔306A到达晶圆10，并且离子被阻挡且无法通过孔306A。
生产工具300被配置为生成亚稳态等离子体，亚稳态等离子体的寿命比典型的等离子体更长。亚稳态是原子或其它系统的激发态，其寿命比其它激发态更长。例如，处于亚稳态的原子和自由基可以以大约1秒的量级保持相当长时间的激发。然而，亚稳态的寿命比稳定基态的寿命更短。亚稳态是通过将氦(He)气体和N2气体导入喷头304生成的，并且等离子体是通过He生成的以生成He*自由基。
如图17所示，喷头304是双腔喷头，其包括两个输入端310A和310B。第一输入端310A可以位于喷头304的顶部处。根据一些实施例，混合气体N2和He通过输入端310A导入喷头304的内室，因此通过线圈308生成了离子N+和He+、电子e-和自由基N*和He*。内室连接到孔306A孔，孔306A被配置为捕获离子N+和He+，并允许自由基N*和He*通过。
第二输入端310B可以位于喷头304的侧面上，并且第二输入端310B不与内室连接。根据一些实施例，氢(H2)通过输入端310B导入喷头304。第二输入端310B连接到面向晶圆10的孔306B。因此，H2气体绕过线圈308，而不是由线圈308激发。因此，H2具有低能量。
进一步参考图17，当H2通过喷头304的侧壁内的隧道传导以从孔306B输出时，会激发满足He*和N*自由基的H2气体，因此产生H*自由基。由于H*从He*和N*自由基而不是直接从线圈308接收能量，因此H*的能量状态较低。所产生的H*的低能量状态使得可以调整高k电介质层156(图13)中所捕获的电荷的类型和量。捕获的电荷影响器件区域100中所产生的FinFET的平带电压(和阈值电压)。
由于高k电介质层156暴露于亚稳态等离子体，等离子体中所生成的离子和分子(例如N+和NH-)被捕获在高k电介质层156中，因此对应的电荷被捕获在高k电介质层156中。电荷的捕获导致器件区域100中FinFET阈值电压的变化和调整，如图18所显露的。
图18图示了实验结果，其中，平带电压被示为N2流速的函数。平带电压是从MOS电容器(MOSCAP)得到的，其栅极包括使用亚稳态等离子体处理的高k栅极电介质，如参考图17所讨论的。X轴代表N2流速，并且Y轴代表MOS电容器的平带电压。当H2的流速为4000sccm，并且He的流速为1000sccm时，得到图18中的结果。线320是当使用不同的N2流速进行如图13所示的灰化工艺时所得到的平带电压。线320显露了：不同的N2流速(在灰化BARC 66中)导致所产生的MOSCAP具有不同的平带电压，这与阈值电压密切关联。此外，较高的平带电压与较高的阈值电压相关联。因此，线320还显露了不同的N2流速(在灰化BARC 66中)导致所产生的FinFET具有不同的阈值电压。
如图18所示，当N2流速为一定值时，例如约2000sccm，对应的平带电压(因此为阈值电压)最低。当N2流速增大或减小时，平带电压增大。这可能是由于自由基H*、H*N*和NH*的量的变化引起的，如图18所示。根据本公开的一些实施例，亚稳态等离子体处理工艺使用小于约10,000sccm的氮流速。亚稳态源还可以由He、N2和/或O2作为侧注气体产生。
根据一些实施例，可以建立阈值电压和N2流速之间的关系。例如，可以制造具有如图14所示的结构的多个样品。每个样品使用一定的N2流速进行灰化工艺(去除BARC 66)，并且不同样品的N2流速彼此不同。测量/确定样品的阈值电压(和平带电压)，从而建立阈值电压与对应的N2流速之间的相关性。在FinFET的制造中，当一些FinFET旨在具有一定的阈值电压时，可以从相关性中找到对应的N2流速，并且在对应的灰化工艺中采用对应的N2流速以调整其阈值电压。
另外，在同一器件管芯中，如果同一管芯(同一晶圆)上的两个或更多个FinFET(可以是n型、p型，或者一些是n型一些是p型)旨在具有不同的阈值电压Vt，则阈值电压Vt的差异可以通过采用不同的N2流速来实现，而FinFET的其他结构和材料可以彼此相同。例如，两个FinFET可以具有相同厚度的相同功函数金属。此外，除了采用不同的N2流速外，两个或更多个FinFET可以共享相同的制造工艺。根据一些实施例，除器件区域100和200以外，还有器件区域100’和200’(示意性地如图13所示)。器件区域100’中的特征和形成工艺与器件区域100相同，并且器件区域200’中的特征和形成工艺与器件区域200相同。使用第一N2流速灰化器件区域200中的BARC 66，并且在灰化器件区域200中的BARC 66时，器件区域100中的高k电介质层156暴露于使用第一N2流速生成的等离子体。使用与第一N2流速不同的第二N2流速灰化器件区域200’中的BARC 66，并且器件区域10’中的高k电介质层156暴露于相应的等离子体。结果，器件区域100和100’中的FinFET具有不同的阈值电压，并且器件区域100和100’中的FinFET的其余结构相同。器件区域100和100’中的其余工艺(如图14-16所示)可能彼此相同，并且共享相同的工艺。器件区域200和200’中的其余工艺(如图14-16所示)可能彼此相同，并且共享相同的工艺。
图19和20图示了实验结果，其展示了在分别使用常规ICP和亚稳态等离子体对BARC 66进行灰化时器件区域200中器件的平带电压的差异。图19和20中的每一个都图示了平带电压和对应的灰化持续时间。图19是在使用常规ICP时得到的，其中，由图17中的输入端310a提供N2和H2(未使用He)，因此自由基具有高能量。输入端310B不提供气体。图19中的数据322、324和326分别是在对应的零秒(无灰化)、180秒和220秒灰化持续时间下得到的。数据表明，随着灰化时间的增加，平带电压增大，使得器件区域200(图13)的阈值电压增大。这是不期望的，因为在调整器件区域100中的器件的阈值电压时，器件区域200中的器件的阈值电压优选地不会改变。器件区域200中器件的阈值电压的非期望变化是由于自由基的高能量产生的，因此含金属层262和BARC 66(图13)无法掩盖自由基的影响。
图20是在使用根据本公开的实施例的亚稳态等离子体时得到的。数据328、330、332、334和336是在对应的灰化时间增加的情况下得到的。数据表明，随着灰化时间的增加，平带电压大体上保持稳定，因此器件区域200(图13)中器件的阈值电压不变。这允许器件区域100中的FinFET的阈值电压可以被独立调整，而不会影响器件区域200中FinFET的阈值电压。
图21图示了在使用不同灰化条件时高k电介质层156(图13)中的氢浓度。X轴代表进入相应样品的深度，并且Y轴代表浓度(原子/cm3)。线337、338和340分别代表在N2流速分别为3,000sccm、1,500sccm和0sccm(不执行灰化)时所得到的H-浓度。结果表明，线336的氢浓度高于线338和线340，这表明线336对应于高k电介质层156中捕获更多的H-。这也表明，3000sccm的N2流对应于更多的负电荷(H-)，因此，使用3000sccm N2灰化形成的对应晶体管比暴露于1500sccm N2灰化的晶体管具有更高的阈值电压。图21还展示了可以通过调整N2流速来调整晶体管的阈值电压。
亚稳态等离子体灰化还有助于减少TiN的氧化，这可以用于形成含金属层262。已经对TiN膜(其上形成有BARC)执行X射线光电子能谱(XPS)分析，并且使用亚稳态等离子体或常规ICP等离子体对BARC进行灰化。可以观察到，经历常规ICP等离子体灰化的样品，在灰化工艺之前的Ti2P强度值为20.0，在灰化工艺之后的Ti2P强度值为18.7。因此，ICP等离子体将Ti2P值降低1.3。作为比较，经历亚稳态等离子体灰化的样品，在灰化工艺之前的Ti2P强度值为19.6，在灰化工艺之后的Ti2P强度值为19.1。因此，亚稳态等离子体将Ti2P值降低0.5，小于1.3。这意味着，当TiN(层262)的上层BARC 66被灰化时，亚稳态等离子体还使得TiN的氧化减少。
由亚稳态等离子体生成的氢自由基用于灰化和去除BARC 66，如图13和14所示。图14图示了在BARC 66灰化之后的结构。此时，含金属层262为下层高k电介质层56提供保护，使其不接收诸如N+和NH-之类的电荷，并且防止调整所产生的FinFET的阈值。
由于采用N2作为工艺气体的亚稳态等离子体灰化工艺，氮在高k电介质层156中以例如N+和NH-的形式被捕获。因此，亚稳态等离子体工艺可以替换在高k电介质层上执行的使用氨作为工艺气体的常规热氮化工艺。因此，根据本公开的一些实施例，在整个FinFET形成中，不在高k电介质层上执行使用氨的热氮化工艺。
图15图示了FinFET的持续形成。根据本公开的一些实施例，沉积了n型功函数层，n型功函数层包括器件区域100中的部分164和器件区域200中的部分264。在图22所示的工艺流程400中，相应的工艺如工艺432所示。根据一些实施例，n型功函数层164和264包括单个层，例如TiAl层。根据其他实施例，n型功函数层164和264中的每一个包括复合层，该复合层包括TiN层、TaN层和基于Al的层(例如，由TiAlN、TiAlC、TaAlN或TaAlC形成)。然后沉积阻挡层和填充金属以形成金属区域168和268。在图22所示的工艺流程400中，相应的工艺如工艺434所示。然后执行诸如CMP工艺或机械研磨工艺之类的平坦化工艺，从而形成金属栅极170和270。还形成了包括对应的栅极170和270以及对应的栅极电介质154/156和254/256的替换栅极堆叠172和272。因此形成了FinFET 174和274。
参考图16，栅极电极170和270是凹陷的，并且填充有电介质材料(例如SiN)以形成硬掩模176和276。蚀刻停止层78形成在硬掩模176、276和ILD 60之上。蚀刻停止层78由电介质材料形成，电介质材料可以包括碳化硅、氮化硅、氮氧化硅等。ILD 80形成在蚀刻停止层78之上，并且栅极接触插塞182和282形成在ILD 80中。
本公开的实施例具有一些有利特征。通过使用亚稳态等离子体进行灰化去除了用于蚀刻形成在晶体管的高k电介质层上的金属层的蚀刻掩模。亚稳态等离子体的能量低。因此，与常规的ICP等离子体灰化(其中，调整阈值的效果是饱和的)不同，可以通过调整氮流速来调整晶体管的阈值电压。另外，金属层直接位于灰化掩模下的晶体管受金属层保护，不受亚稳态等离子体的影响，因此，相应晶体管的阈值电压不受灰化工艺的影响。
根据本公开的一些实施例，一种方法包括：在第一半导体区域之上形成第一高k电介质层；在第二半导体区域之上形成第二高k电介质层；形成第一金属层，所述第一金属层包括位于所述第一高k电介质层之上的第一部分和位于所述第二高k电介质层之上的第二部分；在所述第一金属层的所述第二部分之上形成蚀刻掩模；蚀刻所述第一金属层的所述第一部分，其中，所述蚀刻掩模保护所述第一金属层的所述第二部分；使用亚稳态等离子体来灰化所述蚀刻掩模；以及在所述第一高k电介质层之上形成第二金属层。根据一些实施例，该方法还包括使用氮气、氢气和氦气生成所述亚稳态等离子体。根据一些实施例，所述氮气和所述氦气被输入到喷头的第一输入端，并且所述氢气被输入到所述喷头的第二输入端以与由所述氮气和所述氦气生成的自由基混合。根据一些实施例，在灰化所述蚀刻掩模时，将所述第一高k电介质层暴露于所述亚稳态等离子体。根据一些实施例，所述第一高k电介质层不被热氮化。根据一些实施例，所述第一金属层为p功函数层，并且所述第二金属层为n型功函数层。
根据本公开的一些实施例，一种方法包括：在高k电介质层之上形成金属层；在所述金属层之上形成底部抗反射涂层BARC；在所述BARC之上形成光致抗蚀剂；图案化所述光致抗蚀剂；使用经图案化的光致抗蚀剂作为蚀刻掩模来蚀刻所述BARC；以及使用亚稳态等离子体去除所述BARC，其中，所述亚稳态等离子体是由以下工艺生成的，包括：将氮和氦导入喷头的第一输入端以生成等离子体；过滤以从所述等离子体去除离子，其中氮自由基和氦自由基留在所述等离子体中；以及将氢导入所述喷头的第二输入端，其中氢与氮自由基和氦自由基混合。根据一些实施例，该方法还包括将高k电介质层暴露于所述亚稳态等离子体。根据一些实施例，该方法还包括：在所述高k电介质层的相对侧上形成源极区域和漏极区域；以及在所述高k电介质层上沉积功函数层。根据一些实施例，形成所述金属层包括形成n型功函数层。根据一些实施例，形成所述金属层包括形成p型功函数层。根据一些实施例，在将所述氮和氦导入所述喷头的所述第一输入端以生成所述等离子体时，所述氢不会通过所述喷头周围的线圈。根据一些实施例，该方法还包括：形成多个晶体管，包括形成多个高k电介质层，其中，所述多个高k电介质层由相同的高k电介质材料形成；使用亚稳态等离子体执行多个处理工艺，其中氮、氢和氦用作工艺气体，其中在所述多个高k电介质层之一上执行所述多个处理工艺中的每个处理工艺，并且所述多个处理工艺中的氮流速彼此不同；以及确定所述多个晶体管的阈值电压，以建立氮流速与所述阈值电压之间的相关性。根据一些实施例，所述多个处理工艺中的氢流速彼此相同，并且所述多个处理工艺中的氦流速彼此相同。
根据本公开的一些实施例，一种方法包括：在晶圆上形成第一高k电介质层和第二高k电介质层，其中，所述第一高k电介质层和所述第二高k电介质层由相同的高k电介质材料形成；使用第一亚稳态等离子体工艺在所述第一高k电介质层上执行第一处理工艺，其中氮、氢和氦用作工艺气体，并且所述氮具有第一流速；使用第二亚稳态等离子体工艺在所述第二高k电介质层上执行第二处理工艺，其中氮、氢和氦用作工艺气体，并且所述氮具有第二流速；以及分别在所述第一高k电介质层和所述第二高k电介质层之上形成第一金属层和第二金属层。根据一些实施例，所述第一处理工艺和所述第二处理工艺中的氢流速彼此相同，并且所述第一处理工艺和所述第二处理工艺中的氦流速彼此相同。根据一些实施例，所述第一高k电介质层和所述第二高k电介质层位于所述晶圆的同一管芯中。根据一些实施例，所述第一高k电介质层和所述第二高k电介质层是n型晶体管的部分。
以上概述了若干实施例的特征，使得本领域技术人员能够更好地理解本公开的各个方面。本领域技术人员应当理解，他们可以容易地将本公开用作设计或修改其他工艺和结构以实现相同目的和/或达到本文介绍的实施例的相同优点的基础。本领域技术人员还应当认识到，这样的等效构造不会脱离本公开的精神和范围，并且可以在不脱离本公开的精神和范围的情况下对这样的等效构造进行各种改变、替换和变换。
示例1.一种用于制作半导体器件的方法，包括：在第一半导体区域之上形成第一高k电介质层；在第二半导体区域之上形成第二高k电介质层；形成第一金属层，所述第一金属层包括位于所述第一高k电介质层之上的第一部分和位于所述第二高k电介质层之上的第二部分；在所述第一金属层的所述第二部分之上形成蚀刻掩模；蚀刻所述第一金属层的所述第一部分，其中，所述蚀刻掩模保护所述第一金属层的所述第二部分；使用亚稳态等离子体来灰化所述蚀刻掩模；以及在所述第一高k电介质层之上形成第二金属层。
示例2.根据示例1所述的方法，还包括使用氮气、氢气和氦气生成所述亚稳态等离子体。
示例3.根据示例2所述的方法，其中，所述氮气和所述氦气被输入到喷头的第一输入端，并且所述氢气被输入到所述喷头的第二输入端以与由所述氮气和所述氦气生成的自由基混合。
示例4.根据示例2所述的方法，其中，所述氮气具有小于约10000sccm的流速。
示例5.根据示例1所述的方法，其中，在灰化所述蚀刻掩模时，所述第一高k电介质层被暴露于所述亚稳态等离子体。
示例6.根据示例1所述的方法，其中，所述第一高k电介质层不被热氮化。
示例7.根据示例1所述的方法，其中，所述第一金属层为p型功函数层，并且所述第二金属层为n型功函数层。
示例8.一种用于制作半导体器件的方法，包括：在高k电介质层之上形成金属层；在所述金属层之上形成底部抗反射涂层BARC；在所述BARC之上形成光致抗蚀剂；图案化所述光致抗蚀剂；使用经图案化的光致抗蚀剂作为蚀刻掩模来蚀刻所述BARC；以及使用亚稳态等离子体去除所述BARC，其中，所述亚稳态等离子体是由以下工艺生成的，所述工艺包括：将氮和氦导入喷头的第一输入端以生成等离子体；过滤以从所述等离子体中去除离子，其中氮自由基和氦自由基留在所述等离子体中；以及将氢导入所述喷头的第二输入端，其中氢与所述氮自由基和所述氦自由基混合。
示例9.根据示例8所述的方法，其中，所述氮具有小于约10000sccm的流速。
示例10.根据示例8所述的方法，还包括将高k电介质层暴露于所述亚稳态等离子体。
示例11.根据示例8所述的方法，还包括：在所述高k电介质层的相对侧上形成源极区域和漏极区域；以及在所述高k电介质层上沉积功函数层。
示例12.根据示例8所述的方法，其中，形成所述金属层包括形成n型功函数层。
示例13.根据示例8所述的方法，其中，形成所述金属层包括形成p型功函数层。
示例14.根据示例8所述的方法，其中，在将所述氮和氦导入所述喷头的所述第一输入端以生成所述等离子体时，所述氢不会通过所述喷头周围的线圈。
示例15.根据示例8所述的方法，还包括：形成多个晶体管，包括形成额外的多个高k电介质层，其中，所述额外的多个高k电介质层由相同的高k电介质材料形成；使用亚稳态等离子体执行多个处理工艺，其中氮、氢和氦用作工艺气体，其中在所述额外的多个高k电介质层之一上执行所述多个处理工艺中的每个处理工艺，并且所述多个处理工艺中的氮流速彼此不同；以及确定所述多个晶体管的阈值电压，以建立氮流速与所述阈值电压之间的相关性。
示例16.根据示例15所述的方法，其中，所述多个处理工艺中的氢流速彼此相同，并且所述多个处理工艺中的氦流速彼此相同。
示例17.一种用于制作半导体器件的方法，包括：在衬底上形成第一高k电介质层和第二高k电介质层，其中，所述第一高k电介质层和所述第二高k电介质层由相同的高k电介质材料形成；使用第一亚稳态等离子体工艺在所述第一高k电介质层上执行第一处理工艺，其中氮、氢和氦用作工艺气体，并且所述氮具有第一流速；使用第二亚稳态等离子体工艺在所述第二高k电介质层上执行第二处理工艺，其中氮、氢和氦用作工艺气体，并且所述氮具有第二流速；以及分别在所述第一高k电介质层和所述第二高k电介质层之上形成第一金属层和第二金属层。
示例18.根据示例17所述的方法，其中，所述第一处理工艺和所述第二处理工艺中的氢流速彼此相同，并且所述第一处理工艺和所述第二处理工艺中的氦流速彼此相同。
示例19.根据示例17所述的方法，其中，所述第一高k电介质层和所述第二高k电介质层位于所述衬底的同一管芯中。
示例20.根据示例17所述的方法，其中，所述第一高k电介质层和所述第二高k电介质层是n型晶体管的部分。

Claims (10)

1.一种用于制作半导体器件的方法，包括：
在第一半导体区域之上形成第一高k电介质层；
在第二半导体区域之上形成第二高k电介质层；
形成第一金属层，所述第一金属层包括位于所述第一高k电介质层之上的第一部分和位于所述第二高k电介质层之上的第二部分；
在所述第一金属层的所述第二部分之上形成蚀刻掩模；
蚀刻所述第一金属层的所述第一部分，其中，所述蚀刻掩模保护所述第一金属层的所述第二部分；
使用亚稳态等离子体来灰化所述蚀刻掩模；以及
在所述第一高k电介质层之上形成第二金属层。
2.根据权利要求1所述的方法，还包括使用氮气、氢气和氦气生成所述亚稳态等离子体。
3.根据权利要求2所述的方法，其中，所述氮气和所述氦气被输入到喷头的第一输入端，并且所述氢气被输入到所述喷头的第二输入端以与由所述氮气和所述氦气生成的自由基混合。
4.根据权利要求2所述的方法，其中，所述氮气具有小于10000sccm的流速。
5.根据权利要求1所述的方法，其中，在灰化所述蚀刻掩模时，所述第一高k电介质层被暴露于所述亚稳态等离子体。
6.根据权利要求1所述的方法，其中，所述第一高k电介质层不被热氮化。
7.根据权利要求1所述的方法，其中，所述第一金属层为p型功函数层，并且所述第二金属层为n型功函数层。
8.一种用于制作半导体器件的方法，包括：
在高k电介质层之上形成金属层；
在所述金属层之上形成底部抗反射涂层BARC；
在所述BARC之上形成光致抗蚀剂；
图案化所述光致抗蚀剂；
使用经图案化的光致抗蚀剂作为蚀刻掩模来蚀刻所述BARC；以及
使用亚稳态等离子体去除所述BARC，其中，所述亚稳态等离子体是由以下工艺生成的，所述工艺包括：
将氮和氦导入喷头的第一输入端以生成等离子体；
过滤以从所述等离子体中去除离子，其中氮自由基和氦自由基留在所述等离子体中；以及
将氢导入所述喷头的第二输入端，其中氢与所述氮自由基和所述氦自由基混合。
9.根据权利要求8所述的方法，其中，所述氮具有小于10000sccm的流速。
10.一种用于制作半导体器件的方法，包括：
在衬底上形成第一高k电介质层和第二高k电介质层，其中，所述第一高k电介质层和所述第二高k电介质层由相同的高k电介质材料形成；
使用第一亚稳态等离子体工艺在所述第一高k电介质层上执行第一处理工艺，其中氮、氢和氦用作工艺气体，并且所述氮具有第一流速；
使用第二亚稳态等离子体工艺在所述第二高k电介质层上执行第二处理工艺，其中氮、氢和氦用作工艺气体，并且所述氮具有第二流速；以及
分别在所述第一高k电介质层和所述第二高k电介质层之上形成第一金属层和第二金属层。
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