TWI727676B - 半導體元件的製造方法 - Google Patents

半導體元件的製造方法 Download PDF

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TWI727676B
TWI727676B TW109106146A TW109106146A TWI727676B TW I727676 B TWI727676 B TW I727676B TW 109106146 A TW109106146 A TW 109106146A TW 109106146 A TW109106146 A TW 109106146A TW I727676 B TWI727676 B TW I727676B
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Taiwan
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layer
dielectric layer
nitrogen
plasma
dielectric
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TW109106146A
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TW202034398A (zh
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吳少均
潘昇良
林煥哲
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台灣積體電路製造股份有限公司
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Abstract

一種方法，包括形成第一高介電常數(high k)介電層於第一半導體區上；形成第二高介電常數介電層於第二半導體區上；形成第一金屬層，其包括第一部分於第一高介電常數介電層上和第二部分於第二高介電常數介電層上；形成蝕刻遮罩於第一金屬層的第二部分上；以及蝕刻第一金屬層的第一部分。蝕刻遮罩保護第一金屬層的第二部分。使用介穩電漿(meta stable plasma)灰化蝕刻遮罩。接著，形成第二金屬層於第一高介電常數介電層上。

Description

半導體元件的製造方法
本發明實施例是關於半導體元件的形成方法，特別是關於臨界電壓(threshold voltage)的調節。
金屬氧化物半導體(metal-oxide-semiconductor,MOS)係積體電路中的基礎建構部件。金屬氧化物半導體元件的近期發展包括形成替換閘極(replacement gate)，其包括高介電常數(high k)閘極介電層和在高介電常數閘極介電層上的金屬閘極電極。替換閘極的形成通常涉及沉積高介電常數閘極介電層和在高介電常數閘極介電層上的金屬層，並接著進行化學機械拋光(chemical mechanical polish,CMP)來移除高介電常數閘極介電層和金屬層的多餘部分。金屬層的剩餘部分形成金屬閘極。
在習知的金屬氧化物半導體元件的形成方法中，當導入氨氣來處理高介電常數介電層時，可藉由進行熱退火製程來改變金屬氧化物半導體元件的臨界電壓(threshold voltage)。儘管能改變臨界電壓，調整臨界電壓至預期的數值是不可能的，並需要藉由採用不同的功函數金屬和調整其厚度來達到進一步的數值調整。
一種半導體元件的製造方法，包括:形成第一高介電常數(high-k)介電層於第一半導體區上；形成第二高介電常數介電層於第二半導體區上；形成第一金屬層，其包括第一部分於第一高介電常數介電層上和第二部分於第二高介電常數介電層上；形成蝕刻遮罩於第一金屬層的第二部分上；蝕刻第一金屬層的第一部分，其中蝕刻遮罩保護第一金屬層的第二部分；使用介穩電漿(meta stable plasma)灰化蝕刻遮罩；以及形成第二金屬層於第一高介電常數介電層上。
一種半導體元件的製造方法，包括：形成金屬層於高介電常數介電層上；形成底部抗反射塗料(bottom anti-reflective coating,BARC)於金屬層上；形成光阻於底部抗反射塗料上；圖案化光阻；使用圖案化的光阻作為蝕刻遮罩來蝕刻底部抗反射塗料；以及使用介穩電漿移除底部抗反射塗料，其中產生介穩電漿的製程包括：導入氮氣和氦氣於噴灑頭的第一進料中來產生電漿，從電漿過濾並移除離子，使氮自由基和氦自由基殘留於電漿中，以及導入氫氣於噴灑頭的第二進料中，其中氫氣與氮自由基和氦自由基混合。
一種半導體元件的製造方法，包括：形成第一高介電常數介電層和第二高介電常數介電層於基底上，其中第一高介電常數介電層和第二高介電常數介電層以相同高介電常數介電材料形成；使用第一介穩電漿製程，以氮氣、氫氣、和氦氣作為製程氣體，對第一高介電常數介電層進行第一處理製程，且氮氣具有第一流速；使用第二介穩電漿製程，以氮氣、氫氣、和氦氣作為製程氣體，對第二高介電常數介電層進行第二處理製程，且氮氣具有第二流速；以及形成第一金屬層和第二金屬層分別於第一高介電常數介電層和第二高介電常 數介電層上。
10:晶圓
20:基底
22:井區
24:隔離區
24A:頂面
26:半導體條
28:墊氧化層
30:硬遮罩層
36:凸出鰭
38:虛置閘極堆疊
40:虛置閘極介電質
42:虛置閘極電極
44:硬遮罩層
46:閘極間隔物
50:凹槽
52:磊晶區(源極/汲極區)
53:孔洞(氣隙)
58:接觸蝕刻停止層
60:層間介電質
66:底部抗反射塗料
67:箭頭
68:光阻
78:蝕刻停止層
80:層間介電質
100,200:元件區
100’,200’:元件區
124A,224A:頂面
136,236:凸出鰭
146,246:閘極間隔物
147,247:開口
152,252:源極/汲極區
154,254:介面層
156,256:高介電常數介電層
162,262:含金屬層
164,264:N型功函數層
168,268:金屬區
170,270:閘極電極
172,272:替換閘極堆疊
174,274:鰭式場效電晶體
176,276:硬遮罩
182,282:閘極接觸插塞
300:生產設備
302:晶圓座
304:噴灑頭
306A,306B:孔隙
308:盤管
310A:第一進料
310B:第二進料
320,337,338,340:曲線
322,324,326,328,330,332,334,336:資料
400:製程流程圖
402,404,406,408,410,412,414,416,418,420,422,424,426,428,430,432,434:製程
T1:(水平)厚度
T2:(垂直)厚度
Vt:臨界電壓
以下將配合所附圖式詳述本揭露之各面向。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製。事實上，可任意地放大或縮小元件的尺寸，以清楚地表現出本揭露的特徵。
第1-6、7A、7B和8-16圖是根據一些實施例繪示了形成鰭式場效電晶體(Fin Field-Effect Transistors,Fin FET)的中間階段的透視圖和剖面示意圖。
第17圖是根據一些實施例繪示了用來灰化並同時調整鰭式場效電晶體的臨界電壓(threshold voltage)的生產設備(production tool)和處理製程。
第18圖是根據一些實施例繪示了平帶電壓(flat-band voltage)作為氮氣流速的函數。
第19和20圖是根據一些實施例比較了當分別使用習知的電感耦合電漿(inductively coupled plasma,ICP)處理和介穩電漿(meta stable plasma)處理對於鰭式場效電晶體的平帶電壓所造成的效應。
第21圖是根據一些實施例繪示了被具有不同氮氣流速的介穩電漿所處理的高介電常數介電層中的氫濃度。
第22圖是根據一些實施例繪示了用來形成鰭式場效電晶體的製程流程圖。
以下揭露提供了許多的實施例或範例，用於實施本發明的不同部件。組件和配置的具體範例描述如下，以簡化本發明實施例。當然，這些僅僅 是範例，並非用以限定本發明實施例。舉例來說，敘述中提及第一部件形成於第二部件之上，可包括形成第一和第二部件直接接觸的實施例，也可包括額外的部件形成於第一和第二部件之間，使得第一和第二部件不直接接觸的實施例。另外，本發明可在各種範例中重複元件符號及/或字母。這樣重複是為了簡化和清楚的目的，其本身並非主導所討論各種實施例及/或配置之間的關係。
再者，此處可使用空間上相關的用語，如「在...之下」、「下方的」、「低於」、「在...上方」、「上方的」和類似用語可用於此，以便描述如圖所示一元件或部件和其他元件或部件之間的關係。這些空間用語企圖包括使用或操作中的裝置的不同方位。當裝置被轉至其他方位(旋轉90°或其他方位)，則在此所使用的空間相對描述可同樣依旋轉後的方位來解讀。
根據不同的實施例，提供了具有替換閘極的電晶體和調整電晶體的臨界電壓(threshold voltage)的方法。根據一些實施例，繪示了形成電晶體的中間階段。討論了一些實施例的變化。在所有不同示意圖和例式性的實施例，類似參考符號用來標示類似部件。根據一些實施例，使用鰭式場效電晶體的形成為例來解釋本發明的概念。其他種類的電晶體(如平面電晶體和環繞式閘極電晶體)也可採用於本發明的概念。
根據本發明的一些實施例，利用移除底部抗反射塗料(bottom anti-reflective coating,BARC)的灰化製程來調整鰭式場效電晶體的臨界電壓，其底部抗反射塗料是用來圖案化在閘極介電層頂部上的一膜層(可為如功函數金屬的金屬層)。調整氮氣流速來調整對應的鰭式場效電晶體的臨界電壓至所欲的數值。
根據本發明的一些實施例，第1-6、7A、7B和8-16圖繪示了形成 鰭式場效電晶體(Fin Field-Effect Transistors,Fin FET)的中間階段的剖面示意圖和透視圖。在第22圖所示的製程流程圖400中也示意地反映這些圖式所示的製程。
在第1圖中，提供了基底20。基底20可是半導體基底(如主體半導體基底(bulk semiconductor substrate)、絕緣層上半導體(semiconductor-on-insulator,SOI)基底、或其他類似材料)，其可為(例如以P型或N型摻質)摻雜或未摻雜。基底20可是晶圓10(如矽晶圓)的一部分。總體而言，絕緣層上半導體基底是在絕緣層上形成半導體材料層。絕緣層可是例如埋藏氧化層(buried oxide layer)、氧化矽層、或其他類似材料。在基底上(通常是矽基底或玻璃基底)提供絕緣層。也可使用其他基底(如多層式或梯度基底)。在一些實施例中，基底20的半導體材料可包括矽、鍺、化合物半導體(包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦)、合金半導體(包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP)、或其組合。
進一步參考第1圖，在基底20中形成井區22。個別製程繪示於第22圖的製程流程400中的製程402。根據本發明的一些實施例，井區22係透過植入N型摻質(可為磷、砷、銻、或其他類似材料)於基底20中所形成的N型井區。根據本發明的其他實施例，井區22係透過植入P型摻質(可為硼、銦、或其他類似材料)於基底20中所形成的P型井區。所得的井區22可延伸至基底20的頂面。N型或P型摻質濃度可等於或小於1018cm-3，如介於約1017cm-3和1018cm-3的範圍之中。
參照第2圖，形成隔離區24以從基底20頂面延伸至基底20中。以 下隔離區24替代地被稱為淺溝槽隔離區(shallow trench isolation,STI)。個別製程繪示於第22圖的製程流程400中的製程404。基底20位於鄰近隔離區24之間的部分被稱為半導體條(semiconductor strip)26。為了形成隔離區24，在基底20上形成並接著圖案化墊氧化層(pad oxide layer)28和硬遮罩層30。墊氧化層28可是以氧化矽形成的薄膜。根據本發明的一些實施例，在熱氧化製程中形成墊氧化層28，其中氧化了基底20的頂面層。墊氧化層28充當基底20和硬遮罩層30之間的黏著層(adhesion layer)。墊氧化層28也可充當用來蝕刻硬遮罩層30的蝕刻停止層。根據本發明的一些實施例，硬遮罩層30可是以氮化矽形成，例如使用低壓化學氣相沉積(low-pressure chemical vapor deposition,LPCVD)。根據本發明的其他實施例，藉由矽的熱氮化或電漿輔助化學氣相沉積(plasma enhanced chemical vapor deposition,PECVD)來形成硬遮罩層30。在硬遮罩層30上形成並接著圖案化光阻(未繪示)。然後，使用圖案化的光阻作為蝕刻遮罩來圖案化硬遮罩層30，以形成硬遮罩30，如第2圖所示。
接著，使用圖案化的硬遮罩層30作為蝕刻遮罩來蝕刻墊氧化層28和基底20，緊接著以介電材料填充在基底20中所得的溝槽。進行平坦化製程(如化學機械拋光(chemical mechanical polish,CMP)製程或機械研磨(mechanical grinding)製程)來移除介電材料的多餘部分，而介電材料的剩餘部分係隔離區24。隔離區24可包括內襯介電質(未繪示)，其可是透過基底20表面層的熱氧化所形成的熱氧化物。內襯介電質也可是使用例如原子層沉積(atomic layer deposition,ALD)、高密度電漿化學氣相沉積(high-density plasma chemical vapor deposition,HDPCVD)、或化學氣相沉積(chemical vapor deposition,CVD)所形成沉積的氧化矽層、氮化矽層、或其他類似材料。隔離區24也可包括內襯氧 化物上的介電材料，其中可使用流動性化學氣相沉積(flowable chemical vapor deposition,FCVD)、旋轉塗布(spin-on coating)、或其他類似方法來形成其介電材料。根據一些實施例，在內襯介電質上的介電材料可包括氧化矽。
硬遮罩30的頂面和隔離區24的頂面可實質上彼此齊平。半導體條26介於鄰近隔離區24之間。根據本發明的一些實施例，半導體條26係原本基底20的部分，且因此半導體條26的材料與基底20的材料相同。根據本發明的替代實施例，半導體條26係替換條，其藉由蝕刻基底20介於隔離區24之間的部分來形成凹槽，並在凹槽中進行磊晶來再成長另一種半導體材料來形成替換條。因此，以不同於基底20的半導體材料來形成半導體條26。根據一些實施例，以鍺化矽、碳化矽、或III-V族化合物半導體材料來形成半導體條26。
參考第3圖，凹蝕隔離區24，使得半導體條26的頂部凸出高於隔離區24剩餘部分的頂面24A來形成凸出鰭36。個別製程繪示於第22圖的製程流程400中的製程406。可使用乾蝕刻製程來進行蝕刻，其中使用例如HF3和NH3作為蝕刻氣體。在蝕刻製程期間，可產生電漿。也可包括氬氣。根據本發明的替代實施例，使用濕蝕刻製程來進行隔離區24的凹蝕。蝕刻化學品可包括例如HF。
在上述的實施例中，可藉由任何合適方法來圖案化鰭。舉例來說，可使用一或多個光微影製程(包括雙重圖案化或多重圖案化製程)來圖案化鰭。總體而言，雙重圖案化或多重圖案化製程結合光微影和自我對準製程，讓創造出的圖案具有節距小於例如使用單一直接光微影製程所形成的節距。舉例來說，在一實施例中，在基底上形成並使用光微影製程圖案化犧牲層。使用自我對準製程，沿著圖案化的犧牲層來形成間隔物。然後，移除犧牲層，並可接著使用剩餘的間隔物或心軸(mandrel)來圖案化鰭。
參考第4圖，形成虛置閘極堆疊38延伸於(凸出)鰭36的頂表面上和側壁上。個別製程繪示於第22圖的製程流程400中的製程408。虛置閘極堆疊38可包括虛置閘極介電質40和於虛置閘極介電質40上的虛置閘極電極42。可使用例如多晶矽，且也可使用其他材料來形成虛置閘極電極42。每個虛置閘極堆疊38也可包括於虛置閘極電極42上的一個(或複數個)硬遮罩層44。可以氮化矽、氧化矽、碳氮化矽、或其複合層來形成硬遮罩層44。虛置閘極堆疊38可跨越單一或複數個凸出鰭36及/或隔離區24。虛置閘極堆疊38也具有垂直於凸出鰭36的長度方向(lengthwise direction)。
接著，在虛置閘極堆疊38的側壁上形成閘極間隔物46。個別製程亦繪示於第22圖的製程流程400中的製程408。根據本發明的一些實施例，可以介電材料(如氮化矽、碳氮化矽、或其他類似材料)形成閘極間隔物46，其可具有單膜層結構或包括複數個介電層的多膜層結構。
接著，進行蝕刻製程來蝕刻凸出鰭36未被虛置閘極堆疊38和閘極間隔物46覆蓋的部分，所得的結構繪示於第5圖中。個別製程繪示於第22圖的製程流程400中的製程410。凹蝕可為異向性(anisotropic)，因此凸出鰭36在虛置閘極堆疊38和閘極間隔物46正下方的部分受到保護，未被蝕刻。根據一些實施例，被凹蝕的半導體條26頂面可低於隔離區24的頂面24A，因而形成了凹槽50。凹槽50包括位在虛置閘極堆疊38兩側上的部分，以及介於剩餘部分凸出鰭36之間的部分。
接著，藉由在凹槽50中選擇性地成長(透過磊晶)半導體材料來形成磊晶區(源極/汲極區)52，所得的結構繪示於第6圖中。個別製程繪示於第22圖的製程流程400中的製程412。取決於所得的鰭式場效電晶體為P型鰭式場效 電晶體或N型鰭式場效電晶體，可在磊晶進行中原位(in-situ)摻雜P型或N型摻質。舉例來說，當所得的鰭式場效電晶體為P型鰭式場效電晶體時，可成長鍺硼化矽(SiGeB)、硼化矽(SiB)、或其他類似材料。反之，當所得的鰭式場效電晶體為N型鰭式場效電晶體時，可成長磷化矽(SiP)、碳磷化矽(SiCP)、或其他類似材料。根據本發明的替代實施例，磊晶區52包括III-V族化合物半導體(如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、其組合、或其複合層)。在以磊晶區52填充凹槽50之後，磊晶區52的進一步磊晶成長造成磊晶區52水平地擴張，並可形成刻面(facet)。磊晶區52的進一步成長也可造成鄰近磊晶區52彼此結合。可產生孔洞(氣隙)53。根據本發明的一些實施例，可在磊晶區52頂面仍然是波浪狀時，或在結合的磊晶區52頂面變平坦時(藉由在磊晶區52上進一步成長來達成，如第6圖所示)完成磊晶區52的形成。
在磊晶步驟之後，可進一步以P型或N型摻質植入磊晶區52來形成源極和汲極區，其也使用參考符號52表示。根據本發明的替代實施例，當在磊晶期間以P型或N型摻質原位摻雜磊晶區52時，則略過植入製程。
第7A圖繪示了在接觸蝕刻停止層(contact etch stop layer,CESL)58和層間介電質(inter-layer dielectric,ILD)60形成之後的結構透視圖。個別製程繪示於第22圖的製程流程400中的製程414。可以氧化矽、氮化矽、碳氮化矽、或其他類似材料，並可使用化學氣相沉積、原子層沉積、或其他類似方法來形成接觸蝕刻停止層58。層間介電質60可包括使用例如流動性化學氣相沉積、旋轉塗布、化學氣相沉積、或其他沉積方法所形成的介電材料。層間介電質60可以含氧介電材料所形成，其材料可是使用四乙氧基矽烷氧化物(tetra ethyl ortho silicate oxide)作為前驅物(precursor)、磷矽酸玻璃(phospho-silicate glass,PSG)、硼矽酸玻璃(boro-silicate glass,BSG)、硼摻雜磷矽酸玻璃(boron-doped phospho-silicate glass,BPSG)、或其他類似材料所形成的矽氧基材料。可進行平坦化製程(如化學機械拋光製程或機械研磨製程)來使層間介電質60、虛置閘極堆疊38、和閘極間隔物46的頂面彼此齊平。
第7B圖繪示了在相同基底20上並在相同晶粒和相同晶圓中，在第一鰭式場效電晶體和第二鰭式場效電晶體的形成中的中間結構的剖面示意圖。第一鰭式場效電晶體和第二鰭式場效電晶體中任一個可對應於從第7A圖中含7B-7B線段的垂直平面所獲得的剖面示意圖。在元件區100中形成第一鰭式場效電晶體，並在元件區200中形成第二鰭式場效電晶體。第一鰭式場效電晶體和第二鰭式場效電晶體的臨界電壓可彼此不同。根據本發明的一些實施例，第一鰭式場效電晶體和第二鰭式場效電晶體均為N型鰭式場效電晶體或P型鰭式場效電晶體。根據本發明的替代實施例，第一鰭式場效電晶體為N型鰭式場效電晶體，且第二鰭式場效電晶體為P型鰭式場效電晶體。或者，第一鰭式場效電晶體為P型鰭式場效電晶體，且第二鰭式場效電晶體為N型鰭式場效電晶體。在所討論的範例中，繪示了N型鰭式場效電晶體和P型鰭式場效電晶體的形成，而也思考了其他鰭式場效電晶體的組合。
為了區別第一鰭式場效電晶體和第二鰭式場效電晶體的部件，可使用在第7A圖中的對應部件的參考符號加上100後的參考符號來代表在第一鰭式場效電晶體中的部件，且可使用在第7A圖中的對應部件的參考符號加上200後的參考符號來代表在第二鰭式場效電晶體中的部件。舉例來說，在第7B圖中的源極/汲極區152和252對應於在第7A圖中的源極/汲極區52，且在第7B圖中的 閘極間隔物146和246對應於在第7A圖中的閘極間隔物46。可在共用的製程中形成在第一鰭式場效電晶體和第二鰭式場效電晶體中的對應部件。
在形成了第7A和7B圖中所示的結構之後，以金屬閘極和替換閘極介電質取代虛置閘極堆疊38(包括硬遮罩層44、虛置閘極電極42、和虛置閘極介電質40)，如第8-16圖的製程所示。在第8至16圖中，繪示了隔離區24的頂面124A和224A，且凸出鰭136和236分別凸出高於頂面124A和224A。
為了形成替換閘極，移除如第7A和7B圖中所示的硬遮罩層44、虛置閘極電極42、和虛置閘極介電質40，形成如第8圖所示的開口147和247。個別製程繪示於第22圖的製程流程400中的製程416。於開口147和247分別露出凸出鰭136和236的頂面和側壁。
接著，參考第9圖，形成閘極介電質，其分別延伸進入開口147和247中。個別製程繪示於第22圖的製程流程400中的製程418。根據本發明的一些實施例，閘極介電質包括介面層(interfacial layer,IL)154和254，其分別在凸出鰭136和236的露出表面上形成。介面層154和254可包括氧化層(如氧化矽層)，其透過凸出鰭136和236的熱氧化、化學氧化製程、或沉積製程所形成。閘極介電質也可包括於對應介面層154和254上的高介電常數介電層156和256。高介電常數介電層156和256可以高介電常數介電材料(如氧化鉿、氧化鑭、氧化鋁、氧化鋯、或其他類似材料)所形成。高介電常數介電材料的介電常數(k值)高於3.9，且可高於約7.0，有時高達21.0或更高。高介電常數介電層156和256在上方，並可接觸個別下方的介面層154和254。形成高介電常數介電層156和256作為順應層，並分別延伸於凸出鰭136和236的露出表面上以及閘極間隔物146和246的頂面上和側壁上。根據本發明的一些實施例，使用原子層沉積或化學氣相 沉積來形成高介電常數介電層156和256。
進一步參考第9圖，形成金屬層。個別製程繪示於第22圖的製程流程400中的製程420。金屬層包括在元件區100中的含金屬層162和在元件區200中的含金屬層262。透過沉積形成含金屬層162和262。可使用順應性沉積方法(如原子層沉積或化學氣相沉積)來進行沉積，使得含金屬層162和262(以及各個次層)的水平部分的水平厚度和垂直部分的垂直厚度實質上彼此等同。舉例來說，水平厚度T1和垂直厚度T2可具有小於厚度T1或厚度T2的約20%或10%的差值。根據本發明的一些實施例，含金屬層162和262延伸進入開口147和247中(第8圖)，並包括在層間介電質60的一些部分。
含金屬層162和262可包括P型功函數金屬層(如TiN層)。根據本發明的一些實施例，個別含金屬層162和262為單膜層(如TiN層)。根據其他實施例，個別含金屬層162和262為包括以不同材料形成的複數個膜層的複合層。舉例來說，個別含金屬層162和262可分別包括TiN層、TaN層、和另一個TiN層。
在含金屬層162和262上形成底部抗反射塗料66。個別製程繪示於第22圖的製程流程400中的製程422。根據本發明的一些實施例，以(烘烤後並因此交聯的)光阻形成底部抗反射塗料66。接著，塗覆並圖案化光阻68，使得光阻68在元件區100中的部分被移除，且保留光阻68在元件區200中的部分。個別製程繪示於第22圖的製程流程400中的製程424。
第10圖繪示蝕刻製程，其中光阻68被作為蝕刻遮罩。在蝕刻製程中移除底部抗反射塗料66在元件區100中的部分。個別製程繪示於第22圖的製程流程400中的製程426。在後續的製程中，如第11圖所示，移除光阻68並露出下方的底部抗反射塗料66。
然後，進行蝕刻製程來蝕刻含金屬層162。個別製程繪示於第22圖的製程流程400中的製程428。結果是，露出高介電常數介電層156。所得的結構繪示於第12圖中。在蝕刻製程期間，使用底部抗反射塗料66作為蝕刻遮罩來保護含金屬層262。根據本發明的一些實施例，透過濕蝕刻進行蝕刻製程。舉例來說，當以TiN形成含金屬層162時，蝕刻化學品可包括化學溶液(包括氨水(NH3)、雙氧水(H2O2)、和水)。根據替代實施例，可使用乾蝕刻製程。
第13圖繪示了透過灰化製程來移除底部抗反射塗料66，其中產生了電漿，以箭頭67代表。個別製程繪示於第22圖的製程流程400中的製程430。在第17圖中繪示了用來灰化底部抗反射塗料66的生產設備(production tool)300。配置生產設備300來產生電漿，例如透過電感耦合電漿(inductively coupled plasma,ICP)。再者，放置晶圓10於晶圓座302上，其可為靜電吸盤(electric chuck,E-Chuck)。噴灑頭304置於晶圓10上，其中從製程氣體產生電漿。電漿包括離子和自由基，其藉由噴灑頭304過濾，使得自由基得以通過噴灑頭304中的孔隙306A至晶圓10，而離子受阻擋無法通過孔隙306A。
配置生產設備300來產生介穩電漿(meta stable plasma)，其具有比典型電漿更長的壽命。介穩狀態是原子的激發態或具有比其他激發態的壽命更長的其他系統。舉例來說，在介穩狀態的原子和自由基可維持激發約在1秒鐘之數量級的長時間。然而，介穩狀態具有比穩定基態更短的壽命。藉由導入氦氣和氮氣於噴灑頭304中來產生介穩狀態，從He產生He*自由基來產生電漿。
如第17圖所示，噴灑頭304為雙充氣(dual plenum)噴灑頭，其包括兩個進料(input)310A和310B。第一進料310A可在噴灑頭304頂端。根據一些實施例，透過第一進料310A導入氮氣和氦氣的混合氣體於噴灑頭304的內 腔，且因此藉由例如盤管(coils)308產生N+和He+離子、e-電子、和N*和He*自由基。連接內腔至孔隙306A，其配置來困住N+和He+離子，並允許N*和He*自由基通過。
第二進料310B可位在噴灑頭304的側邊上，且第二進料310B並未連接至內腔。根據一些實施例，透過第二進料310B導入氫氣於噴灑頭304。第二進料310B連接至孔隙306B，其面向晶圓10。因此，氫氣繞過盤管308，且並未被盤管308激發。因此，氫氣具有很低的能量。
進一步參考第17圖，當透過噴灑頭304側壁內的管道(tunnel)從孔隙306B導入氫氣至出料時，氫氣遇到He*和N*自由基而被激發，並因此產生了H*自由基。由於H*從He*和N*(而非直接從盤管308)接收能量，H*的能態很低。所得的H*的低能態讓調整在高介電常數介電層156(第13圖)中受困的電荷種類和量成為可能。受困電荷影響在元件區100中所得的鰭式場效電晶體的平帶電壓(flat-band voltage)(和臨界電壓)。
露出高介電常數介電層156於介穩電漿的結果是，在電漿中產生的離子和分子(如N+和NH-等)受困於高介電常數介電層156中，對應的電荷也因此受困於高介電常數介電層156中。受困電荷導致在元件區100中的鰭式場效電晶體的臨界電壓的改變和調整，其顯露於第18圖中。
第18圖繪示了實驗結果，其中繪示平帶電壓作為氮氣流速的函數。從金屬氧化物半導體電容獲得平帶電壓，其閘極包括使用介穩電漿做處理後的高介電常數閘極介電質，其參考第17圖所述。X軸代表氮氣流速，而Y軸代表金屬氧化物半導體電容的平帶電壓。當氫氣流速為4000sccm，且氦氣流速為1000sccm時，則獲得第18圖中的結果。當使用不同氮氣流速來進行灰化製程(如 在第13圖中)，則獲得平帶電壓的曲線320。曲線320透露出不同氮氣流速(在底部抗反射塗料66的灰化中)導致具有不同平帶電壓的金屬氧化物半導體電容，其平帶電壓緊密地與臨界電壓相關。再者，更高的平帶電壓與更高的臨界電壓相關。因此，曲線320也透露出不同氮氣流速(在底部抗反射塗料66的灰化中)導致具有不同臨界電壓的鰭式場效電晶體。
如在第18圖中所示，當氦氣流速在一特定數值時(如約2000sccm)，對應的平帶電壓(因此臨界電壓)最低。當增加或減少氦氣流速時，平帶電壓則增加。這可藉由改變H*、H*N*、NH*自由基的量所造成，如在第18圖中所示。根據本發明的一些實施例，介穩電漿處理製程使用小於約10000sccm的氮氣流速。介穩型態的來源也能藉由氦氣、氮氣、及/或氧氣作為次要注入氣體(side injection gas)來產生。
根據一些實施例，可建立臨界電壓和氮氣流速之間的關聯。舉例來說，可製造複數個樣品，例如第14圖中所示的結構。每個樣品使用特定氮氣流速來經歷灰化製程(來移除底部抗反射塗料66)，且用在不同樣品的氮氣流速也彼此不同。量測/判斷樣品的臨界電壓(和平帶電壓)，使得臨界電壓和對應氮氣流速之間的關聯性被建立。在鰭式場效電晶體的製造中，當一些鰭式場效電晶體預期具有特定臨界電壓時，可從其關聯性找出對應的氮氣流速，且在對應的灰化製程中採用對應的氮氣流速來調整其臨界電壓。
另外，在相同的元件晶粒上，若在同一顆晶粒上(同一片晶圓)的兩個或更多個鰭式場效電晶體(其可為N型、P型、或有些N型有些P型)企圖具有不同的臨界電壓Vt，可藉由採用不同氮氣流速來達成臨界電壓Vt的差異，而鰭式場效電晶體的其他結構和材料可彼此一致。舉例來說，兩個鰭式場效電 晶體可具有一致的功函數金屬和一致的厚度。再者，兩個或更多個鰭式場效電晶體，除了採用不同的氮氣流速以外，可共享相同的製造過程。根據一些實施例，除了元件區100和200以外，也有元件區100’和200’(示意地繪示於第13圖中)。在元件區100’中的部件和形成製程與元件區100一致，且在元件區200’中的部件和形成製程與元件區200一致。使用第一氮氣流速來灰化在元件區200中的底部抗反射塗料66，且露出在元件區100中的高介電常數介電層156於電漿，其使用第一氮氣流速(當灰化在元件區200中的底部抗反射塗料66時)所產生。使用不同於第一氮氣流速的第二氮氣流速來灰化在元件區200’中的底部抗反射塗料66，且露出在元件區100’中的高介電常數介電層156於個別電漿。結果是，在元件區100和100’的鰭式場效電晶體具有不同的臨界電壓，且在元件區100和100’的鰭式場效電晶體其餘的結構一致。在元件區100和100’中的其餘製程(如第14-16圖中所示)可彼此相同，並共享相同製程。在元件區200和200’中的其餘製程(如第14-16圖中所示)可彼此相同，並共享相同製程。
第19和20圖繪示了實驗結果，展示了當分別使用習知的電感耦合電漿和介穩電漿來灰化底部抗反射塗料66，在元件區200中的元件的平帶電壓差異。第19和20圖個別繪示平帶電壓和對應的灰化時間長度。第19圖是當使用習知的電感耦合電漿時所得的結果，其中氮氣和氫氣(不使用氦氣)是由第17圖中的第一進料310A提供，因此自由基有很高的能量。沒有氣體從第二進料310B所提供。在第19圖中獲得資料322、324、和326，其分別具有對應的灰化時間長度0秒(未灰化)、180秒、和220秒。資料顯示隨著增加灰化時間長度的增加，平帶電壓跟著增加，造成在元件區200(第13圖)的元件臨界電壓的增加。這是不想要的，因為較佳的是當調整在元件區100中的元件臨界電壓時，不改變在元 件區200中的元件臨界電壓。在元件區200中的元件臨界電壓的不想要的改變係歸因於自由基的高能量，因此含金屬層262和底部抗反射塗料66(第13圖)無法遮蔽自由基的效應。
根據本發明的實施例，第20圖是當使用介穩電漿時所得的結果。獲得資料328、330、332、334、和336，其具有對應的灰化時間長度的增加。資料顯示隨著灰化時間長度的增加，平帶電壓實質上維持穩定，並因此在元件區200(第13圖)的元件臨界電壓未改變。這允許了獨立地調整在元件區100中的鰭式場效電晶體臨界電壓，而不影響在元件區200中的鰭式場效電晶體臨界電壓。
第21圖繪示了當使用不同灰化條件時，在高介電常數介電層156中的氫濃度。X軸代表進入個別樣品的深度，而Y軸代表濃度(原子數/cm3)。曲線337、338、和340分別代表當氮氣流速為3000sccm、1500sccm、和0sccm(未進行灰化)時，所獲得的H-濃度。結果顯示曲線337具有比曲線338和340更高的氫濃度，顯示其對應於更多H-受困於高介電常數介電層156中。這也顯示3000sccm的氮氣流速對應於更多負電荷(H-)，且因此使用3000sccm氮氣灰化形成的對應電晶體具有比暴露於1500sccm氮氣灰化更高的臨界電壓。第21圖也展示了可藉由調整氮氣流速來調整電晶體的臨界電壓。
介穩電漿灰化也有助於減少TiN的氧化，其可用來形成含金屬層262。在TiN膜上進行了X射線光電子光譜(X-ray photoelectron spectroscopy,XPS)分析，TiN膜具有底部抗反射塗料形成在其上，並使用介穩電漿或習知的電感耦合電漿其中一項來灰化底部抗反射塗料。有觀察到，樣品歷經習知的電感耦合電漿灰化時，在灰化製程前具有20.0的Ti2P強度值，在灰化製程後具有18.7的Ti2P 強度值。因此，電感耦合電漿減少1.3的Ti2P強度值。相較之下，樣品歷經介穩電漿灰化時，在灰化製程前具有19.6的Ti2P強度值，在灰化製程後具有19.1的Ti2P強度值。因此，介穩電漿減少0.5的Ti2P強度值，其小於1.3。這表示當灰化上方的底部抗反射塗料66時，介穩電漿也導致TiN膜(含金屬層262)的氧化較少。
使用藉由介穩電漿產生的氫自由基來灰化並移除底部抗反射塗料66，如第13和14圖所示。第14圖繪示了在灰化底部抗反射塗料66後的結構。在此時，含金屬層262針對下方的高介電常數介電層256提供保護，使其免於接收如N+和NH-的電荷，並避免所得的鰭式場效電晶體臨界電壓的調整。
採用氮氣作為製程氣體的介穩電漿灰化製程的結果是，氮(例如以N+和NH-的形式)受困在高介電常數介電層156中。因此，介穩電漿製程可取代對高介電常數介電層進行的習知的熱氮化製程，其使用氨氣作為製程氣體。因此，根據本發明的一些實施例，在整個鰭式場效電晶體的形成中，並未對高介電常數介電層進行使用氨氣的熱氮化製程。
第15圖繪示了鰭式場效電晶體的持續形成。根據本發明的一些實施例，沉積包括在元件區100中的N型功函數層164和在元件區200中的N型功函數層264。個別製程繪示於第22圖的製程流程400中的製程432。根據一些實施例，N型功函數層164和264包括如TiAl層的單膜層。根據其他實施例，個別N型功函數層164和264包括複合層，其包括TiN層、TaN層、和鋁基層(例如以TiAlN、TiAlC、TaAlN、或TaAlC所形成)。接著，沉積阻擋層和填充金屬來形成金屬區168和268。個別製程繪示於第22圖的製程流程400中的製程434。然後，進行平坦化製程(如化學機械拋光製程或機械研磨製程)來形成閘極電極170和270。也形成替換閘極堆疊172和272，其包括對應的閘極電極170和270和對應的閘極 介電質。從而形成鰭式場效電晶體174和274。
參照第16圖，凹蝕替換閘極堆疊172和272，並以介電材料(如SiN)填充來形成硬遮罩176和276。在硬遮罩176和276和層間介電質60上形成蝕刻停止層(etch stop layer)78。以介電材料(可包括碳化矽、氮化矽、氧氮化矽、或其他類似材料)形成蝕刻停止層78。在蝕刻停止層78上形成層間介電質80，並在層間介電質80中形成閘極接觸插塞182和282。
本發明的實施例具有一些有利的特徵。透過使用介穩電漿的灰化來移除蝕刻遮罩，其用來蝕刻在電晶體的高介電常數介電層上所形成的金屬層。介穩電漿的能量很低。因此，不像習知的電感耦合電漿灰化(其調整臨界電壓的效應趨近飽和)，可藉由調整氮氣流速來調整電晶體的臨界電壓。而且，具有在灰化的遮罩正下方的金屬層的電晶體受到其金屬層保護，免於被介穩電漿影響，且因此個別電晶體的臨界電壓未被灰化製程影響。
根據本發明的一些實施例，一種半導體元件的製造方法，包括：形成第一高介電常數介電層於第一半導體區上；形成第二高介電常數介電層於第二半導體區上；形成第一金屬層，其包括第一部分於第一高介電常數介電層上和第二部分於第二高介電常數介電層上；形成蝕刻遮罩於第一金屬層的第二部分上；蝕刻第一金屬層的第一部分，其中蝕刻遮罩保護第一金屬層的第二部分；使用介穩電漿灰化蝕刻遮罩；以及形成第二金屬層於第一高介電常數介電層上。根據一些實施例，半導體元件的製造方法更包括使用氮氣、氫氣、和氦氣產生該介穩電漿。根據一些實施例，輸入氮氣和氦氣於噴灑頭的第一進料中，並輸入氫氣於噴灑頭的第二進料中來與氮氣和氦氣產生的自由基混合。根據一些實施例，當灰化蝕刻遮罩時，第一高介電常數介電層暴露於介穩電漿。根據 一些實施例，第一高介電常數介電層未被熱氮化。根據一些實施例，第一金屬層為P型功函數層，而第二金屬層為N型功函數層。
根據本發明的一些實施例，一種半導體元件的製造方法，包括：形成金屬層於高介電常數介電層上；形成底部抗反射塗料於金屬層上；形成光阻於底部抗反射塗料上；圖案化光阻；使用圖案化的光阻作為蝕刻遮罩來蝕刻底部抗反射塗料；以及使用介穩電漿移除底部抗反射塗料，其中產生介穩電漿的製程包括：導入氮氣和氦氣於噴灑頭的第一進料中來產生電漿，從電漿過濾並移除離子，使氮自由基和氦自由基殘留於電漿中，以及導入氫氣於噴灑頭的第二進料中，其中氫氣與氮自由基和氦自由基混合。根據一些實施例，半導體元件的製造方法更包括暴露高介電常數介電層於介穩電漿。根據一些實施例，半導體元件的製造方法更包括形成源極和汲極區於高介電常數介電層的兩側上；以及沉積功函數層於高介電常數介電層上。根據一些實施例，形成金屬層包括形成N型功函數層。根據一些實施例，形成金屬層包括形成P型功函數層。根據一些實施例，當導入氮氣和氦氣於噴灑頭的第一進料中來產生電漿時，氫氣未通過環繞噴灑頭的盤管。根據一些實施例，半導體元件的製造方法更包括形成複數個電晶體，包括形成額外複數個高介電常數介電層，其中額外高介電常數介電層以相同的高介電常數介電材料形成；使用介穩電漿，以氮氣、氫氣、和氦氣作為製程氣體，進行複數個處理製程，其中每個處理製程進行於額外高介電常數介電層的其中之一，且在處理製程中的氮氣流速彼此不同；以及決定電晶體的臨界電壓，來建立氮氣流速和臨界電壓之間的關聯性。根據一些實施例，在處理製程中的氫氣流速彼此相同，且在處理製程中的氦氣流速彼此相同。
根據本發明的一些實施例，一種半導體元件的製造方法，包括： 形成第一高介電常數介電層和第二高介電常數介電層於基底上，其中第一高介電常數介電層和第二高介電常數介電層以相同高介電常數介電材料形成；使用第一介穩電漿製程，以氮氣、氫氣、和氦氣作為製程氣體，對第一高介電常數介電層進行第一處理製程，且氮氣具有第一流速；使用第二介穩電漿製程，以氮氣、氫氣、和氦氣作為製程氣體，對第二高介電常數介電層進行第二處理製程，且氮氣具有第二流速；以及形成第一金屬層和第二金屬層分別於第一高介電常數介電層和第二高介電常數介電層上。根據一些實施例，在第一處理製程和第二處理製程中的氫氣流速彼此相同，且在第一處理製程和第二處理製程中的氦氣流速彼此相同。根據一些實施例，第一高介電常數介電層和第二高介電常數介電層都在晶圓的同一個晶粒中。根據一些實施例，第一高介電常數介電層和第二高介電常數介電層為N型電晶體的部件。
以上概述數個實施例之部件，以便在本發明所屬技術領域中具有通常知識者可以更加理解本發明的觀點。在本發明所屬技術領域中具有通常知識者應理解，他們能輕易地以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解，此類等效的結構並無悖離本發明的精神與範圍，且他們能在不違背本發明之精神和範圍下，做各式各樣的改變、取代和替換。
20:基底
58:接觸蝕刻停止層
60:層間介電質
100,200:元件區
124A,224A:頂面
136,236:凸出鰭
146,246:閘極間隔物
152,252:源極/汲極區
154,254:介面層
156,256:高介電常數介電層
262:含金屬層
164,264:N型功函數層

Claims (13)

  1. 一種半導體元件的製造方法，包括：形成一第一高介電常數(high-k)介電層於一第一半導體區上；形成一第二高介電常數介電層於一第二半導體區上；形成一第一金屬層，其包括一第一部分於該第一高介電常數介電層上和一第二部分於該第二高介電常數介電層上；形成一蝕刻遮罩於該第一金屬層的該第二部分上；蝕刻該第一金屬層的該第一部分，其中該蝕刻遮罩保護該第一金屬層的該第二部分；使用氮氣、氫氣、和氦氣產生一介穩電漿(meta stable plasma)，其中輸入氮氣和氦氣於一噴灑頭的一第一進料(input)中，並輸入氫氣於該噴灑頭的一第二進料中來與氮氣和氦氣產生的自由基混合；使用該介穩電漿灰化該蝕刻遮罩；以及形成一第二金屬層於該第一高介電常數介電層上。
  2. 如請求項1之半導體元件的製造方法，其中氮氣具有小於約10000sccm的流速。
  3. 如請求項1-2中任一項之半導體元件的製造方法，其中當灰化該蝕刻遮罩時，該第一高介電常數介電層暴露於該介穩電漿。
  4. 如請求項1-2中任一項之半導體元件的製造方法，其中該第一高介電常數介電層未被熱氮化。
  5. 如請求項1-2中任一項之半導體元件的製造方法，其中該第一金屬層為一P型功函數層，而該第二金屬層為一N型功函數層。
  6. 一種半導體元件的製造方法，包括：形成一金屬層於一高介電常數介電層上；形成一底部抗反射塗料(bottom anti-reflective coating,BARC)於該金屬層上；形成一光阻於該底部抗反射塗料上；圖案化該光阻；使用圖案化的該光阻作為蝕刻遮罩來蝕刻該底部抗反射塗料；以及使用一介穩電漿移除該底部抗反射塗料，其中產生該介穩電漿的製程包括：導入氮氣和氦氣於一噴灑頭的一第一進料中來產生一電漿；從該電漿過濾並移除離子，使氮自由基和氦自由基殘留於該電漿中；以及導入氫氣於該噴灑頭的一第二進料中，其中氫氣與氮自由基和氦自由基混合。
  7. 如請求項6之半導體元件的製造方法，更包括：形成源極和汲極區於該高介電常數介電層的兩側上；以及沉積一功函數層於該高介電常數介電層上。
  8. 如請求項6之半導體元件的製造方法，其中當導入氮氣和氦氣於該噴灑頭的該第一進料中來產生該電漿時，氫氣未通過環繞該噴灑頭的盤管(coils)。
  9. 如請求項6-8中任一項之半導體元件的製造方法，更包括：形成複數個電晶體，包括形成額外複數個高介電常數介電層，其中該些額外高介電常數介電層以相同的高介電常數介電材料形成；使用該介穩電漿，以氮氣、氫氣、和氦氣作為製程氣體，進行複數個處理製程，其中每個處理製程進行於該些額外高介電常數介電層的其中之一，且在該 些處理製程中的氮氣流速彼此不同；以及決定該些電晶體的臨界電壓(threshold voltage)，來建立氮氣流速和臨界電壓之間的關聯性。
  10. 如請求項9之半導體元件的製造方法，其中在該些處理製程中的氫氣流速彼此相同，且在該些處理中的氦氣流速彼此相同。
  11. 一種半導體元件的製造方法，包括：形成一第一高介電常數介電層和一第二高介電常數介電層於一基底上，其中該第一高介電常數介電層和該第二高介電常數介電層以一相同高介電常數介電材料形成；使用一第一介穩電漿製程，以氮氣、氫氣、和氦氣作為製程氣體，對該第一高介電常數介電層進行一第一處理製程，且氮氣具有一第一流速；使用一第二介穩電漿製程，以氮氣、氫氣、和氦氣作為製程氣體，對該第二高介電常數介電層進行一第二處理製程，且氮氣具有一第二流速；以及形成一第一金屬層和一第二金屬層分別於該第一高介電常數介電層和該第二高介電常數介電層上。
  12. 如請求項11之半導體元件的製造方法，其中該第一高介電常數介電層和該第二高介電常數介電層都在該基底的同一個晶粒中。
  13. 如請求項11或12之半導體元件的製造方法，其中該第一高介電常數介電層和該第二高介電常數介電層為N型電晶體的部件。
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