CN111430327B - 一种高散热扇出型封装结构及封装方法 - Google Patents

一种高散热扇出型封装结构及封装方法 Download PDF

Info

Publication number
CN111430327B
CN111430327B CN202010148685.XA CN202010148685A CN111430327B CN 111430327 B CN111430327 B CN 111430327B CN 202010148685 A CN202010148685 A CN 202010148685A CN 111430327 B CN111430327 B CN 111430327B
Authority
CN
China
Prior art keywords
layer
graphene
chip
heat dissipation
carrier plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010148685.XA
Other languages
English (en)
Other versions
CN111430327A (zh
Inventor
崔成强
杨冠南
徐广东
张昱
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangdong Fozhixin Microelectronics Technology Research Co ltd
Original Assignee
Guangdong University of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangdong University of Technology filed Critical Guangdong University of Technology
Priority to CN202010148685.XA priority Critical patent/CN111430327B/zh
Publication of CN111430327A publication Critical patent/CN111430327A/zh
Application granted granted Critical
Publication of CN111430327B publication Critical patent/CN111430327B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3738—Semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明涉及一种高散热扇出型封装结构，包括带有凸点的芯片、石墨烯载板、介电层、再布线层、塑封层、散热模块以及焊球；所述石墨烯载板的上下两侧均设置有所述再布线层，所述介电层设置在所述石墨烯载板与所述再布线层之间，所述石墨烯载板上贯穿有铜柱，所述再布线层之间通过所述铜柱进行连接，所述芯片设置在所述石墨烯载板的上方，位于所述石墨烯载板上方的再布线层与所述芯片的凸点连接，位于所述石墨烯载板下方的再布线层与所述焊球连接，所述塑封层包裹在所述芯片的外侧，所述散热模块设置在所述塑封层上。本发明的高散热扇出型封装结构为芯片扇出封装结构的高密度互连提供了平台，同时大幅提高芯片封装结构的散热能力。

Description

一种高散热扇出型封装结构及封装方法
技术领域
本发明涉及封装结构技术领域，具体涉及一种高散热扇出型封装结构及封装方法。
背景技术
随着电子产品高性能化和集成化的潮流，芯片向密度更高、速度更快、成本更低等方向发展，功率电子也逐渐采用先进的封装技术，如晶圆级封装或嵌入式封装。宽禁带半导体电力电子器件近年来不断获得技术的突破，具备广泛的市场应用前景。这类器件具备更高的效率、更高的开关频率和更高的工作温度等优势，在新能源发电、电动汽车、充电桩、电力转换及管理系统和工业电机领域等已展现出其巨大的应用潜力。
因芯片的功率提高产生了大量的热，高温条件下对封装的结构、材料和散热等方面提出了挑战，封装结构散热可以采用在塑封后的芯片背面粘贴散热器，这对高功率下的芯片散热有一定作用，但散热效果有限；陶瓷材料由于其在热、电、机械特性等方面极为稳定，被用做集成电路芯片封装。传统的方法是将芯片放置在已载有引脚架或后膜金属导线的陶瓷基板孔洞中，完成芯片与引脚或后膜金属键合点之间的电路互连，再将另一片陶瓷或金属封盖以玻璃、锡合金焊料将其与基板密封粘接而完成。然而随着芯片及功率器件的不断发展，再进一步提高芯片I/O数量，同时减小芯片尺寸，提高集成度、可靠性和散热能力等方面还存局限。
发明内容
为了解决现有的芯片封装结构散热能力等方面存在局限的问题，本发明提供了一种高散热扇出型封装结构及封装方法，采用石墨烯载板对芯片进行机械支撑，为芯片扇出封装结构的高密度互连提供了平台，同时借助石墨烯载板优异的导热性能和石墨烯散热板进行散热，大幅提高了芯片封装结构的散热能力。
为解决上述技术问题，本发明提供以下技术方案：
一种高散热扇出型封装结构，包括带有凸点的芯片、石墨烯载板、介电层、再布线层、塑封层、散热模块以及焊球；所述石墨烯载板的上下两侧均设置有所述再布线层，所述介电层设置在所述石墨烯载板与所述再布线层之间，所述石墨烯载板上贯穿有铜柱，所述再布线层之间通过所述铜柱进行连接，所述芯片设置在所述石墨烯载板的上方，位于所述石墨烯载板上方的再布线层与所述芯片的凸点连接，位于所述石墨烯载板下方的再布线层与所述焊球连接，所述塑封层包裹在所述芯片的外侧，所述散热模块设置在所述塑封层上。
在本发明中，采用石墨烯载板对芯片进行机械支撑，为芯片扇出封装结构的高密度互连提供了平台，同时借助石墨烯基板优异的导热性能和使用散热模块进行散热，大幅提高芯片封装结构的散热能力。
进一步的，所述散热模块为具有热沉形状的石墨烯散热板，散热效果好。
进一步的，所述石墨烯载板以及石墨烯散热板均由石墨烯或其复合材料制成，具有良好的散热效果。
进一步的，所述石墨烯载板的微观原子层沿其垂直方向进行布置，原子层垂直排布，利于芯片底面沿纵向散热。
进一步的，所述石墨烯散热板包括底层石墨烯原子层和上层石墨烯原子层，所述底层石墨烯原子层沿平行于所述石墨烯载板的方向进行布置，所述上层石墨烯原子层垂直行于所述石墨烯载板的方向进行布置，利用两种不一样的排布方式，极大地增强了散热效果。
一种基于上述的高散热扇出型封装结构的高散热扇出型封装方法，包括以下步骤：
S1：在具有通孔的石墨烯载板的上下两侧覆压介电层；
S2：进行金属种子层沉积、覆压感光材料、曝光显影和图形电镀操作，在介电层上形成再布线层，同时通过电镀填充石墨烯板的通孔，导通上下再布线层；
S3：去除感光材料层，并通过差别刻蚀的方法去除金属种子层；
S4：通过具有高导热性能的粘结材料将芯片安装至石墨烯载板上；
S5：进行塑封；
S6：在塑封层上方安装散热模块；
S7：在再布线层的上方涂覆光敏阻焊材料保护层，并进行曝光、显影、固化处理和表面处理；
S8：进行球下金属沉积、植球和切割，最终获得所需封装结构。
进一步的，在步骤S4中，当芯片的凸点朝下时，通过倒装的方式实现芯片的凸点与再布线层的互连，安装起来更加方便。
进一步的，在步骤S4中，当芯片的凸点朝上时，将芯片背部安装至石墨烯载板上，并通过引线键合方式实现芯片的凸点与再布线层的互连，安装起来更加方便。
进一步的，石墨烯载板的通孔通过机械、化学刻蚀或激光加工制成，通孔内壁通过物理氧化、化学腐蚀、电弧放电或绝缘层沉积的方式进行绝缘化处理，处理效果更好。
进一步的，在步骤S4中，其中的高导热性能的粘结材料为纳米铜膏或纳米银膏，介电层材料为环氧树脂、聚酰亚胺、苯并环丁烯或ABF，塑封层材料为环氧树脂、聚酯、聚氨酯、聚硅氧烷、双马来酰亚胺或氰酸酯树脂，稳定性好。
与现有技术相比，本发明具有以下有益效果：
本发明采用石墨烯载板对芯片进行机械支撑，为芯片扇出封装结构的高密度互连提供了平台，同时借助石墨烯载板优异的导热性能和石墨烯散热板的热沉沿横向和纵向原子层排布方式进行散热，大幅提高芯片封装结构的散热能力。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据附图获得其他的附图。
图1为本发明的高散热扇出型封装结构的引线键合方式的结构示意图；
图2为本发明的高散热扇出型封装结构的引线键合方式的制作过程示意图；
图3为本发明的高散热扇出型封装结构的倒装方式的结构示意图；
图4为本发明的高散热扇出型封装结构的倒装方式的制作过程示意图。
图中：1、介电层；2、石墨烯载板；3、感光材料层；4、金属种子层；5、铜柱；6、再布线层；7、芯片；8、粘结材料；9、引线；10、塑封层；11、保护层；12、焊球；13、底层石墨烯原子层；14、上层石墨烯原子层。
具体实施方式
下面将对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
本发明实施例包括：
如图1和图3所示，一种高散热扇出型封装结构，包括带有凸点的芯片7、石墨烯载板2、介电层1、再布线层6、塑封层10、散热模块以及焊球12；石墨烯载板2的上下两侧均设置有再布线层6，介电层1设置在石墨烯载板2与再布线层6之间，石墨烯载板2上贯穿有铜柱5，再布线层6之间通过铜柱5进行连接，芯片7设置在石墨烯载板2的上方，位于石墨烯载板2上方的再布线层6与芯片7的凸点连接，位于石墨烯载板2下方的再布线层6与焊球12连接，塑封层10包裹在芯片7的外侧，散热模块设置在塑封层10上。
在本发明中，采用石墨烯载板2对芯片7进行机械支撑，为芯片7扇出封装结构的高密度互连提供了平台，同时借助石墨烯基板优异的导热性能和使用散热模块进行散热，大幅提高芯片7封装结构的散热能力。
在本实施例中，散热模块为具有热沉形状的石墨烯散热板，散热效果好。
在本实施例中，石墨烯载板2以及石墨烯散热板均由石墨烯或其复合材料制成，具有良好的散热效果。
在本实施例中，石墨烯载板2的微观原子层沿其垂直方向进行布置，原子层垂直排布，利于芯片底面沿纵向散热。
如图1和图3所示，石墨烯散热板包括底层石墨烯原子层13和上层石墨烯原子层14，底层石墨烯原子层13沿平行于石墨烯载板2的方向进行布置，上层石墨烯原子层14垂直行于石墨烯载板2的方向进行布置，利用两种不一样的排布方式，极大地增强了散热效果。
如图2和图4所示，一种基于上述的高散热扇出型封装结构的高散热扇出型封装方法，包括以下步骤：
S1：在具有通孔的石墨烯载板2的上下两侧覆压介电层1；
S2：进行金属种子层4沉积、覆压感光材料、曝光显影和图形电镀操作，在介电层1上形成再布线层6，同时通过电镀填充石墨烯板的通孔，导通上下再布线层6；
S3：去除感光材料层3，并通过差别刻蚀的方法去除金属种子层4；
S4：通过具有高导热性能的粘结材料8将芯片7安装至石墨烯载板2上；
S5：进行塑封；
S6：在塑封层10上方安装散热模块；
S7：在再布线层6的上方涂覆光敏阻焊材料保护层11，并进行曝光、显影、固化处理和表面处理；
S8：进行球下金属沉积、植球和切割，最终获得所需封装结构。
如图4所示，在步骤S4中，当芯片7的凸点朝下时，通过倒装的方式实现芯片7的凸点与再布线层6的互连，安装起来更加方便。
如图2所示，在步骤S4中，当芯片7的凸点朝上时，将芯片7背部安装至石墨烯载板2上，并通过引线9键合方式实现芯片7的凸点与再布线层6的互连，安装起来更加方便。
在本实施例中，石墨烯载板2的通孔通过机械、化学刻蚀或激光加工制成，通孔内壁通过物理氧化、化学腐蚀、电弧放电或绝缘层沉积的方式进行绝缘化处理，处理效果更好。
在本实施例中，在步骤S4中，其中的高导热性能的粘结材料8为纳米铜膏或纳米银膏，介电层1材料为环氧树脂、聚酰亚胺、苯并环丁烯或ABF，塑封层10材料为环氧树脂、聚酯、聚氨酯、聚硅氧烷、双马来酰亚胺或氰酸酯树脂，稳定性好。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书内容所作的等效结构或等效流程变换，或直接或间接运用在其它相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (7)

1.一种高散热扇出型封装结构，其特征在于，包括带有凸点的芯片、石墨烯载板、介电层、再布线层、塑封层、散热模块以及焊球；所述石墨烯载板的上下两侧均设置有所述再布线层，所述介电层设置在所述石墨烯载板与所述再布线层之间，所述石墨烯载板上贯穿有铜柱，所述再布线层之间通过所述铜柱进行连接，所述芯片设置在所述石墨烯载板的上方，位于所述石墨烯载板上方的再布线层与所述芯片的凸点连接，位于所述石墨烯载板下方的再布线层与所述焊球连接，所述塑封层包裹在所述芯片的外侧，所述散热模块设置在所述塑封层上；所述散热模块为具有热沉形状的石墨烯散热板，所述石墨烯散热板包括底层石墨烯原子层和上层石墨烯原子层，所述底层石墨烯原子层沿平行于所述石墨烯载板的方向进行布置，所述上层石墨烯原子层垂直于所述石墨烯载板的方向进行布置。
2.根据权利要求1所述的高散热扇出型封装结构，其特征在于，所述石墨烯载板以及石墨烯散热板均由石墨烯或其复合材料制成。
3.根据权利要求2所述的高散热扇出型封装结构，其特征在于，所述石墨烯载板的微观原子层沿其垂直方向进行布置。
4.一种基于权利要求1所述的高散热扇出型封装结构的高散热扇出型封装方法，其特征在于，包括以下步骤：
S1：在具有通孔的石墨烯载板的上下两侧覆压介电层；
S2：进行金属种子层沉积、覆压感光材料、曝光显影和图形电镀操作，在介电层上形成再布线层，同时通过电镀填充石墨烯板的通孔，导通上下再布线层；
S3：去除感光材料层，并通过差别刻蚀的方法去除金属种子层；
S4：通过具有高导热性能的粘结材料将芯片安装至石墨烯载板上；
S5：进行塑封；
S6：在塑封层上方安装散热模块；
S7：在再布线层的上方涂覆光敏阻焊材料保护层，并进行曝光、显影、固化处理和表面处理；
S8：进行球下金属沉积、植球和切割，最终获得所需封装结构。
5.根据权利要求4所述的高散热扇出型封装方法，其特征在于，在步骤S4中，当芯片的凸点朝下时，通过倒装的方式实现芯片的凸点与再布线层的互连；当芯片的凸点朝上时，将芯片背部安装至石墨烯载板上，并通过引线键合方式实现芯片的凸点与再布线层的互连。
6.根据权利要求4所述的高散热扇出型封装方法，其特征在于，石墨烯载板的通孔通过机械、化学刻蚀或激光加工制成，通孔内壁通过物理氧化、化学腐蚀、电弧放电或绝缘层沉积的方式进行绝缘化处理。
7.根据权利要求4所述的高散热扇出型封装方法，其特征在于，在步骤S4中，其中的高导热性能的粘结材料为纳米铜膏或纳米银膏，介电层材料为环氧树脂、聚酰亚胺、苯并环丁烯或ABF，塑封层材料为环氧树脂、聚酯、聚氨酯、聚硅氧烷、双马来酰亚胺或氰酸酯树脂。
CN202010148685.XA 2020-03-05 2020-03-05 一种高散热扇出型封装结构及封装方法 Active CN111430327B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010148685.XA CN111430327B (zh) 2020-03-05 2020-03-05 一种高散热扇出型封装结构及封装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010148685.XA CN111430327B (zh) 2020-03-05 2020-03-05 一种高散热扇出型封装结构及封装方法

Publications (2)

Publication Number Publication Date
CN111430327A CN111430327A (zh) 2020-07-17
CN111430327B true CN111430327B (zh) 2022-02-11

Family

ID=71547429

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010148685.XA Active CN111430327B (zh) 2020-03-05 2020-03-05 一种高散热扇出型封装结构及封装方法

Country Status (1)

Country Link
CN (1) CN111430327B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113192936B (zh) * 2021-04-23 2024-02-13 泓林微电子（昆山）有限公司 一种双面芯片封装结构

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103801686A (zh) * 2013-12-31 2014-05-21 深圳市国创新能源研究院 一种石墨烯纳米复合材料及其制备方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003249607A (ja) * 2002-02-26 2003-09-05 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
CN105206592B (zh) * 2015-09-01 2019-01-04 华进半导体封装先导技术研发中心有限公司 扇出型封装的结构和制作方法
CN105722375B (zh) * 2016-01-29 2018-03-06 白德旭 一种石墨烯散热装置及其制备方法
US10847869B2 (en) * 2017-06-07 2020-11-24 Mediatek Inc. Semiconductor package having discrete antenna device
CN108841362A (zh) * 2018-07-23 2018-11-20 无锡市铝泰新材料股份有限公司 复合金属散热材料及其制造工艺
CN110202130A (zh) * 2019-07-03 2019-09-06 常州轻工职业技术学院 基于3d打印工艺成型的大功率led曲面石墨烯散热基板及其成型方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103801686A (zh) * 2013-12-31 2014-05-21 深圳市国创新能源研究院 一种石墨烯纳米复合材料及其制备方法

Also Published As

Publication number Publication date
CN111430327A (zh) 2020-07-17

Similar Documents

Publication Publication Date Title
US8354746B2 (en) Semiconductor package and method of forming Z-direction conductive posts embedded in structurally protective encapsulant
TWI523126B (zh) 在包含膠封或包含在具有與晶圓級晶片尺寸封裝的大型陣列中的熱膨脹係數相似的熱膨脹係數的空白晶粒之印刷電路板中形成孔穴的半導體裝置和方法
TWI479577B (zh) 形成屏障材料於晶粒之周圍以減少翹曲之半導體裝置和方法
TWI499030B (zh) 在矽穿孔插入物中形成開放孔穴以包含在晶圓級晶片尺寸模組封裝的半導體晶粒之半導體裝置和方法
US8836097B2 (en) Semiconductor device and method of forming pre-molded substrate to reduce warpage during die molding
CN102479762B (zh) 散热增益型半导体组件
TW201104797A (en) Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
CN102169842A (zh) 用于凹陷的半导体基底的技术和配置
TW201203400A (en) Semiconductor device and method of forming perforated opening in bottom substrate of flipchip pop assembly to reduce bleeding of underfill material
CN111430327B (zh) 一种高散热扇出型封装结构及封装方法
CN111430326B (zh) 一种嵌入式高散热扇出型封装结构及封装方法
CN115312406A (zh) 芯片封装结构及制备方法
CN213366617U (zh) 一种扇出型led封装结构
CN114203882A (zh) 一种扇出型led封装结构及其封装方法
Manessis et al. Development of advanced power modules for electric vehicle applications
CN213150764U (zh) 一种覆晶芯片结构
CN213242537U (zh) 一种晶圆系统级三维扇出型封装结构
ZHU et al. Electronic Packaging Technology
CN113675093B (zh) 一种双面塑封的散热结构的封装设计及制备方法
CN221282116U (zh) 封装件
CN103824820A (zh) 引线框区域阵列封装技术
CN111128751B (zh) 中介层的制造方法
CN208954980U (zh) 带一体式多层铜的陶瓷封装基板结构
Gupta et al. Next generation chip embedding technology for high efficiency power modules and power sips
US11961831B2 (en) Electronic package, semiconductor package structure, and method for manufacturing the semiconductor package structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20240206

Address after: Room A107, Research Building A, Neifo High tech Think Tank Center, Nanhai Software Technology Park, Shishan Town, Nanhai District, Foshan City, Guangdong Province, 528000

Patentee after: Guangdong fozhixin microelectronics technology research Co.,Ltd.

Country or region after: China

Address before: No.729, Dongfeng East Road, Yuexiu District, Guangzhou City, Guangdong Province 510060

Patentee before: GUANGDONG University OF TECHNOLOGY

Country or region before: China