CN111430226A - 一种多晶硅的沉积方法及其应用 - Google Patents
一种多晶硅的沉积方法及其应用 Download PDFInfo
- Publication number
- CN111430226A CN111430226A CN202010281348.8A CN202010281348A CN111430226A CN 111430226 A CN111430226 A CN 111430226A CN 202010281348 A CN202010281348 A CN 202010281348A CN 111430226 A CN111430226 A CN 111430226A
- Authority
- CN
- China
- Prior art keywords
- deposition method
- ions
- annealing treatment
- polycrystalline silicon
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000151 deposition Methods 0.000 title claims abstract description 44
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 37
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 238000000137 annealing Methods 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 230000008569 process Effects 0.000 claims abstract description 17
- 238000005468 ion implantation Methods 0.000 claims abstract description 14
- 150000002500 ions Chemical class 0.000 claims abstract description 11
- -1 silicon ions Chemical class 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 229910021645 metal ion Inorganic materials 0.000 claims abstract description 6
- 238000002513 implantation Methods 0.000 claims description 10
- 238000003860 storage Methods 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 claims description 8
- 229910052739 hydrogen Inorganic materials 0.000 claims description 8
- 239000001257 hydrogen Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims description 2
- 238000000231 atomic layer deposition Methods 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 230000008021 deposition Effects 0.000 abstract description 9
- 230000007547 defect Effects 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 230000000694 effects Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
- 230000002522 swelling effect Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
Abstract
本发明涉及一种多晶硅的沉积方法及其应用。一种多晶硅的沉积方法,包括下列步骤:在半导体载体沉积多晶硅膜,然后离子注入,再进行退火处理;其中,所述离子注入采用的离子为硅离子或金属离子。本发明可以在较低的温度下消除硅沉积时产生的缝隙或孔洞,从而减少后续工艺可能发生的缺陷。
Description
技术领域
本发明涉及半导体制备领域,特别涉及一种多晶硅的沉积方法及其应用。
背景技术
随着DRAM设备的微型化,其电容孔尺寸逐渐减小,所需的沟槽深宽比越大,这导致在沉积形成电容孔的多晶硅时容易形成孔洞或缝隙,若不处理这些孔洞(void)或缝隙(seam)会造成后续工艺进行时发生不良,例如电阻增加等。
为解决以上问题,US7157327B2公开了一种处理方法:在沉积多晶硅后,在氢气气氛下进行退火处理,这样利用退火过程中硅原子的迁移消除缝隙或孔洞,然而该技术中的退火步骤需在极高的温度下进行,加大了工艺难度。
发明内容
本发明的目的在于提供一种多晶硅的沉积方法,该方法可以在较低的温度下消除硅沉积时产生的缝隙或孔洞,从而减少后续工艺可能发生的缺陷。
为了实现以上目的,本发明提供了以下技术方案:
一种多晶硅的沉积方法,包括下列步骤:
在半导体载体沉积多晶硅膜,然后离子注入,再进行退火处理;
其中,所述离子注入采用的离子为硅离子或金属离子。
与现有技术相比,本发明在退火之前增加了离子注入,这样可以对多晶硅膜内部及表面进行改性,产生“膨胀(swelling)”效应,此时只需要低温退火处理就能使硅原子发生迁移,消除沉积时产生的缝隙或孔洞。一般情况下利用上述方法进行退火处理,只需要500℃以上即可。
上述沉积方法可用于制备电容孔结构。
上述沉积方法还可用于制备半导体器件,该半导体器件包括但不限于:集成电路装置或电容器(如DRAM、2D NAND、3D NAND等)。
一种制造DRAM的位线接触部(Data Line Contact)和存储节点接触部的方法,包括:
提供半导体衬底,衬底中包括掩埋沟道晶体管;
刻蚀衬底形成位线接触部和存储节点接触部;
以及如上文所述的多晶硅的沉积方法,其中所述半导体载体为存储节点接触部。
附图说明
通过阅读下文优选实施方式的详细描述,各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的,而并不认为是对本发明的限制。而且在整个附图中,用相同的参考符号表示相同的部件。
图1为制作BL位线触点时沉积多晶硅后的结构示意图;
图2为图1的截面图;
图3为制作单元电容孔时沉积多晶硅且凹蚀后的结构示意图;
图4为图3的截面图;
图5至图9为本发明提供的多个沉积多晶硅的方法示意图。
具体实施方式
以下,将参照附图来描述本公开的实施例。但是应该理解,这些描述只是示例性的,而并非要限制本公开的范围。此外,在以下说明中,省略了对公知结构和技术的描述,以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的,其中为了清楚表达的目的,放大了某些细节,并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的,实际中可能由于制造公差或技术限制而有所偏差,并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中,当将一层/元件称作位于另一层/元件“上”时,该层/元件可以直接位于该另一层/元件上,或者它们之间可以存在居中层/元件。另外,如果在一种朝向中一层/元件位于另一层/元件“上”,那么当调转朝向时,该层/元件可以位于该另一层/元件“下”。
在BL位线触点(Bit line Contact)的制作过程中,沉积多晶硅101后,形成如图1所示的图形,其截面形貌如图2所示,截面形貌中显示沉积的多晶硅中有缝隙102,该缝隙会使后续工艺发生缺陷。
在单元电容孔的制作过程中也存在与上述相同的问题,沉积多晶硅,经过凹蚀的多晶硅201如3所示的图形,其截面形貌如图4所示,显示有缝隙202缺陷。
为解决以上问题,本发明在沉积多晶硅后采取了以下措施:
在半导体载体沉积多晶硅,然后离子注入,再进行退火处理;
其中,所述离子注入采用的离子为硅离子或金属离子。
例如针对图2和图4所示的缺陷,通过离子注入,对多晶硅膜内部及表面进行改性,产生“膨胀(swelling)”效应,以利于后续退火时硅原子的迁移。
在离子注入步骤中,选用对器件的电特性无损或有利的,例如硅离子Si或金属离子,金属离子包括但不限于Ge、W等。对于不同的离子其适宜的工艺条件可能有区别,但针对多晶硅的改性时适宜的条件通常在以下范围选择:注入能量28~32keV,注入剂量0.8~1.2E16/cm2,其中更优选的条件是注入能量30keV,注入剂量1E16/cm2。
在离子注入完成后可以选择直接退火处理。本发明的退火处理只需要在较低的温度下进行,且达到消除缝隙和孔洞的目的。退火处理对多晶硅沉积的形貌改善有关键作用,不同气氛的退火处理条件有差异。例如,在真空气氛下进行所述退火处理的工艺条件优选为:温度500~900℃,时间≥10min。在氢气气氛下进行所述退火处理的工艺条件优选为:温度500~900℃,压力0.1~200torr,时间≥10min。
为了提高对多晶硅沉积形貌的改善效果,在离子注入之后和退火处理之前还可以增加一道工序:注入氢离子。注入氢离子的工艺条件优选为:注入能量1~20keV,注入剂量≥1E13/cm2。
上文列举了本发明的方法用于BL位线触点和单元电容孔的条件,然而本发明的应用并不仅限于此,其可用于任意半导体结构的制作,尤其用在蚀刻有沟槽的半导体结构中有显著的优势,这是因为沟槽的深宽比较高,出现缝隙和孔洞的现象更严重。具有沟槽的结构典型的代表是位线(Data Line)与电容孔结构,例如集成电路装置或电容器(如DRAM、2DNAND、3D NAND等)中的电容结构。
例如,制造DRAM的位线接触部(Data Line Contact)和存储节点接触部的方法:提供半导体衬底,衬底中包括掩埋沟道晶体管;刻蚀衬底形成位线接触部和存储节点接触孔;以及上述任意实施方式的多晶硅的沉积方法,其中,半导体载体为存储节点接触部。
结合上文所述,本发明的主要沉积方法包括但不限于如图5至9的方法。
另外,在半导体的制作中,沉积多晶硅后通常进行抛光或凹蚀的处理,因此为了避免离子注入和退火处理的不必要工作量,建议在沉积多晶硅之后和离子注入之前进行抛光或凹蚀。
在以上的描述中,对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解,可以通过各种技术手段,来形成所需形状的层、区域等。另外,为了形成同一结构,本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外,尽管在以上分别描述了各实施例,但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是,这些实施例仅仅是为了说明的目的,而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围,本领域技术人员可以做出多种替代和修改,这些替代和修改都应落在本公开的范围之内。
Claims (15)
1.一种多晶硅的沉积方法,其特征在于,包括下列步骤:
在半导体载体沉积多晶硅,然后离子注入,再进行退火处理;
其中,所述离子注入采用的离子为硅离子或金属离子。
2.根据权利要求1所述的沉积方法,其特征在于,所述半导体载体为蚀刻有接触部(contact)的半导体结构。
3.根据权利要求1所述的沉积方法,其特征在于,所述注入离子的工艺条件为:注入能量28~32keV,注入剂量0.8~1.2E16/cm2。
4.根据权利要求1所述的沉积方法,其特征在于,所述退火处理在真空气氛下或氢气气氛下进行。
5.根据权利要求4所述的沉积方法,其特征在于,在真空气氛下进行所述退火处理的工艺条件为:温度500~900℃,时间≥10min。
6.根据权利要求4所述的沉积方法,其特征在于,在氢气气氛下进行所述退火处理的工艺条件为:温度500~900℃,压力0.1~200torr,时间≥10min。
7.根据权利要求1所述的沉积方法,其特征在于,所述金属离子为Ge离子。
8.根据权利要求1-7任一项所述的沉积方法,其特征在于,所述离子注入之后和所述退火处理之前还包括:
注入氢离子。
9.根据权利要求8所述的沉积方法,其特征在于,所述注入氢离子的工艺条件为:注入能量1~20keV,注入剂量≥1E13/cm2。
10.根据权利要求1所述的沉积方法,其特征在于,在所述沉积多晶硅之后和所述离子注入之前还包括:化学机械抛光或凹蚀。
11.根据权利要求1所述的沉积方法,其特征在于,所述沉积多晶硅的方法为化学气相沉积法或原子层沉积法。
12.一种制造DRAM的位线接触部(Data Line Contact)和存储节点接触部的方法,其特征在于,包括:
提供半导体衬底,衬底中包括掩埋沟道晶体管;
刻蚀衬底形成位线接触部和存储节点接触部;
以及权利要求1-11任一项所述的多晶硅的沉积方法,其中所述半导体载体为存储节点接触部。
13.权利要求1-11任一项所述的沉积方法在制备位线(Data Line)与电容孔结构中的应用。
14.权利要求1-11任一项所述的沉积方法在制备半导体器件中的应用。
15.根据权利要求14所述的应用,其特征在于,所述半导体器件为集成电路装置或电容器。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010281348.8A CN111430226B (zh) | 2020-04-10 | 2020-04-10 | 一种多晶硅的沉积方法及其应用 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010281348.8A CN111430226B (zh) | 2020-04-10 | 2020-04-10 | 一种多晶硅的沉积方法及其应用 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111430226A true CN111430226A (zh) | 2020-07-17 |
CN111430226B CN111430226B (zh) | 2023-04-07 |
Family
ID=71553807
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010281348.8A Active CN111430226B (zh) | 2020-04-10 | 2020-04-10 | 一种多晶硅的沉积方法及其应用 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN111430226B (zh) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20050104826A (ko) * | 2004-04-29 | 2005-11-03 | 주식회사 하이닉스반도체 | 반도체 소자의 랜딩플러그 폴리 형성방법 |
CN1719582A (zh) * | 2004-07-08 | 2006-01-11 | 三星电子株式会社 | 制备多晶硅薄膜的方法以及用其制备半导体器件的方法 |
CN105047552A (zh) * | 2015-08-26 | 2015-11-11 | 上海华力微电子有限公司 | 一种制备金属栅极的方法 |
US20160020093A1 (en) * | 2014-07-18 | 2016-01-21 | ASM IP Holding B.V | Process for forming silicon-filled openings with a reduced occurrence of voids |
CN108550525A (zh) * | 2018-05-28 | 2018-09-18 | 武汉新芯集成电路制造有限公司 | 浮栅制备方法 |
-
2020
- 2020-04-10 CN CN202010281348.8A patent/CN111430226B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20050104826A (ko) * | 2004-04-29 | 2005-11-03 | 주식회사 하이닉스반도체 | 반도체 소자의 랜딩플러그 폴리 형성방법 |
CN1719582A (zh) * | 2004-07-08 | 2006-01-11 | 三星电子株式会社 | 制备多晶硅薄膜的方法以及用其制备半导体器件的方法 |
KR20060004788A (ko) * | 2004-07-08 | 2006-01-16 | 삼성전자주식회사 | 다결정 실리콘 제조방법 및 이를 이용하는 반도체 소자의제조방법 |
US20160020093A1 (en) * | 2014-07-18 | 2016-01-21 | ASM IP Holding B.V | Process for forming silicon-filled openings with a reduced occurrence of voids |
CN105047552A (zh) * | 2015-08-26 | 2015-11-11 | 上海华力微电子有限公司 | 一种制备金属栅极的方法 |
CN108550525A (zh) * | 2018-05-28 | 2018-09-18 | 武汉新芯集成电路制造有限公司 | 浮栅制备方法 |
Also Published As
Publication number | Publication date |
---|---|
CN111430226B (zh) | 2023-04-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9379177B2 (en) | Deep trench capacitor | |
JPS63140581A (ja) | 縦型mosトランジスタ | |
US20120049262A1 (en) | A dram cell structure with extended trench and a manufacturing method thereof | |
TW451425B (en) | Manufacturing method for memory cell transistor | |
KR100460066B1 (ko) | 반도체소자의 제조방법 | |
KR100603588B1 (ko) | 낮은 콘택 저항을 갖는 반도체 소자 및 그 제조 방법 | |
US20020179996A1 (en) | Semiconductor device having a nitride barrier for preventing formation of structural defects | |
TWI235426B (en) | Method for manufacturing single-sided buried strap | |
CN111430226B (zh) | 一种多晶硅的沉积方法及其应用 | |
CN109119473B (zh) | 一种晶体管及其制作方法 | |
CN115662902A (zh) | 沟槽型场效应晶体管的制作方法 | |
EP4109533A1 (en) | Semiconductor structure and method for manufacturing semiconductor structure | |
CN108962742B (zh) | 半导体结构的制造方法 | |
CN114678325A (zh) | 接触孔中填充多晶硅的方法 | |
CN102543823B (zh) | 一种浅沟槽隔离制作方法 | |
JP2917894B2 (ja) | 半導体装置の製造方法 | |
RU2149481C1 (ru) | Способ создания структуры - кремний на изоляторе для сбис (варианты) | |
CN102437117B (zh) | 一种新的硅化物和金属前介质集成工艺及该形成的结构 | |
CN114628316A (zh) | 接触孔内填充磷掺杂多晶硅的方法 | |
TW493249B (en) | Manufacture method of dynamic random access memory cell capacitor | |
KR20000045274A (ko) | 캐패시터 제조 방법 | |
JP2000340677A (ja) | 半導体装置およびその製造方法 | |
CN117038447A (zh) | 一种dram单元结构中的蚀刻终止层及其制备方法 | |
JP2511852B2 (ja) | 半導体装置の製造方法 | |
CN114678267A (zh) | 一种向半导体栅极掺杂离子的方法及其应用 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |