CN111370484B - Proton irradiation resistant InP-based HEMT device based on composite channel and double doped layers and processing method thereof - Google Patents

Proton irradiation resistant InP-based HEMT device based on composite channel and double doped layers and processing method thereof Download PDF

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CN111370484B
CN111370484B CN202010242429.7A CN202010242429A CN111370484B CN 111370484 B CN111370484 B CN 111370484B CN 202010242429 A CN202010242429 A CN 202010242429A CN 111370484 B CN111370484 B CN 111370484B
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钟英辉
张佳佳
赵向前
靳雅楠
孟圣皓
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Zhengzhou University
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Abstract

The invention belongs to the technical field of proton irradiation resistant semiconductor devices, and particularly relates to a proton irradiation resistant InP-based HEMT device based on a composite channel and a double-doped layer and a processing method thereof. The InP-based HEMT channel adopts an InGaAs/InAs/AlInGaAs composite channel, the InAs material has low electron effective mass and high channel carrier mobility, a deep potential well is formed due to the narrow forbidden band width to enhance the channel carrier limiting capability, the AlInGaAs material has high Al displacement threshold energy to reduce the channel induced defect concentration to generate a weaker scattering effect, and the carrier mobility is compensated. And a double-doped structure above the channel is adopted, so that the concentration of the channel primary carriers is increased, and the compensation of the carrier removal effect caused by irradiation induced defects is realized. An InP thin layer is added between the InAlAs barrier layer and the InGaAs cap layer in the epitaxial structure and serves as an automatic cut-off layer for etching the cap layer of the gate trench process, and the precise control of the gate trench process is achieved.

Description

Proton irradiation resistant InP-based HEMT device based on composite channel and double doped layers and processing method thereof
Technical Field
The invention belongs to the technical field of proton irradiation resistant semiconductor devices, and particularly relates to a proton irradiation resistant InP-based HEMT device based on a composite channel and a double-doped layer and a processing method thereof.
Background
With the development of society and the progress of technology, the demand of national defense fields such as aerospace, satellite communication and the like and the demand of civilian fields such as smart cities, unmanned driving and the like on high-frequency millimeter wave integrated circuits are more and more urgent. The implementation of high performance, high frequency integrated circuits relies on mature nanoscale semiconductor device fabrication techniques. With the mainstream Si-based Complementary Metal Oxide Semiconductor (CMOS) reaching the 10 nm technical node, the preparation technology of a high-frequency semiconductor device with a new principle, a new material and a new structure becomes an important exploration direction of the 'post-molar age'. The III-V InP-based High Electron Mobility Transistor (HEMT) depends on an energy band engineering solution, has the characteristics of high frequency, low noise, low power consumption, high gain and the like, is known to be an excellent choice for realizing an ultra-high-speed low-noise integrated circuit, and has great application potential in the space fields of satellite radars, deep space exploration, astronomy and the like.
The application of aerospace equipment in space environment will face extremely complex irradiation environment: proton, electron, neutron, gamma ray, etc., with the highest proton fraction. An electronic system is used as a control core of space equipment, a microelectronic device is very sensitive to charged particle radiation and is easy to generate various damage effects such as ionization effect, displacement damage, single event and the like, great challenges are brought to the reliability of semiconductor devices and integrated circuits, control failure and even failure of the electronic system can be caused, and the space operation reliability and stability of the space equipment are greatly reduced. Therefore, the reinforced structure and the process of the proton irradiation resistant device become the key for ensuring the reliable and long-life operation of the electronic system of the aerospace equipment.
The InP-based HEMT proton irradiation induces vacancy defects through a displacement effect, the induced defects cause the concentration of channel carriers to be reduced through a carrier removal effect, and cause the mobility of the channel carriers to be reduced through a scattering effect, and finally, the alternating current and direct current characteristics of the device are degraded. The epitaxial structure parameters are adjusted through energy band engineering, the carrier concentration and the mobility are compensated, the limiting capacity of a channel on carriers is improved, the irradiation induced defect concentration is reduced, the degradation influence of irradiation on a device can be relieved certainly, and the method becomes an irradiation-resistant reinforcing alternative. Therefore, the invention provides the InP-based HEMT irradiation-resistant reinforcing structure and the processing method, wherein the double doping layers improve the channel carrier concentration, the compound channel increases the carrier mobility and the limiting capability of the channel to the carrier, and the induced defect concentration is reduced.
Disclosure of Invention
The invention aims to provide an anti-proton irradiation InP-based HEMT device based on a composite channel and a double-doped layer and a processing method thereof.
In order to achieve the purpose, the invention adopts the technical scheme that:
an extension structure of the InP-based HEMT is respectively an InP substrate, an InAlAs buffer layer, an InGaAs/InAs/AlInGaAs composite channel layer, an InAlAs lower isolating layer (an isolating layer 2, a spacer-2), an Si lower doped layer (a surface doped layer 2, si-Doping-2), an InAlAs upper isolating layer (an isolating layer 1, a spacer-1), an Si upper doped layer (a surface doped layer 1, si-Doping-1), an InAlAs Schottky barrier layer, an InP corrosion stop layer and an InGaAs cap layer from bottom to top; the InAlAs buffer layer is provided with a source region isolation table board, two sides of the high-doped InGaAs cap layer are respectively provided with source electrode ohmic contact metal and drain electrode ohmic contact metal, an InP corrosion cut-off layer between the source electrode ohmic contact metal and the drain electrode ohmic contact metal or an InAlAs Schottky barrier layer is provided with T-shaped gate Schottky contact metal, source electrode wiring metal is arranged on the InAlAs buffer layer under the source electrode ohmic contact metal and the active region isolation table board, drain electrode wiring metal is arranged on the drain electrode ohmic contact metal and the InAlAs buffer layer under the active region isolation table board, and gate electrode wiring metal is arranged on the InAlAs buffer layer under the active region isolation table board.
Furthermore, in the device, the thickness of the InP substrate is 100 μm, the thickness of the InAlAs buffer layer is 500nm, the thickness of the InGaAs/InAs/AlInGaAs composite channel layer is 15 nm, the thickness of the InAlAs lower isolation layer is 3 nm, and the doping density of the doping layer below Si is 5 multiplied by 10 12 cm -2 The thickness of InAlAs upper isolation layer is 2 nm, and the doping density of Si upper doped layer is 2 × 10 11 cm -2 The thickness of the InAlAs Schottky barrier layer is 10 nm, the thickness of the InP corrosion stop layer is 5 nm, the thickness of the InGaAs cap layer is 15 nm, and the doping concentration is 3 multiplied by 10 19 cm -2
Further, the InGaAs/InAs/AlInGaAs composite channel layer,comprises an InGaAs layer with the thickness of 3 nm, an InAs layer with the thickness of 2 nm and an AlInGaAs layer with the thickness of 10 nm; in the InGaAs/InAs/AlInGaAs composite channel, the proportion of each element is In 0.53 Ga 0.47 As/InAs/In 0.53 (Al 0.7 Ga 0.3 ) 0 . 47 As; the proportion of each element of the InAlAs barrier layer and the buffer layer is In 0.52 Al 0.48 As; the proportion of each element of the InGaAs cap layer is In 0.53 Ga 0.47 As。
The processing method of the proton irradiation resistant InP-based HEMT device based on the composite channel and the double doped layers comprises the following steps:
A. preparing an InP-based InAlAs/InGaAs HEMT epitaxial wafer, cleaning the epitaxial wafer until the surface of the epitaxial wafer under a microscope is free from contamination, and drying by adopting nitrogen; the epitaxial wafer sequentially comprises an InP substrate, an InAlAs buffer layer, an InGaAs/InAs/AlInGaAs composite channel layer, an InAlAs lower isolating layer, a Si lower doped layer, an InAlAs upper isolating layer, a Si upper doped layer, an InAlAs Schottky barrier layer, an InP corrosion stop layer and an InGaAs cap layer from bottom to top; all epitaxial materials in the epitaxial wafer are grown by a molecular beam epitaxy method;
B. forming an active region isolation table board on the epitaxial wafer through positive photoetching, corroding part of the InAlAs buffer layer, corroding the InGaAs cap layer by using mixed corrosive liquid of phosphoric acid and hydrogen peroxide, corroding the InP corrosion stop layer by using mixed corrosive liquid of phosphoric acid and hydrochloric acid, and corroding the InAlAs Schottky barrier layer, the InGaAs/InAs/AlInGaAs composite channel layer and the InAlAs buffer layer by using mixed corrosive liquid of phosphoric acid and hydrogen peroxide;
C. defining a metal area of ohmic contact of a source electrode and a metal area of ohmic contact of a drain electrode on two sides of a highly doped InGaAs cap layer of an active area isolated from a mesa by photoetching, depositing a metal film Ti/Pt/Au on the metal area of ohmic contact of the source electrode and the metal area of ohmic contact of the drain electrode by adopting electron beam evaporation equipment or sputtering furnace equipment, and forming ohmic contact of the source electrode and the drain electrode on the highly doped InGaAs cap layer by the operations;
D. defining a source wiring metal region on the InAlAs buffer layer under the source ohmic contact and active region isolation platform surface, defining a drain wiring metal region on the InAlAs buffer layer under the drain ohmic contact and active region isolation platform surface, defining a grid wiring metal region on the InAlAs buffer layer under the active region isolation platform surface, depositing a metal film Ti/Au on the wiring metal region by adopting electron beam evaporation equipment or sputtering furnace equipment, and forming wiring metal by the above operations;
E. forming a T-shaped gate between the metal area contacted with the source electrode and the metal area contacted with the drain electrode, wherein the three steps of forming T-shaped gate morphology by electron beam lithography, preparing a gate groove and preparing gate metal are included:
firstly, forming a T-shaped gate morphology on a highly doped InGaAs cap layer between a metal area contacted with a source electrode and a metal area contacted with a drain electrode by adopting PMMA/Al/UVIII three-layer electron beam glue and adopting a method of electron beam Exposure (EBL) and development for two times;
secondly, preparing a gate groove;
and finally, depositing a Ti/Pt/Au gate metal film in the gate groove by adopting electron beam evaporation or sputtering furnace equipment, and connecting the Ti/Pt/Au gate metal film with gate wiring metal to obtain the InP-based HEMT.
Specifically, the volume ratio of the mixed corrosive liquid of phosphoric acid and hydrogen peroxide in the step B is H 3 PO 4 :H 2 O 2 :H 2 O = 3; the volume ratio of the phosphoric acid and the hydrochloric acid mixed corrosive liquid is HCl to H 3 PO 4 3-5; and over-etching the InAlAs buffer layer by 15-30 nm.
Specifically, the thickness of the deposited metal film in the step C is as follows: 10 to 20nm of Ti, 10 to 20nm of Pt and 300 to 500nm of Au.
Specifically, the thickness of the deposited metal film in the step D is as follows: ti of 10 to 20nm and Au of 300 to 500nm.
Specifically, the process for forming the T-shaped gate shape in the step E comprises the following steps of firstly forming a PMMA/Al/UVIII three-layer electron beam glue layer on a wafer, wherein the thicknesses of all layers are PMMA:80 to 200 nm, al: 7 to 15 nm, UVIII:500 to 700 nm; the dosage of the UVIII electron beam adhesive layer in electron beam exposure is as follows: 100 uC; CD26 development time is 60 to 90 sec; the dosage of PMMA electron beam glue layer exposed by electron beams is as follows: 800 to 1200 uC; and developing the mixture for 2.5 to 3.5 min by using o-xylene.
Specifically, the preparation of the gate trench in the step E includes two ways:
Figure DEST_PATH_IMAGE002
corroding the InGaAs cap layer by using a phosphoric acid and hydrogen peroxide mixed corrosive liquid, and etching the InP corrosion stop layer at a low speed by using Ar plasma through inductively coupled plasma equipment, wherein the thickness of the InP corrosion stop layer is kept to be 1-2 nm;
Figure DEST_PATH_IMAGE004
corroding the InGaAs cap layer by using phosphoric acid and hydrogen peroxide mixed corrosive liquid, carrying out low-speed etching on the InP corrosion stop layer by using Ar plasma through Inductively Coupled Plasma (ICP) equipment, not reserving the InP corrosion stop layer, carrying out 1-3 times of digital corrosion on the InAlAs Schottky barrier layer material, wherein the corrosion thickness is approximately as follows: 2 to 4nm.
Specifically, the volume ratio of the mixed corrosive liquid of phosphoric acid and hydrogen peroxide in the step E is H 3 PO 4 :H 2 O 2 :H 2 O = 3; the etching thickness is 3 to 4nm, the flow rate of Ar plasma is 15 to 30 sccm, and the radio frequency power is 5 to 20 mW; the thickness of the gate metal film is as follows: 10 to 20nm of Ti, 10 to 20nm of Pt and 300 to 500nm of Au.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, the InP-based HEMT channel adopts an InGaAs/InAs/AlInGaAs composite channel, the channel carrier mobility and the channel carrier limiting capability are increased through a narrow-band gap InAs material, the AlInGaAs material Al displacement threshold energy is higher, the channel induced defect concentration is reduced, the weaker scattering effect is generated, and the carrier mobility is compensated. Meanwhile, the lattice matching of the channel InGaAs and AlInGaAs materials with the isolation layer material and the buffer layer material avoids performance reduction caused by lattice mismatch of the InAs materials with the isolation layer material and the buffer layer material.
The InP-based HEMT adopts a double-doped structure above the channel, increases the concentration of the channel primary carrier, and realizes the compensation of the carrier removal effect caused by irradiation induced defects. Meanwhile, the double doped layer is positioned above the channel, so that the control is easier through the gate voltage, and the carrier concentration and transconductance of the channel of the device are increased.
In the InP-based HEMT epitaxial structure, the InP thin layer is added between the InAlAs barrier layer and the InGaAs cap layer to serve as an automatic stop layer for etching the cap layer of the gate trench process, so that the precise control of the gate trench process is realized. And performing low-power etching on the InP corrosion stop layer by adopting Ar plasma through Inductively Coupled Plasma (ICP) equipment, and reserving a thin layer of InP to prevent InAlAs barrier layer materials from being exposed and oxidized in air. Meanwhile, the low-power dry etching can realize the accurate control of the transverse width and the longitudinal depth of the gate groove. In addition, an InP corrosion cut-off layer below the gate metal can be etched at low power in the gate groove process, then the thickness of the InAlAs barrier layer is accurately controlled through digital corrosion, the gate groove distance is reduced, and the gate control capacity of the device is improved.
Drawings
Fig. 1 is a schematic cross-sectional structure diagram of the proton irradiation resistant InP-based HEMT device based on a composite channel and a double doped layer in example 1;
fig. 2 is a flowchart of a method for fabricating the proton irradiation resistant InP-based HEMT device based on a composite channel and a double doped layer as described in example 1;
FIG. 3 is a flow chart of the preparation of a T-shaped grating based on PMMA/Al/UVIII step exposure development in step E of example 1;
FIG. 4 is a schematic structural view of a conventional single-channel single-doped InP-based HEMT device;
FIG. 5 is an irradiation resistance characteristic diagram of a conventional single-channel single-doped layer InP-based HEMT under irradiation of different proton doses; (a) Output characteristic (I) DS -V DS ) (b) transfer characteristics (I) DS -V GS );
FIG. 6 is an anti-irradiation characteristic diagram of a composite channel double-doped InP-based HEMT under irradiation of different proton doses; (a) Output characteristic (I) DS -V DS ) (b) transfer characteristics (I) DS -V GS );
FIG. 7 is a comparison of the degradation of characteristics of conventional single-channel single-doped and composite-channel double-doped InP-based HEMTs; (a) Normalized saturation current degradation, and (b) normalized transfer characteristic degradation.
Detailed Description
In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention is described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
Example 1
A cross-sectional structure of an anti-proton irradiation InP-based HEMT device based on a composite Channel and a double-doped layer is shown in figure 1, the epitaxial structure of the InP-based HEMT is an InP Substrate (InP Substrate) with the thickness of 100 mu m, an InAlAs Buffer layer (InAlAs Buffer) with the thickness of 500nm, an InGaAs/InAs/AlInGaAs composite Channel layer (InGaAs/InAs/AlInGaAs Channel) with the thickness of 15 nm, wherein the InGaAs layer with the thickness of 3 nm, the InAs layer with the thickness of 2 nm and the AlInGaAs layer with the thickness of 10 nm, an InAlInGaAs lower isolation layer (InAlSpacer-2) with the thickness of 3 nm, and the doping density is 5 multiplied by 10 12 cm -2 A doped layer (Si-Doping-2) below Si, an InAlAs upper isolating layer (InAlAs Spacer-1) with the thickness of 2 nm, and the Doping density of 2 multiplied by 10 11 cm -2 Doping layer (Si-Doping-1) on Si, inAlAs Schottky Barrier layer (InAlAs Barrier) with thickness of 10 nm, inP corrosion cut-off layer with thickness of 15 nm and Doping concentration of 3 multiplied by 10 19 cm -2 InGaAs cap layer of (a). All InAlAs and InGaAs layers are in lattice matching with the InP substrate, all epitaxial materials grow through a Molecular Beam Epitaxy (MBE) method, a source region isolation table board is arranged on the InAlAs buffer layer, source ohmic contact metal and drain ohmic contact metal are arranged on two sides of the high-doping InGaAs cap layer respectively, T-type grid Schottky contact metal is arranged on an InP corrosion stop layer or an InAlAs Schottky barrier layer between the source ohmic contact metal and the drain ohmic contact metal, source wiring metal is arranged on the InAlAs buffer layer under the source ohmic contact metal and the active region isolation table board, drain wiring metal is arranged on the InAlAs buffer layer under the drain ohmic contact metal and the active region isolation table board, and grid wiring metal is arranged on the InAlAs buffer layer under the active region isolation table board. In the InGaAs/InAs/AlInGaAs composite channel, the proportion of each element is In 0.53 Ga 0.47 As/InAs/In 0.53 (Al 0.7 Ga 0.3 )0. 47 As. The proportion of each element of the InAlAs barrier layer and the buffer layer is In 0.52 Al 0.48 As. The proportion of each element of the InGaAs cap layer is In 0.53 Ga 0.47 As。
A flow chart of the processing method of the proton irradiation resistant InP-based HEMT device based on the composite channel and the double doped layer is shown in fig. 2, and the specific steps are as follows:
A. preparing an InP-based InAlAs/InGaAs HEMT epitaxial wafer, sequentially cleaning the epitaxial wafer by using acetone, ethanol and deionized water until the surface of the epitaxial wafer under a microscope is free from contamination, and drying by using nitrogen; as shown In fig. 2, the epitaxial wafer of the epitaxial wafer comprises, from bottom to top, an InP Substrate (InP Substrate), an InAlAs Buffer layer (InAlAs Buffer), in 0.53 Ga 0.47 As/InAs/In 0.53 (Al 0.7 Ga 0.3 ) 0 . 47 The InAs composite Channel layer (InGaAs/InAs/AlInGaAs Channel), an InAlAs lower isolating layer (InAlAs Spacer-2), a Si lower doped layer (Si-Doping-2), an InAlAs upper isolating layer (InAlAs Spacer-1), a Si upper doped layer (Si-Doping-1), an InAlAs Schottky Barrier layer (InAlAs Barrier), an InP corrosion stop layer and an InGaAs cap layer, wherein all InAlAs and InGaAs layers are matched with an InP substrate in a lattice mode; all epitaxial materials in the epitaxial wafer are grown by a Molecular Beam Epitaxy (MBE) method;
B. forming a convex active region isolation mesa on an epitaxial wafer by positive photoetching, wherein in order to ensure that an InGaAs channel layer under the active region isolation mesa is completely corroded, part of an InAlAs buffer layer is over-corroded, and a phosphoric acid and hydrogen peroxide mixed corrosive liquid (volume ratio H) is used in the processing process 3 PO 4 :H 2 O 2 :H 2 O =3 3 PO 4 =1 3 PO 4 :H 2 O 2 :H 2 O =3Corroding the nAlAs buffer layer; the InAlAs buffer layer is over-etched by about 20nm, so that good electrical isolation characteristics are ensured;
C. defining a metal area of ohmic contact of a source electrode and a metal area of ohmic contact of a drain electrode on two sides of a high-doping InGaAs cap layer of an active area isolation mesa by photoetching, depositing a metal film Ti/Pt/Au (the thickness of the deposited metal film is 10 to 20nm, 10 to 20nm and 300 to 500nm) on the metal area of ohmic contact of the source electrode and the metal area of ohmic contact of the drain electrode by adopting electron beam evaporation equipment or sputtering furnace equipment, and forming ohmic contact of the source electrode and the drain electrode on the high-doping InGaAs cap layer by the operations;
D. defining a source wiring metal area on the InAlAs buffer layer under the source ohmic contact and the active region isolation platform by photoetching, defining a drain wiring metal area on the InAlAs buffer layer under the drain ohmic contact and the active region isolation platform, defining a grid wiring metal area on the InAlAs buffer layer under the active region isolation platform (as shown in figure 1, the purple part is wiring metal), depositing a metal film Ti/Au (Ti: 10 to 20nm, au:300 to 500nm) on the wiring metal area by adopting an electron beam evaporation device or a sputtering furnace device, and forming wiring metal by the operations;
E. forming a T-shaped gate between a metal area contacted with a source electrode and a metal area contacted with a drain electrode, wherein the three steps of electron beam lithography T-shaped gate morphology, gate groove preparation and gate metal preparation are included:
firstly, forming a T-shaped grid shape on a highly doped InGaAs cap layer between a metal area contacted with a source electrode and a metal area contacted with a drain electrode by adopting a PMMA/Al/UVIII three-layer electron beam glue and through a method of electron beam Exposure (EBL) and development twice, wherein the T-shaped grid shape forming process is shown in figure 3, firstly forming a PMMA/Al/UVIII three-layer electron beam glue layer on a wafer, and the thicknesses of all layers are respectively PMMA:80 to 200 nm, al: 7 to 15 nm, UVIII:500 to 700 nm; dose of electron beam exposure UVIII electron beam glue layer: 100 The uC and the CD26 develop for 60 to 90 sec, the exposure dose threshold of the PMMA electron beam glue layer is large, and the PMMA electron beam glue layer cannot be influenced during exposure with small dose; dosage of electron beam exposure PMMA electron beam glue layer: developing with o-xylene at 800-1200 uC for 2.5-3.5 min, wherein UVIII is developed, and forward scattering during PMMA exposure is reduced;
secondly, preparing a gate groove specifically comprises two modes:
Figure 473126DEST_PATH_IMAGE002
by mixing phosphoric acid and hydrogen peroxide as corrosive liquid (volume ratio H) 3 PO 4 :H 2 O 2 :H 2 O = 3;
Figure 921425DEST_PATH_IMAGE004
by mixing phosphoric acid and hydrogen peroxide as corrosive liquid (volume ratio H) 3 PO 4 :H 2 O 2 :H 2 O =3: 2 to 4nm, and the single digital corrosion step comprises the following steps: oxidizing 30s in hydrogen peroxide, and corroding 30s in phosphoric acid and aqueous solution with the volume ratio equal to 1; the source-drain spacing can be reduced by re-etching the InAlAs barrier layer, and the transconductance and the frequency characteristic of the device are improved;
and finally, depositing a Ti/Pt/Au gate metal film (Ti: 10 to 20nm, pt:10 to 20nm and Au:300 to 500nm) in the gate groove by using electron beam evaporation or sputtering furnace equipment, and connecting the film with gate wiring metal to obtain the InP-based HEMT.
The processing method adopts the InGaAs/InAs/AlInGaAs composite channel layer for the channel of the InP-based HEMT device, the carrier mobility of the channel and the limiting capacity of the channel on the carrier are increased through the narrow-band gap InAs material, the Al displacement threshold energy in the AlInGaAs material is high, the concentration of channel induced defects is reduced, a weaker scattering effect is generated, and the carrier mobility is compensated. Meanwhile, the lattice matching of the channel InGaAs and AlInGaAs materials with the isolation layer material and the buffer layer material avoids performance reduction caused by lattice mismatch of the InAs materials with the isolation layer material and the buffer layer material.
The InP-based HEMT device adopts a double-doped structure above the channel, increases the concentration of the channel primary carrier, and realizes the compensation of the carrier removal effect caused by irradiation induced defects. Meanwhile, the double doped layer is positioned above the channel and is easier to control through gate voltage, and the carrier concentration and transconductance of the channel of the device are increased.
In the epitaxial structure of the InP-based HEMT device, an InP thin layer is added between the InAlAs barrier layer and the InGaAs cap layer to serve as an automatic cut-off layer for etching the cap layer of the gate trench process, so that the accurate control of the gate trench process is realized. The gate slot process flow is as follows: etching the InGaAs cap layer by using a mixed etching solution of phosphoric acid and hydrogen peroxide; and performing low-power etching on the InP corrosion stop layer by adopting Ar plasma through Inductively Coupled Plasma (ICP) equipment, and reserving a thin layer of InP to prevent InAlAs barrier layer materials from being exposed and oxidized in air. Meanwhile, the low-power dry etching can realize the accurate control of the transverse width and the longitudinal depth of the gate groove. In addition, in the gate trench process, after an InP corrosion stop layer below gate metal is etched at low power, 1-3 times of digital corrosion is carried out through an InAlAs barrier layer, wherein the corrosion thickness is approximately as follows: 2 to 4nm, and the single digital corrosion step comprises the following steps: oxidizing in hydrogen peroxide for 30s, and corroding in phosphoric acid and aqueous solution with the volume ratio equal to 1; the source-drain spacing can be reduced by re-etching the InAlAs barrier layer, and the transconductance and the frequency characteristic of the device are improved.
For the prepared device, in step E, when the gate trench is prepared, the InP corrosion cut-off layer is not retained, and for the obtained device structure, a hydrodynamic carrier transport model and a density gradient quantum effect model are used to respectively perform a conventional single-channel single-doped structure (the structure is shown in fig. 4, wherein the epitaxial structure of the InP-based HEMT is an InP substrate (InP Subs) with a thickness of 100 μm from bottom to toptrate), an InAlAs Buffer layer (InAlAs Buffer) with a thickness of 500nm, an InGaAs Channel layer (InGaAs Channel) with a thickness of 15 nm, an InAlAs spacer layer (InAlAs spacer) with a thickness of 5 nm, and a doping density of 5 × 10 12 cm -2 The doped layer of Si face, inAlAs Schottky Barrier layer (InAlAs Barrier) with thickness of 10 nm, inP corrosion cut-off layer with thickness of 5 nm and doping concentration of 3 x 10 19 cm -2 InGaAs cap layer) and the proton irradiation resistance of the double-doped composite channel structure, and the proton irradiation induced vacancy defect is introduced into the carrier transport model for self-consistent calculation, with the results shown in fig. 5, 6 and 7. Considering that the irradiation induced defect of the heterostructure can cause degradation influence on the channel carrier concentration and mobility through carrier removal effect and scattering effect. Taking the proton irradiation energy which causes the heterojunction region of the device to induce the most vacancy defects as 75 keV, and the irradiation dose is 2.5 multiplied by 10 11 cm -2 ,5×10 11 cm -2 , 1×10 12 cm -2 , 2×10 12 cm -2 And 4X 10 12 cm -2
As can be seen from FIGS. 5 and 6, the maximum saturation leakage current (I) of the single-channel single-doped InP-based HEMT before irradiation D,sat ) And maximum transconductance (g) m,max ) 570 mA/mm and 970 mS/mm respectively, and the maximum saturation leakage current and the maximum transconductance of the double-doped composite channel HEMT are 867 mA/mm and 1822 mS/mm respectively. With the increase of proton dose, the maximum saturation leakage current and the maximum transconductance of the single-channel single-doped and composite-channel double-doped InP-based HEMTs both show degradation trends, and it can be clearly seen from fig. 7 that the degradation degree of the composite-channel double-doped InP-based HEMTs is lower than that of the single-channel single-doped structure. At maximum dose 4X 10 12 cm -2 In the case of the single-channel single-doped HEMT, the saturation leakage current and the maximum transconductance are respectively kept at 9.3% and 25% of those of the non-irradiated HEMT, while the two parameters of the composite channel double-doped HEMT can still be kept at 61% and 56% of those of the non-irradiated HEMT. Therefore, the composite channel double-doped HEMT has better radiation resistance and is more suitable for being applied to a space radiation environment.
Although the present invention has been illustrated and described with reference to specific examples, it should be understood that the present invention is not limited to the details of the foregoing embodiments, and that various changes, modifications, substitutions, combinations and omissions may be made without departing from the spirit and scope of the invention.

Claims (10)

1. The proton irradiation resistant InP-based HEMT device is characterized in that an epitaxial structure of the InP-based HEMT comprises an InP substrate, an InAlAs buffer layer, an AlInGaAs/InAs/InGaAs composite channel layer, an InAlAs lower isolating layer, an Si lower doping layer, an InAlAs upper isolating layer, an Si upper doping layer, an InAlAs Schottky barrier layer, an InP corrosion stop layer and an InGaAs cap layer from bottom to top respectively; the InAlAs buffer layer is provided with a source region isolation table board, two sides of the InGaAs cap layer are respectively provided with source electrode ohmic contact metal and drain electrode ohmic contact metal, an InP corrosion cut-off layer between the source electrode ohmic contact metal and the drain electrode ohmic contact metal or an InAlAs Schottky barrier layer is provided with T-shaped gate Schottky contact metal, source electrode wiring metal is arranged on the InAlAs buffer layer below the source electrode ohmic contact metal and the active region isolation table board, drain electrode wiring metal is arranged on the drain electrode ohmic contact metal and the InAlAs buffer layer below the active region isolation table board, and gate wiring metal is arranged on the InAlAs buffer layer below the active region isolation table board.
2. The device of claim 1, wherein the InP substrate has a thickness of 100 μm, the InAlAs buffer layer has a thickness of 500nm, the InGaAs/InAs/AlInGaAs composite channel layer has a thickness of 15 nm, the InAlAs lower spacer layer has a thickness of 3 nm, the doping density of the Si lower doped layer is 5 x 10 12 cm -2 The thickness of the InAlAs upper isolation layer is 2 nm, the doping density of the Si upper doping layer is 2 multiplied by 10 11 cm -2 The thickness of the InAlAs Schottky barrier layer is 10 nm, the thickness of the InP corrosion stop layer is 5 nm, the thickness of the InGaAs cap layer is 15 nm, and the doping concentration is 3 multiplied by 10 19 cm -3
3. The device of claim 1, wherein the InGaAs/InAs/AlInGaAs composite channel layer comprises a 3 nm thick InGaAs layer, a 2 nm thick InAs layer, and a 10 nm thick AlInGaAs layer; the proportion of each element In the InGaAs/InAs/AlInGaAs composite channel layer is In 0.53 Ga 0.47 As/InAs/In 0.53 (Al 0.7 Ga 0.3 ) 0 . 47 As; the proportion of each element of the InAlAs barrier layer and the buffer layer is In 0.52 Al 0.48 As; the proportion of each element of the InGaAs cap layer is In 0.53 Ga 0.47 As。
4. A method for fabricating an anti-proton irradiation InP based HEMT device according to any one of claims 1-3 based on composite channel and double doped layer comprising the steps of:
A. preparing an InP-based InAlAs/InGaAs HEMT epitaxial wafer, cleaning the epitaxial wafer until the surface of the epitaxial wafer under a microscope is free from contamination, and drying by adopting nitrogen; the epitaxial wafer sequentially comprises an InP substrate, an InAlAs buffer layer, an InGaAs/InAs/AlInGaAs composite channel layer, an InAlAs lower isolation layer, a Si lower doping layer, an InAlAs upper isolation layer, a Si upper doping layer, an InAlAs Schottky barrier layer, an InP corrosion stop layer and an InGaAs cap layer from bottom to top;
B. forming an active region isolation table-board on the epitaxial wafer through positive photoetching, and over-etching part of the InAlAs buffer layer;
corroding the InGaAs cap layer by using a mixed corrosive liquid of phosphoric acid and hydrogen peroxide, corroding the InP corrosion stop layer by using a mixed corrosive liquid of phosphoric acid and hydrochloric acid, and corroding the InAlAs Schottky barrier layer, the InGaAs/InAs/AlInGaAs composite channel layer and the InAlAs buffer layer by using a mixed corrosive liquid of phosphoric acid and hydrogen peroxide;
C. defining a metal area of ohmic contact of a source electrode and a metal area of ohmic contact of a drain electrode at two sides of a high-doping InGaAs cap layer of an active area isolated from a mesa by photoetching, depositing a metal film Ti/Pt/Au on the metal area of ohmic contact of the source electrode and the metal area of ohmic contact of the drain electrode by adopting electron beam evaporation equipment or sputtering furnace equipment, and forming ohmic contact of the source electrode and the drain electrode on the high-doping InGaAs cap layer by the operation;
D. defining a source wiring metal region on the InAlAs buffer layer under the source ohmic contact and active region isolation platform surface, defining a drain wiring metal region on the InAlAs buffer layer under the drain ohmic contact and active region isolation platform surface, defining a grid wiring metal region on the InAlAs buffer layer under the active region isolation platform surface, depositing a metal film Ti/Au on the wiring metal region by adopting electron beam evaporation equipment or sputtering furnace equipment, and forming wiring metal through the above operations;
E. forming a T-shaped gate between a metal area of ohmic contact of a source electrode and a metal area of ohmic contact of a drain electrode, wherein the three steps of forming T-shaped gate morphology by electron beam lithography, preparing a gate groove and preparing gate metal are included;
firstly, forming a T-shaped gate morphology on a highly doped InGaAs cap layer between a metal area contacted with a source electrode and a metal area contacted with a drain electrode by adopting PMMA/Al/UVIII three-layer electron beam glue and adopting a method of electron beam Exposure (EBL) and development for two times;
secondly, preparing a gate groove;
and finally, depositing a Ti/Pt/Au gate metal film in the gate groove by adopting electron beam evaporation or sputtering furnace equipment, and connecting the Ti/Pt/Au gate metal film with gate wiring metal to obtain the InP-based HEMT.
5. The processing method according to claim 4, wherein the volume ratio of the mixed corrosive liquid of phosphoric acid and hydrogen peroxide in the step B is H 3 PO 4 :H 2 O 2 :H 2 O = 3; the volume ratio of the phosphoric acid and the hydrochloric acid mixed corrosive liquid is HCl to H 3 PO 4 3-5; and over-etching the InAlAs buffer layer by 15-30 nm.
6. The process of claim 4 wherein the thickness of the deposited metal film in step C is: 10 to 20nm of Ti, 10 to 20nm of Pt and 300 to 500nm of Au.
7. The process of claim 4 wherein the thickness of the deposited metal film in step D is: ti of 10 to 20nm and Au of 300 to 500nm.
8. The processing method according to claim 4, wherein the T-shaped grid feature forming process in step E is to form a PMMA/Al/UVIII three-layer electron beam glue layer on the wafer, and the thicknesses of the layers are PMMA:80 to 200 nm, al: 7 to 15 nm, UVIII:500 to 700 nm; the dosage of the UVIII electron beam adhesive layer in electron beam exposure is as follows: 100 uC; CD26 development is 60 to 90 sec; the dosage of PMMA electron beam glue layer exposed by electron beams is as follows: 800 to 1200 uC; and developing the solution for 2.5 to 3.5 min by using o-xylene.
9. The process of claim 4, wherein the preparation of the gate trench in step E comprises two ways:
Figure DEST_PATH_IMAGE001
corroding the InGaAs cap layer by using a phosphoric acid and hydrogen peroxide mixed corrosive liquid, and etching the InP corrosion stop layer at a low speed by using Ar plasma through inductively coupled plasma equipment, wherein the thickness of the InP corrosion stop layer is kept to be 1-2 nm;
Figure 95333DEST_PATH_IMAGE002
corrode InGaAs cap layer through phosphoric acid and hydrogen peroxide mixed etchant, adopt Ar plasma to carry out low-speed sculpture to InP corrosion stop layer through inductively coupled plasma equipment, do not keep InP corrosion stop layer, carry out 1, 2 or 3 times digital corrosion to InAlAs Schottky barrier layer material, corrode the thickness and be: 2 to 4nm.
10. The processing method according to claim 4, wherein the volume ratio of the mixed corrosive liquid of phosphoric acid and hydrogen peroxide in the step E is H 3 PO 4 :H 2 O 2 :H 2 O = 3; the etching thickness is 3 to 4nm, the flow rate of Ar plasma is 15 to 30 sccm, and the radio frequency power is 5 to 20 mW; the thickness of the gate metal film is as follows: 10 to 20nm of Ti, 10 to 20nm of Pt and 300 to 500n of Aum。
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