JP2002184787A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having an InGaAs non-alloy ohmic contact layer formed on a GaAs substrate, which can prevent non-uniform device characteristics caused by deterioration of surface morphology resulting from a difference in lattice constant between the non-alloy ohmic contact layer and a layer located thereunder. SOLUTION: An interface between planarized layer 15 and a layer 6 adjacent thereto is flattened to an atomic layer level by forming the layer 15 made of e.g. InGaP that is different in etching characteristic from InGaAs under a non-alloy ohmic contact layer 8 of InGaAs, recess etching is carried out by selectively etching the contact layer 8 utilizing the difference in etching characteristic, the etching is stopped by the planarized layer 15, and thereafter the planarized layer 15 is etched to improve the surface morphology of a recess 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a non-alloy ohmic contact structure suitably used in a semiconductor device suitable for high frequency and high efficiency operation. And a method of manufacturing the same.

[0002]

2. Description of the Related Art HFET (heterojunction field effect transistor) and HBT (heterojunction bipolar transistor)
Semiconductor devices using a heterojunction such as those described above are suitable for high-speed and high-efficiency operation, and are therefore used in various fields such as satellite broadcasting and mobile phones.

In order to bring out the excellent characteristics of HFETs and HBTs, it is important to reduce ohmic contact resistance. For that purpose, a non-alloy ohmic contact structure using an InGaAs contact layer having a large InAs molar ratio is promising. That is, In
As mole ratio of 0.5 or more and high electron density of In
It is known that when Si is added to GaAs at a high concentration, the Fermi level enters the conduction band and a good ohmic contact with an electrode made of a metal such as Ti / Pt / Au can be formed.

In the above case, InA in InGaAs is used.
The higher the s mole ratio, the lower the Fermi level is in the conduction band, and the lower the contact resistance, which is preferable as an ohmic contact. On the other hand, the higher the InAs mole ratio, the larger the difference in lattice constant from GaAs. Therefore, InG used for non-alloy ohmic contact and having an InAs molar ratio of 0.5 or more is used.
In aAs, the difference between the lattice constant of the GaAs substrate and that of the GaAs substrate becomes large, and when the layers are stacked to a thickness greater than the critical thickness, misfit dislocations occur and the surface morphology deteriorates.

A conventional method of manufacturing an HFET will be described below with reference to FIGS.

First, referring to FIG. 8, semi-insulating GaAs
On a substrate 1, an undoped GaAs buffer layer 2, an undoped InGaAs channel layer 3, an n-type Al _0.25 Ga _0.75
As carrier supply layer 4, undoped Al _0.25 Ga _0.75 A
s Schottky barrier layer 5, n-type GaAs cap layer 6, n
-Type In _x Ga _{1 -x} As composition gradient layer 7 (x = 0 → 0.
5) and the n-type In _0.5 Ga _0.5 As ohmic contact layer 8 are sequentially grown epitaxially by MBE, MOCVD or the like.

The above-mentioned InGaAs channel layer 3 is formed so as to have a thickness less than a critical thickness at which misfit dislocation does not occur.
The composition and film thickness are selected (for example, InAs molar ratio = 0.2, film thickness = 10 nm). Therefore, in the semiconductor layer from the buffer layer 2 to the ohmic contact layer 8, up to the interface between the cap layer 6 and the composition gradient layer 7 is lattice-matched with the GaAs substrate 1, so that no dislocation occurs. Therefore, from the GaAs substrate 1 to the composition gradient layer 7
The interface between the layers in the laminated structure up to is flat.

On the other hand, since the composition gradient layer 7 and the ohmic contact 8 need to sufficiently reduce the contact resistance, it is necessary to increase the InAs molar ratio and make the film thickness more than the critical film thickness as described above. Yes, lattice matching with the GaAs substrate 1 is lost, and as a result, dislocations occur, and the surface morphology deteriorates as shown in FIG.

[0009] Next, as shown in FIG.
The elements are removed until they reach the buffer layer 2, and the respective elements are electrically separated from each other.

Next, as shown in FIG.
An ohmic electrode 10 is formed on the contact layer 8.

Next, as shown in FIG. 11, a photoresist 11 having a desired pattern is formed, and in this state, recess etching is performed to a predetermined depth so as to obtain a desired threshold voltage. , A recess 12 is formed. The recess etching includes the following two methods.

The first method uses an etching solution (for example, a mixed solution of phosphoric acid, a hydrogen peroxide solution, and water) that does not greatly change the etching characteristics of each of InGaAs, GaAs, and AlGaAs.
This is a method in which monitoring of the current value between 0 and etching are performed alternately, and etching is performed until a predetermined current value is obtained.

The second method is to use an etching solution (for example, a mixture of citric acid, ammonia water, hydrogen peroxide solution, and water) having a sufficiently low etching rate on AlGaAs to form a film on the surface of the AlGaAs Schottky barrier layer 5. This is a method of stopping etching. In this method, it is necessary to control the film thickness of the AlGaAs Schottky barrier layer 5 in the epitaxial growth stage so that a desired threshold value is obtained when the etching is stopped.

After the completion of the recess etching step, the photoresist 11 is removed.

Next, as shown in FIG. 12, a gate electrode 13 is formed in the recess 12.

Thus, the main part of the HFET is completed.

[0017]

As described above, in the composition gradient layer 7 and the ohmic contact layer 8, as a result of taking measures to sufficiently reduce the contact resistance, as shown in FIG. In addition, the surface morphology has deteriorated.

In such a state, when the recess etching by the first method described above is performed,
Since the process proceeds while taking on relatively large irregularities on the surface of the ohmic contact layer 8, that is, the bad surface morphology, this is reflected in the etching of the AlGaAs Schottky barrier layer 5 as shown in FIG. This degrades the surface morphology at the bottom of the recess 12 in the AlGaAs Schottky barrier layer 5.

In addition, the surface morphology at the bottom of the recess 12 tends to be further deteriorated than the surface morphology of the ohmic contact layer 8 due to variations in etching.

As a result, the distance between the bottom surface of the gate electrode 13 formed on the surface of the AlGaAs Schottky barrier layer 5 and the channel layer 3 also varies. In this case, a problem is encountered that the obtained device characteristics vary and, as a result, the yield is deteriorated.

In the above description, the HFET has been described. However, even in the case of the HBT, similar to the case of the HFET,
A similar problem is encountered because a base electrode and a collector electrode are formed in a portion where the surface morphology is deteriorated.

On the other hand, in the recess etching by the above-mentioned second method, since the etching rate on the surface of the AlGaAs Schottky barrier layer 5 becomes slow, improvement of the surface morphology can be expected.

However, in order to sufficiently improve the surface morphology, it is desirable that the etching selectivity be large.
For that purpose, the AlAs molar ratio in AlGaAs must be increased. However, since AlGaAs having a large AlAs molar ratio is easily oxidized and forms an energy level called DX center which is not preferable from the viewpoint of HFET characteristics, AlGaAs having such a large AlAs molar ratio is added to the Schottky barrier layer 5. If used, the characteristics and reliability of the HFET deteriorate.

Therefore, according to the recess etching by the second method, the AlAs molar ratio which can optimize the characteristics of the HFET and the AlA which can optimize the surface morphology can be obtained.
Since this does not match the s molar ratio, a problem is encountered that it is difficult to design an optimum device.

It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can solve the above-mentioned problems.

[0026]

SUMMARY OF THE INVENTION The present invention provides a non-alloy ohmic device formed by laminating a semiconductor substrate and a semiconductor layer on the semiconductor substrate that is not lattice-matched to the semiconductor substrate to a thickness greater than a critical thickness. A contact layer, which is firstly directed to a semiconductor device, and in order to solve the above-mentioned technical problem, a flattening layer having an etching characteristic different from that of the semiconductor layer is provided between the semiconductor substrate and the semiconductor layer. It is characterized by being formed. The flattening layer is made of a semiconductor which is lattice-matched with the semiconductor substrate or which does not have a lattice-matching but has a thickness less than or equal to the critical thickness.

In a first preferred embodiment, the semiconductor substrate is made of GaAs, the non-alloy ohmic contact layer is made of In _x Ga _{1 -x} As (x ≧ 0.5), and the planarizing layer is made of , In _y Ga _1-y P (0 ≦ y ≦ 1).

In a second preferred embodiment, the semiconductor substrate is made of GaAs, the non-alloy ohmic contact layer is made of In _x Ga _{1 -x} As (x ≧ 0.5), and the flattening layer is made of , Al _z Ga _{1 -z} As (0 <z ≦ 1)
Consists of

In a third preferred embodiment, the semiconductor substrate is made of InP, the non-alloy ohmic contact layer is made of In _x Ga _{1 -x} As (x> 0.53), and the flattening layer is , InP.

In a fourth preferred embodiment, the semiconductor substrate is made of InP, the non-alloy ohmic contact layer is made of In _x Ga _{1 -x} As (x ≧ 0.53), and the planarizing layer is , In _z Al _1-z As (0 ≦ z <1)
Consists of

The present invention is also directed to a method for manufacturing a semiconductor device.

In this method of manufacturing a semiconductor device, a step of preparing a semiconductor substrate and a step of forming a semiconductor on the semiconductor substrate, which is lattice-matched with the semiconductor substrate or which does not have a lattice-matching but has a film thickness less than or equal to the critical film thickness. Forming a planarization layer,
By stacking a semiconductor layer that does not lattice-match with the semiconductor substrate on the planarization layer to a thickness greater than the critical thickness, non-alloyed
A step of forming an ohmic contact layer, a step of forming an ohmic electrode on the non-alloy ohmic contact layer, a step of recess etching the semiconductor layer and the planarizing layer, and a step of forming a recess in the recess formed by the recess etching. Forming an electrode on the
In order to solve the above technical problem, the present invention is characterized by having the following configuration.

That is, the flattening layer has an etching characteristic different from that of the semiconductor layer. In the recess etching step, the semiconductor layer is formed by utilizing the difference in etching characteristics between the flattening layer and the semiconductor layer. The method is characterized by including a step of stopping the etching at the flattening layer while selectively etching, and then a step of etching the flattening layer.

[0034]

1 to 5 sequentially show typical steps involved in a method of manufacturing a semiconductor device according to an embodiment of the present invention, more specifically, a method of manufacturing an HFET. I have. FIGS. 1 to 5 correspond to FIGS. 8 to 12, respectively, and FIGS. 1 to 5 correspond to FIGS.
, Elements corresponding to the elements shown in FIGS. 8 to 12 are denoted by the same reference numerals.

Referring to FIG. 1, first, semi-insulating GaAs
A substrate 1 is prepared.

Next, on the GaAs substrate 1, an undoped GaAs buffer layer 2, an undoped InGaAs channel layer 3, an n-type Al _0.25 Ga _0.75 As carrier supply layer 4,
Undoped Al _0.25 Ga _0.75 As Schottky barrier layer 5,
n-type GaAs cap layer 6, n-type In _0.5 Ga _0.5 P planarization layer 15, n-type In _x Ga _1-x As gradient composition layer 7 (x
= 0 → 0.5) and the n-type In _0.5 Ga _0.5 As ohmic contact layer 8 are sequentially formed by the MBE method and the MOCV
It is formed by epitaxial growth by the D method or the like.

As in the conventional case, the composition and thickness of the InGaAs channel layer 3 are selected so as to be less than the critical thickness in order to prevent the occurrence of misfit dislocation (for example, the InAs mole ratio). = 0.2,
Film thickness 10 nm).

Further, InGaP for the planarization layer 15, even without the lattice-matched GaAs substrate 1, the thickness need only be critical thickness less but, an In _0.5 Ga _0.5 P is lattice matched with the GaAs substrate 1 More preferably, it consists of The thickness of the planarizing layer 5 is desirably as thin as possible to prevent an increase in contact resistance.

With the above structure, the buffer layer 2, channel layer 3, carrier supply layer 4, cap layer 6, and planarization layer 15 formed on the GaAs substrate 1 are lattice-matched with the GaAs substrate 1. Therefore, dislocation does not occur, and the interface between these layers can be made flat.

On the other hand, since the composition gradient layer 7 and the ohmic contact layer 8 need to have a sufficiently low contact resistance, it is necessary to increase the InAs molar ratio and to make the thickness more than the critical film thickness. Yes, as a result, dislocations are generated, and the surface morphology is deteriorated as shown in FIG.

Next, as shown in FIG. 2, the unnecessary portion 9 is removed so as to reach the buffer layer 2, whereby the unnecessary portion 9 is removed.
Each element is electrically isolated from each other.

Next, an ohmic electrode 10 is formed on the ohmic contact layer 8 as shown in FIG.

Next, as shown in FIG. 4, a photoresist 11 having a desired pattern is formed.

Next, a recess etching step is performed to a predetermined depth so as to obtain a desired threshold voltage, whereby a recess 12 is formed. Details of the recess etching step will be described with reference to FIG.

FIG. 6A shows a state in which dislocation occurs in the composition gradient layer 7 and the ohmic contact layer 8 and the surface morphology is deteriorated, as described above.

In the structure shown in FIG.
InGaP forming the planarization layer 15 is composed of InGaAs forming the composition gradient layer 7 and the ohmic contact layer 8.
s, AlGaAs forming the Schottky barrier layer 5 and GaAs forming the cap layer 6 have different etching characteristics. Utilizing this difference in etching characteristics, etching is performed as follows.

That is, after forming the photoresist 11 on the ohmic contact layer 8, first, InGaAs
s can be etched but InGaP cannot be etched (for example, a mixture of phosphoric acid, hydrogen peroxide and water, or a mixture of sulfuric acid, hydrogen peroxide and water), and As a result, as shown in FIG. 6 (2a) or FIG. 6 (2b), the ohmic contact layer 8
And the composition gradient layer 7 is removed. And InGaP
Is not etched, so this etching
Stop at the aP planarization layer 15.

At this time, no dislocation is generated in the InGaP flattening layer 15, and therefore, the interface between the flattening layer 15 and the composition gradient layer 7 is flat at the atomic layer level, and the morphology is good. Interface, ie, InGaP planarization layer 15
Surface appears. As described above, the influence of the bad surface morphology of the ohmic contact layer 8 is removed, and the variation in etching is suppressed. As a result, as shown in FIG. 6 (2a), the surface morphology of the etched portion is improved. be able to.

FIG. 6B shows a case where the surface morphology of the ohmic contact layer 8 is very poor, and the surface morphology of the etched portion is not sufficiently improved by the above-described etching. Even in this case, as will be described later, the surface morphology can be improved to a sufficiently good level in a later etching step.

Next, the substrate is immersed in an etching solution (eg, a mixture of hydrochloric acid, hydrogen peroxide and water) that can etch InGaP but cannot etch GaAs,
Thereby, as shown in FIG. 6C, the InGaP flattening layer 15 is removed.

At this time, as shown in FIG. 6B, even if the surface morphology of the etched portion is not sufficiently improved in the previous etching step, the InGaP flattening layer 15 is not removed in this etching step. By removing only the morphology and exposing the surface of the GaAs cap layer 6 having good morphology, the surface morphology of the etched portion can be improved to a sufficiently good level.

The selectivity of InGaAs / InGaP by the mixed solution of phosphoric acid, hydrogen peroxide solution and water as the etchant used for removing the above-mentioned ohmic contact layer 8 and composition gradient layer 7 is 100 or more. In addition, the selectivity of InGaP / GaAs by a mixture of hydrochloric acid, hydrogen peroxide solution and water as an etchant used for removing the planarization layer 15 is 1000 or more. Therefore, a sufficiently large selectivity can be given, and good surface morphology can be maintained.

As shown in FIG. 6C, after the planarizing layer 15 is removed, further etching is performed to obtain a desired threshold voltage. The same method as the two methods shown in the related art can be applied to this etching.

That is, according to the first method, InGa
Monitoring and etching of the current value between the ohmic electrodes 10 using an etching solution (for example, a mixed solution of phosphoric acid, hydrogen peroxide solution, and water) in which the etching characteristics of As, GaAs, and AlGaAs are not significantly different from each other. Are performed alternately, and etching is performed until a predetermined current value is obtained.

If the etching by the above-described first method is employed, the surface morphology of the bottom of the formed recess 12 is improved.
When the gate electrode 13 is formed on the surface of the Schottky barrier layer 5, the distance from the bottom surface of the gate electrode 13 to the channel layer 3 becomes uniform, and the uniformity of the threshold can be improved.

On the other hand, according to the second method, AlGaAs
Etching is performed using an etching solution (for example, a mixed solution of citric acid, ammonia water, hydrogen peroxide solution, and water) having a sufficiently low etching rate, and the etching is performed on the surface of the AlGaAs Schottky barrier layer 5. Stop. In this method, in order to obtain a desired threshold value when the etching is stopped, the AlGaAs Schottky barrier layer 5 is formed at the epitaxial growth stage.
Needs to be controlled in advance.

If the etching by the above-described second method is adopted, the A in the AlGaAs Schottky barrier layer 5
Even if the lAs molar ratio is set to an optimum value on the characteristics of the HFET,
A good morphological recess 12 can be formed, and H
The uniformity of the threshold value can be improved without sacrificing the characteristics of the FET.

Thus, the recess etching is completed, and a recess 12 as shown in FIG. 4 is formed.

FIG. 7 shows such a change in surface roughness (Ra) before and after the recess etching in the case of this embodiment and the case of the above-mentioned prior art. In the case of the prior art, by recess etching,
While the surface roughness (Ra) is about 1.5 times,
According to this embodiment, it can be seen that the surface roughness (Ra) is reduced to about 1/3 times and the flatness is improved.

After finishing the recess etching process, the photoresist 11 is removed.

Next, as shown in FIG. 5, a gate electrode 13 is formed in the recess 12.

Thus, the main part of the HFET is completed.

Although the present invention has been described with reference to a specific embodiment, various modifications can be made within the scope of the present invention as exemplified below.

First, in the above embodiment, the planarizing layer 15
Although InGaP is used as the material of the above, any material may be used as long as the material has etching characteristics different from those of InGaAs.

For example, Al _x G is used as a material for the planarizing layer.
Using a _1-x As (0 <x ≦ 1) and using a mixed solution of citric acid, ammonia water, hydrogen peroxide water and water as an etching solution, stop etching on the surface of the AlGaAs planarization layer. You may do so. At this time, Al
As the AlAs molar ratio of GaAs increases, the etching rate decreases, and the selectivity with InGaAs increases. Therefore, the composition of the planarizing layer is preferably as high as the AlAs molar ratio.

Although the GaAs substrate 1 is used in the above-described embodiment, for example, an InP substrate may be used. In this case, even if InP is used as the material of the flattening layer, or In _z Al having a thickness equal to or less than the critical film thickness is used.
_1-z As (0 ≦ z <1) may be used.

As described above, when InP is used as the material for the planarizing layer, the InGaAs ohmic contact layer and the InGaAs composition gradient layer are selectively formed by a mixture of phosphoric acid, hydrogen peroxide and water. In the case where InAlAs is used as a material for the flattening layer, the InGaAs ohmic contact layer and the InGaAs composition gradient layer are selectively formed by a mixture of citric acid, hydrogen peroxide and water. It may be etched. In these cases, the ohmic contact layer preferably has a composition of In _x Ga _{1 -x} As (x> 0.53).

Although the above-described embodiment relates to an HFET, the present invention can be applied to other semiconductor devices such as an HBT.

[0069]

As described above, according to the present invention, a flattening layer having an etching characteristic different from that of a semiconductor layer is provided between a semiconductor substrate and a semiconductor layer forming a non-alloy ohmic contact layer. In a recess etching step for forming a recess in a semiconductor device having such a structure, a difference in etching characteristics between the planarization layer and the semiconductor layer is used to form a semiconductor layer. While selectively etching is performed, the etching is stopped at the flattening layer, and then the flattening layer is etched.

Further, since the flattening layer is made of a semiconductor which is lattice-matched with the semiconductor substrate or which is not lattice-matched but whose thickness is equal to or less than the critical thickness, dislocations are generated in this flattening layer. Therefore, the interface between the planarizing layer and the layer in contact with the planarizing layer can be made flat.

Based on these facts, a non-alloy alloy formed by laminating a semiconductor layer that does not lattice match with the semiconductor substrate to a thickness greater than or equal to the critical thickness is related to the semiconductor substrate.
The effect of surface morphology degradation caused by the difference in lattice constant between the ohmic contact layer and the underlying layer is advantageously blocked by the planarization layer and the surface morphology at the bottom of the recess formed by recess etching. Can be improved. Therefore, the uniformity of the characteristics of the semiconductor device is improved, and the production yield of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically illustrating a structure obtained by a first step, for explaining a method of manufacturing an HFET as a semiconductor device according to an embodiment of the present invention.

FIG. 2 shows a second step performed after the first step shown in FIG.
FIG. 5 is a cross-sectional view schematically showing a structure obtained by the step of FIG.

FIG. 3 shows a third step performed after the second step shown in FIG. 2;
FIG. 5 is a cross-sectional view schematically showing a structure obtained by the step of FIG.

FIG. 4 is a view showing a fourth step performed after the third step shown in FIG. 3;
FIG. 5 is a cross-sectional view schematically showing a structure obtained by the step of FIG.

FIG. 5 shows a fifth step performed after the fourth step shown in FIG. 4;
FIG. 4 is a cross-sectional view schematically showing a structure obtained by the step of FIG. 3, showing a main part of the obtained HFET.

FIG. 6 is an illustrative cross-sectional view for explaining details of a recess etching step as a fourth step shown in FIG. 4;

FIG. 7 is a diagram showing a change in surface roughness before and after recess etching in a case according to an embodiment of the present invention and a case according to a conventional technique.

FIG. 8 is a cross-sectional view schematically showing a structure obtained by a first step included in a conventional method for manufacturing an HFET that is interesting to the present invention.

FIG. 9 shows a second step performed after the first step shown in FIG.
FIG. 5 is a cross-sectional view schematically showing a structure obtained by the step of FIG.

FIG. 10 is a cross-sectional view schematically showing a structure obtained by a third step performed after the second step shown in FIG.

11 is a cross-sectional view schematically showing a structure obtained by a fourth step performed after the third step shown in FIG.

FIG. 12 is a cross-sectional view schematically showing a structure obtained by a fifth step performed after the fourth step shown in FIG. 11, showing a main part of the obtained HFET.

FIG. 13 is a cross-sectional view for explaining details of a fourth step shown in FIG. 11, and shows a problem to be solved by the present invention.

[Description of Signs] 1 semi-insulating GaAs substrate (semiconductor substrate) 2 buffer layer 3 channel layer 4 carrier supply layer 5 Schottky barrier layer 6 cap layer 7 composition gradient layer 8 ohmic contact layer 10 ohmic electrode 11 photoresist 12 recess 13 Gate electrode 15 Flattening layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/331 29/73 F term (Reference) 4M104 AA05 BB14 BB36 CC01 CC03 DD06 DD15 DD43 DD48 DD64 DD72 GG06 GG11 HH15 HH20 5F003 BF06 BH00 BH05 BH08 BH18 BM02 BM03 BP32.

Claims (6)

[Claims] 1. A semiconductor substrate comprising: a semiconductor substrate; and a non-alloy ohmic contact layer formed on the semiconductor substrate by laminating a semiconductor layer that is not lattice-matched with the semiconductor substrate to a critical thickness or more. A semiconductor device, further comprising: a planarization layer formed between the semiconductor substrate and the semiconductor layer, the planarization layer having different etching characteristics from the semiconductor layer, wherein the planarization layer lattice-matches with the semiconductor substrate. Or a semiconductor device comprising a semiconductor which does not lattice match but has a thickness less than or equal to a critical thickness. 2. The method according to claim 1, wherein the semiconductor substrate is made of GaAs,
The non-alloy ohmic contact layer is made of In
_2. The semiconductor device according to claim 1, wherein the flattening layer is made of _x Ga _1-x As (x ≧ 0.5), and the flattening layer is made of In _y Ga _1-y P (0 ≦ y ≦ 1). 3. The semiconductor substrate is made of GaAs,
The non-alloy ohmic contact layer is made of In
_2. The semiconductor device according to claim 1, wherein the semiconductor device is made of xGa ₁ -xAs (x ≧ 0.5), and the flattening layer is made of Al _z Ga ₁ -zAs (0 <z ≦ 1). 4. The semiconductor substrate is made of InP, and the non-alloy ohmic contact layer is made of In _x
2. The semiconductor device according to claim 1, wherein said semiconductor device is made of Ga _1-x As (x> 0.53), and said planarization layer is made of InP. Wherein said semiconductor substrate is made of InP, the non-alloy ohmic contact layer, an In _x
2. The semiconductor device according to claim 1, wherein the semiconductor device is made of Ga _1-x As (x> 0.53), and the flattening layer is made of In _z Al _1-z As (0 ≦ z <1). 6. A step of preparing a semiconductor substrate, and a flattening layer on the semiconductor substrate, which is made of a semiconductor which is lattice-matched to the semiconductor substrate or which is not lattice-matched but whose thickness is equal to or less than a critical thickness. Forming a non-alloy ohmic contact layer on the planarization layer by laminating a semiconductor layer that is not lattice-matched to the semiconductor substrate to a critical thickness or more; Forming an ohmic electrode on the alloy ohmic contact layer, recess etching the semiconductor layer and the planarizing layer, and forming an electrode in the recess formed by the recess etching. The flattening layer has an etching characteristic different from that of the semiconductor layer, and the recess etching step includes the flattening layer and the semiconductor. By utilizing the difference in etching properties between, while selectively etching the semiconductor layer, a step of stopping the etching at the planarization layer, then,
Etching the flattening layer.