JP4704614B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly, to a method for manufacturing a compound semiconductor device combining crystal growth technology capable of controlling monoatomic layer (superlattice) growth and wet etching technology, and the same. It relates to the semiconductor element used.
[0002]
[Prior art]
In general, a method of manufacturing a conventional compound semiconductor device having a zero-dimensional confinement quantum effect, for example, a quantum dot laser, has been reported in the literature such as “Applied Physics Vol. 67, No. 7 (1998) p776-786”. As one of the methods, a method as shown in FIG. 5 has been proposed.
[0003]
In this method, as shown in FIG. 5A, first, for example, an organic resist 102 is formed on a semiconductor epitaxial substrate 100 obtained by epitaxial growth on an n-type semiconductor substrate, and a mask 104 is overlaid thereon and exposed. Next, as shown in FIG. 5B, dip-type dots 106 are formed by wet etching, for example. Next, the resist 102 is removed, and as shown in FIG. 5C, a crystal growth method capable of controlling the monoatomic layer growth again, for example, molecular beam epitaxy (MBE), is formed on the semiconductor epitaxial substrate 100 on which the dots 106 are formed. The quantum dots 114 having a heterojunction type quantum well structure are formed by epitaxially growing the quantum well layer 108, the P-type cladding layer 110, and the p-type contact layer 112 by a molecular beam epitaxy (Molecular Beam Epitaxy) method. Then, as shown in FIG. 5D, a P-type electrode 116 is formed on the contact layer 112, and an n-type electrode 118 is formed on the lower side of the semiconductor epitaxial substrate 100, thereby producing a semiconductor laser.
[0004]
Thus, a semiconductor laser having a quantum dot structure portion as an active layer is a quantum dot laser, and a dramatic improvement in characteristics can be expected.
[0005]
[Problems to be solved by the invention]
However, a semiconductor element manufactured by the above-described conventional technology, for example, a quantum dot laser, has a surface level (or interface level) formed mainly by a resist material and O (oxygen), C (carbon), etc. resulting from resist processing. When compared with the ratio of the active layer size (about 10 nm) as compared with the active layer of a normal two-dimensional quantum well structure type semiconductor laser, the number increases rapidly. That is, for example, impurities such as oxygen and carbon adhere to the interface 120 in the etching step shown in FIG.
[0006]
For this reason, electrons injected into the conduction band in the barrier layer and the active layer come to be bonded to holes at the surface (interface) level with a higher probability than to be combined with holes in the full band (surface re-growth). Combined). As a result, there is a problem that the characteristics of the semiconductor laser deteriorate.
[0007]
Therefore, in order to fabricate a quantum dot laser having good characteristics, in addition to the technique of creating a quantum well structure of nanometer (nm) size that exhibits a zero-dimensional quantum confinement effect, the above surface (interface) It is necessary to suppress recombination between level holes and electrons, that is, to reduce impurities attached to the interface.
[0008]
The present invention has been made to solve the above-mentioned problems, and suppresses deterioration of a semiconductor element manufacturing method and operation characteristics for forming at least a nanometer-sized dot pattern on a semiconductor layer with a required size and density. An object of the present invention is to provide a semiconductor element that can be used.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a method of manufacturing a semiconductor device according to the first aspect of the present invention includes a mask layer made of GaAs or InP doped with Zn atoms on a first semiconductor layer made of GaAs or InP. A step of forming by epitaxial growth capable of controlling atomic layer growth, and removing at least the Zn atoms on the outermost surface of the mask layer using a solution for removing the Zn atoms. And a step of forming a hole-like dot pattern in the semiconductor layer.
[0010]
According to the present invention, for example, in a method for manufacturing a semiconductor device such as a semiconductor laser having a quantum well structure or a field effect transistor, Zn is formed on a first semiconductor layer made of GaAs (gallium arsenide) or InP (indium phosphide). A mask layer made of GaAs or InP doped with atoms is formed by epitaxial growth capable of controlling monoatomic layer growth. For the first semiconductor layer, for example, a semi-insulating or n-type or p-type (100) GaAs substrate or a semi-insulating or n-type or p-type (100) InP substrate can be used.
[0011]
Then, by removing at least Zn atoms on the outermost surface of the mask layer using a solution for removing Zn atoms, for example, by immersing in sulfuric acid at a predetermined condition, for example, a predetermined temperature and time, that is, By performing wet etching, a hole-like dot pattern is formed in the mask layer and the first semiconductor layer. Since the diameter and depth of the hole-like dot pattern vary depending on the temperature of the predetermined solution and the immersion time, the required dot size, that is, the size that can produce the required quantum effect, the mask layer, and the first semiconductor Predetermined conditions are set according to the layer. The doping concentration of Zn atoms doped in the mask layer is set according to the necessary dot formation interval.
[0012]
As described above, since a hole-like dot pattern for forming quantum dots can be formed only by a basic substrate processing process and crystal growth without using any resist, oxide film, or the like. The surface can be a clean surface free of impurities.
[0013]
A semiconductor device according to a second aspect of the present invention includes a first semiconductor layer made of GaAs or InP, a mask layer made of GaAs or InP doped with Zn atoms, formed by epitaxial growth capable of controlling monoatomic layer growth, and Removing at least the Zn atoms on the outermost surface of the mask layer using a solution for removing the Zn atoms, thereby forming a hole-like dot pattern formed in the mask layer and the first semiconductor layer; An active layer formed on the mask layer and a second semiconductor layer formed on the active layer.
[0014]
According to this invention, the hole-like dot pattern formed in the mask layer and the first semiconductor layer is formed by the method for manufacturing a semiconductor element according to claim 1. Next, a quantum dot that confines electrons in a zero-dimensional manner is formed by epitaxially growing a required quantum well structure as an active layer thereon. Further, subsequently, the second semiconductor layer is formed by epitaxial growth. Thereby, it can be made to function as a quantum dot laser, for example.
[0015]
Thus, since a hole-like dot pattern for forming quantum dots is formed only by epitaxial growth capable of controlling basic substrate processing and monoatomic layer growth without using any resist or oxide film, etc., The surface of the hole-like dot pattern becomes a clean surface free of impurities. Therefore, most of the electrons injected into the active layer flow into the quantum dots because there are no impurity levels as recombination centers at the interface. Thereby, since the electrons are efficiently injected into the active layer, the laser characteristics can be improved.
[0016]
As described in claim 3, the active layer is made of In._zGa_1-zIt can be configured to be composed of As (0 <z <1).
[0017]
According to a fourth aspect of the present invention, each of the mask layer, the first semiconductor layer, and the second semiconductor layer is made of GaAs, and the first semiconductor layer is on a first conductivity type substrate. A buffer layer, a first cladding layer, and a first barrier layer, and the second semiconductor layer is formed on the second barrier layer with the second conductivity type second cladding layer and the second barrier layer. A structure in which conductive contact layers are sequentially stacked can be employed.
[0018]
According to a fifth aspect of the present invention, the mask layer is made of GaAs, and the first semiconductor layer is made of Al on a first conductivity type substrate made of GaAs._xGa_1-xA buffer layer made of As (0 <x <0.4), a first cladding layer, and a first barrier layer are sequentially stacked, and each of the second semiconductor layers is made of Al._xGa_1-xA second barrier layer made of As (0 <x <0.4), a second conductivity type second cladding layer, and a second conductivity type contact layer are sequentially stacked, and the active layer is formed of the Al layer._xGa_1-xIt can be configured by an epitaxial layer having an energy gap smaller than As (0 <x <0.4).
[0019]
In addition, as described in claim 6, the mask layer, the first semiconductor layer, and the second semiconductor layer are each composed of InP, and the first semiconductor layer is formed on a substrate of a first conductivity type. A buffer layer, a first cladding layer, and a first barrier layer, and the second semiconductor layer is formed on the second barrier layer with the second conductivity type second cladding layer and the second barrier layer. A structure in which conductive contact layers are sequentially stacked can be employed.
[0020]
Further, as described in claim 7, the mask layer is made of InP, and the first semiconductor layer is made of InP on a substrate of the first conductivity type made of InP._yAl_1-yA buffer layer made of As (0 <y <1), a first cladding layer, and a first barrier layer are sequentially stacked, and each of the second semiconductor layers is made of In._yAl_1-yA second barrier layer made of As (0 <y <1), a second conductivity type second cladding layer, and a second conductivity type contact layer are sequentially stacked, and the active layer is formed of the In layer._yAl_1-yIt can be configured by an epitaxial layer having an energy gap smaller than As (0 <y <1).
[0021]
  Further, as described in claim 8BeforeThe first semiconductor layer and the second semiconductor layerIs Al_xGa_1-xAs (0 <x <0.4), the first semiconductor layer is formed by sequentially stacking a buffer layer, a donor layer doped with an n-type impurity, and a spacer layer on a semi-insulating substrate. The second semiconductor layer may be formed by stacking a contact layer doped with an n-type impurity on a Schottky layer.
[0022]
  Further, as described in claim 9BeforeThe first semiconductor layer and the second semiconductor layerIs In_yAl_1-yAs (0 <y <1), the first semiconductor layer is formed by sequentially stacking a buffer layer, a donor layer doped with an n-type impurity, and a spacer layer on a semi-insulating substrate, The second semiconductor layer can be formed by stacking a contact layer doped with an n-type impurity on a Schottky layer.
[0023]
According to the invention described in claim 8 or claim 9, a field effect transistor (FET) exhibiting single electron transistor operation can be produced by forming gate, source, and drain electrodes on the contact layer.
[0024]
The first conductivity type is, for example, n-type or p-type, and the second conductivity type is p-type or n-type. That is, when the first conductivity type is n-type, the second conductivity type is p-type, and when the first conductivity type is p-type, the second conductivity type is n-type.
[0025]
In addition, as described in claim 10, a semiconductor element manufactured using molecular beam epitaxy or metal organic vapor phase epitaxy for epitaxial growth capable of controlling monoatomic layer growth can be obtained.
[0026]
In addition, as described in claim 11, the semiconductor element can be manufactured using molecular beam epitaxy or metal organic vapor phase epitaxy as epitaxial growth capable of monolayer growth control.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
Hereinafter, as a first embodiment of the present invention, a method of forming a hole-like dot pattern in a mask layer and a continuous semiconductor layer formed by an epitaxial growth method capable of at least monoatomic layer growth control will be described.
[0028]
First, as shown in FIG. 1A, a non-doped GaAs buffer layer 14 is epitaxially grown to a thickness of 500 nm on a semiconductor substrate, for example, a semi-insulating (100) GaAs substrate 12. Subsequently, a Zn-doped GaAs layer 16 serving as a mask layer in the present invention is epitaxially grown by 3 nm. The Zn doping concentration of the Zn-doped GaAs layer 16 is 1 × 10¹⁷cm^-3It is. For this amount of doping, 10% in the GaAs crystal.⁶Zn atoms are uniformly distributed at a ratio of about 1 to one atom.
[0029]
The epitaxial growth of at least the mask layer is performed by an MBE crystal growth apparatus (not shown) using, for example, the MBE method, which is an epitaxial crystal growth method capable of controlling the monoatomic layer growth in order to be able to cope with the miniaturization of the pattern size. .
[0030]
Then, the epitaxial substrate 11 manufactured in this way is once taken out from an MBE crystal growth apparatus (not shown), and sulfuric acid (H) heated to 90 ° C. as shown in FIG.₂SO_Four) For one minute as an example.
[0031]
Thereby, an inverted conical dot 18 having a diameter of a circle on the upper surface of about 20 nm and a depth of about 10 nm as shown in FIG. 1C is formed. Here, as described above, the Zn doping amount of the Zn-doped GaAs layer 16 is 1 × 10 5.¹⁷cm^-3Therefore, when viewed from the center of the Zn atom in the GaAs crystal, it can be considered that there is no other Zn atom around a radius of about 10 nm, and one dot 18 is formed for almost one Zn atom. It can be estimated that it was formed.
[0032]
By the way, it is known that the size at which the quantum effect is remarkably exhibited in the electrons in the well-type potential is on the order of 10 nm. The dot 18 formed as described above has a size close to the size at which this quantum effect is manifested, and it can be seen that by using this invention, it is possible to produce a very fine pattern such as a quantum dot.
[0033]
Next, the mechanism by which the dots 18 are formed by wet etching will be described.
[0034]
It is known that Zn atoms doped in III-V compound semiconductors such as GaAs and InP are arranged at the group V atom position (As atom position in the case of GaAs).
[0035]
When the Zn-doped GaAs and InP layers are immersed at least under the above-described etching conditions, only doped Zn atoms located on the outermost surface layer are selectively desorbed first. When the wet etching is further continued, the group III Ga atom located at the nearest nearest position where the Zn atom has escaped is desorbed, and then the group V As atom located at the second nearest position is desorbed. Such a phenomenon occurs in a chain between Group V and Group III atoms starting from Zn atoms.
[0036]
In this way, the dot 18 is formed with the Zn atom desorption trace as the nucleus, because the surface of the microscopic hole-like dot formed by the removal of the Zn atom from the outermost surface of the GaAs (100) surface is the ( 100) This is due to the formation of a plane orientation different from the surface. That is, the GaAs (100) surface and the crystal plane of the micro dot pattern have different plane orientations, which is caused by the anisotropy (plane orientation dependence) of the etching rate of the etching solution in the GaAs crystal.
[0037]
In addition, among Zn atoms doped in GaAs, it is considered that the outermost surface Zn atoms are selectively desorbed due to a difference in binding energy between Zn atoms and As atoms in GaAs.
[0038]
For this reason, when the mask layer is etched in the sulfuric acid solution heated to 90 ° C. described in the present invention, micro lattice defects occurring around the lattice position of Zn atoms are caused by the Zn-doped GaAs layer 16 and The dots 18 are formed on the continuous non-doped GaAs buffer layer 14. The dots 18 gradually increase in size (upper surface diameter and depth) corresponding to the etching time.
[0039]
Thus, in this embodiment, dots can be formed by only basic substrate processing and crystal growth without using an organic resist or oxide film that is often used in normal pattern formation processes. The subsequent outermost surface of the epitaxial layer is contamination free, that is, a clean surface free of impurities.
[0040]
As described above, when impurities are incorporated into the surface of the epitaxial layer or the interface in the epitaxial layer by a process using an organic resist or the like, carrier depletion occurs in an electronic device, and non-radiative recombination of electrons occurs in an optical device. In any case, the Zn-doped GaAs layer 16 which is an epitaxial thin film layer is used as a mask in the present invention, so that the incorporation of impurities can be prevented.
[0041]
In addition, since an epitaxial growth method capable of controlling a single atomic layer is used as an epitaxial layer growth method, so-called atomic layer epitaxy is possible, and an epitaxial layer serving as a mask can form a very thin layer of about several atomic layers. Become. As a result, a fine pattern with a dot pattern size on the order of nanometers can be produced, and the degree of freedom in process design can be expanded.
[0042]
Further, the dot size can be formed to an arbitrary size by controlling the etching time, and the dot density can be arbitrarily designed by controlling the doping concentration of Zn atoms. Regarding the uniformity of the dot density, since the doping of Zn atoms is performed by the epitaxial growth method, an in-plane distribution with extremely high uniformity can be obtained.
[0043]
In this embodiment, the temperature of the sulfuric acid solution is set to 90 ° C., but the etching rate changes abruptly when the temperature of the solution is increased, so that it depends on the size of the dots 18 (the diameter and depth of the upper surface). And set the temperature and time.
[0044]
In the above description, the semi-insulating (100) GaAs substrate 12 and the Zn-doped GaAs layer 16 are used. However, an InP substrate and a Zn-doped InP epitaxial layer may be used.
[0045]
[Second Embodiment]
Next, as a second embodiment of the present invention, a method for manufacturing a semiconductor element, for example, a semiconductor laser, using the dot forming method described in the first embodiment will be described.
[0046]
FIG. 2 shows the steps of the semiconductor laser manufacturing method. First, as shown in FIG. 2A, for example, a (100) Si-doped GaAs substrate 20 (Si concentration: 3 × 10¹⁸cm^-3) On the n-GaAs buffer layer 22 (Si concentration: 3 × 10¹⁸cm^-3) By 100 nm epitaxial growth.
[0047]
Next, the n-GaAs cladding layer 24 is formed by 500 nm epitaxial growth. The n-GaAs cladding layer 24 has a Si doping concentration of 2 × 10.¹⁸cm^-3It is.
[0048]
Next, a non-doped GaAs barrier layer 26 is formed by 15 nm epitaxial growth, and further a Zn-doped GaAs layer 16 (Zn concentration: 1 × 10 10) serving as a mask layer in the present invention.¹⁷cm^-3) By 3 nm epitaxial growth.
[0049]
Then, the epitaxial substrate 11 manufactured in this way is once taken out from an MBE apparatus (not shown), and heated to 90 ° C. as shown in FIG.₂SO_Four) For one minute as an example. By this wet etching, as described in the first embodiment, hole-like dots 18 are formed from the Zn-doped GaAs layer 16 to the non-doped GaAs barrier layer 26 with the outermost surface Zn atoms as nuclei.
[0050]
Next, the epitaxial substrate 11 subjected to the above process is washed with water, set again in an MBE apparatus (not shown), and epitaxially grown to form a required quantum well structure for an active layer. That is, first, as shown in FIG. 2C, for example, non-doped In_0.15Ga_0.85The As active layer 27 is formed by 10 nm epitaxial growth.
[0051]
Next, the non-doped GaAs barrier layer 28 is 3 nm and the p-GaAs cladding layer 30 (Be concentration: 5 × 10¹⁸cm^-3) 500 nm, Be-doped p for electrode formation⁺-GaAs contact layer 32 (Be concentration: 1 × 10¹⁹cm^-3) By 100 nm epitaxial growth.
[0052]
Non-doped In sandwiched between the n-GaAs cladding layer 24 and the p-GaAs cladding layer 30_0.15Ga_0.85In the As active layer 27, a two-dimensional quantum well layer 27A having a thickness of 10 nm, which is the same as the design value, is formed on the (100) plane, and the In composition is lower than the design value at the bottom of the dip of the dot compared to the (100) plane. A large 0-dimensional quantum well structure, that is, a quantum dot 27B is formed. An example in which a quantum dot having a large In composition is formed when an inverted conical dot pattern is formed on a GaAs substrate and InGaAs is epitaxially grown thereon is described in Reference Applied Physics Letters, Vol. 61, No. 7 (1992). (Year), page 813, which is a well-known fact.
[0053]
Then, an electrode forming process similar to that of a normal semiconductor laser is applied to the epitaxial substrate having such a structure, and an electrode forming p⁺The quantum dot laser 10 is fabricated by forming the p-type electrode 34 on the upper side of the GaAs contact layer 32 and the n-type electrode 36 on the lower side of the (100) Si-doped GaAs substrate 20.
[0054]
When a current is passed through the quantum dot laser 10, most of the injected electrons once flow into the two-dimensional quantum well layer 27A having a thickness of 10 nm, but the quantum dot 27B has a lower conduction band energy level. Finally, electrons flow from the two-dimensional quantum well layer 27A to the quantum dots 27B, and stimulated emission occurs between the conduction band and the full band of the quantum dots 27B to cause laser oscillation.
[0055]
Thus, in this embodiment, since an organic resist or an oxide film often used in a normal pattern formation process or the like is not used, a contamination-free clean surface is formed at the regrowth interface. For this reason, since there is no impurity order as a recombination center at the heterointerface of the quantum well, almost all of the injected electrons flow from the two-dimensional quantum well layer 27A to the zero-dimensional quantum well layer, that is, the quantum dots 27B. As a result, the laser characteristics are improved.
[0056]
Further, the dot size can be formed to an arbitrary size by controlling the etching time, and the dot density can be arbitrarily designed by controlling the doping concentration of Zn atoms. Regarding the uniformity of the dot density, since the doping of Zn atoms is performed by the epitaxial growth method, an in-plane distribution with extremely high uniformity can be obtained.
[0057]
In this embodiment, the portion of the GaAs layer is made of Al._xGa_1-xThe non-doped InGaAs active layer 27 may be replaced with a non-doped GaAs layer in the As (0 <x <0.4) mixed crystal.
[0058]
In this embodiment, an n-GaAs substrate is used. For example, Zn is 2 × 10.¹⁹cm^{- Three}P doped to some extent⁺It is also possible to make a semiconductor quantum dot laser having a structure in which p-type and n-type are inverted using a GaAs substrate.
[0059]
[Third Embodiment]
Next, a third embodiment of the present invention will be described. In the second embodiment, a Si-doped GaAs substrate is used as a semiconductor substrate. In this embodiment, a case where an Sn-doped InP substrate is used as an n-type semiconductor substrate will be described. In addition, the case of using the metal organic vapor phase epitaxy (MOVPE) method, which is an epitaxial growth method that is generally used to grow the same crystal (InP) as the InP substrate, and can control the monoatomic layer growth. explain.
[0060]
First, as shown in FIG. 3A, an n-InP buffer layer 42 (Si concentration: 3 × 10 6) is formed on a (100) Sn-doped InP substrate 40 by MOVPE.¹⁸cm^{- Three}) To 100 nm.
[0061]
Next, the n-InP cladding layer 44 (Si concentration: 2 × 10¹⁸cm^-3) 500 nm, non-doped InP barrier layer 46 15 nm, and Zn-doped InP layer 48 (Zn concentration: 1 × 10¹⁷cm^-3) Is grown 3 nm epitaxially.
[0062]
Then, the epitaxial substrate 11 manufactured in this way is once taken out from a MOVPE crystal growth apparatus (not shown), and is etched for 1 minute in a sulfuric acid solution heated to 45 ° C. as an example, as shown in FIG.
[0063]
By the way, in the first embodiment and the second embodiment, the Zn-doped GaAs epitaxial layer is etched using sulfuric acid heated to 90 ° C. However, when the etching is performed up to this temperature in the configuration of this embodiment, Zn is etched. The desorption rate of InP and the etching rate of InP become 100 times or more faster and cannot be controlled.
[0064]
As described above, the etching rate changes even in the case of etching with sulfuric acid at the same temperature in the case of InP and in the case of GaAs. Therefore, it is necessary to set the temperature at an appropriate controllable etching rate.
[0065]
For this reason, in this embodiment, the temperature of sulfuric acid is set to 45 ° C. and wet etching is performed. By this wet etching, as described in the above embodiment, only Zn atoms are selectively desorbed first. When the etching is further continued, the In atom and the P atom are desorbed in a chain with the lattice position trace of the desorbed Zn atom as a nucleus, and a dip-shaped dot 18 is formed. This is because, as described in the above embodiment, a micro surface having a plane index different from the (100) surface is formed by the elimination of the outermost surface Zn atom of the InP layer, and etching is continued. Due to the etching anisotropy depending on the plane orientation on the surface of InP, this micro pattern is enlarged in a similar manner to form dots 18.
[0066]
Next, when the dots 18 having the required dot size are formed, the wet etching is stopped and the epitaxial substrate 11 is washed with water. The epitaxial substrate 11 is set again in a MOVPE apparatus (not shown), and the remaining epitaxial layers constituting the device structure are formed. Perform layer regrowth.
[0067]
That is, first, as shown in FIG._0.53Ga_0.47The As active layer 50 is formed by 10 nm epitaxial growth.
[0068]
Next, a non-doped InP barrier layer 52 is formed by 3 nm epitaxial growth.
[0069]
Next, the p-InP cladding layer 54 (Zn concentration: 1 × 10¹⁸cm^-3) 500 nm, p-InP contact layer 56 (Zn concentration: 2 × 10¹⁸cm^-3) By 100 nm epitaxial growth.
[0070]
Non-doped InP sandwiched between non-doped InP barrier layer 46 and p-InP cladding layer 54_0.53Ga_0.47The As active layer 50 forms a two-dimensional quantum well layer 50A having a thickness of 10 nm as designed on the (100) plane, and a zero-dimensional quantum having an In composition larger than that on the (100) plane at the dip bottom of the dot. A well structure, that is, a quantum dot 50B is formed.
[0071]
An epitaxial substrate having such a structure is subjected to an electrode forming process similar to that of a normal semiconductor laser, and a p-type electrode 58 is formed on the upper side of the p-InP contact layer 56, and the (100) Sn-doped InP substrate 40 is formed. The quantum dot laser 10 is produced by forming the n-type electrode 60 on the lower side.
[0072]
Most of the electrons injected from the electrode of the quantum dot laser 10 initially flow into the two-dimensional quantum well 50A on the (100) plane, but the zero-dimensional quantum well layer, that is, the quantum dot 50B has a conduction band energy. Since the level is low, it finally flows into the conduction band of the quantum dot 50B, and good laser oscillation characteristics due to the zero-dimensional confinement quantum effect can be obtained.
[0073]
In the present embodiment, the MOVPE method is used as an epitaxial growth method capable of controlling the monoatomic layer growth other than the MBE method that is relatively often used for epitaxial growth of a phosphorus (P) compound semiconductor. Similar to the second embodiment, Zn atoms are selectively desorbed by wet etching in the Zn-doped InP layer 48 which is a mask layer of a thin film epitaxially grown by the MOVPE method. By using the MOVPE method in this way, the Zn-doped InP layer 48 and the non-doped InP layer 46 serving as a mask can obtain the same kind of crystal layer (homoepi layer) having the same lattice distortion as the cladding layer.
[0074]
Further, since no organic resist or the like is used, a contamination-free clean surface can be obtained. For this reason, since the recombination center of an electron is not formed, the characteristic of a laser can be improved.
[0075]
In addition, since the dot size formed on the InP surface can be arbitrarily changed in proportion to the etching time, the size of the quantum dot size can be freely changed and the size can be made uniform. Since Zn atoms are incorporated into InP by doping, it is expected to be uniformly distributed in the crystal. Therefore, it is expected that the quantum dots are uniformly distributed on the crystal surface. Furthermore, by using an InP substrate, the energy gap of InP is smaller than that of GaAs, so the oscillation wavelength of the quantum dot laser is expected to change compared to that of GaAs, and the diversification of functions of the quantum dot laser is expected. I can expect.
[0076]
In this embodiment, the p-InP cladding layer 54, the n-InP cladding layer 44, the Zn-doped InP layer 48, and the non-doped InP barrier layer 46 are used._yAl_1-yAn As (y = 0.52) layer may be substituted.
[0077]
In this embodiment, an n-InP substrate is used. For example, Zn is 2 × 10.¹⁹cm^{- Three}It is also possible to make a semiconductor quantum dot laser having a structure in which p-type and n-type are inverted by using a p-InP substrate doped to some extent.
[0078]
[Fourth Embodiment]
Next, as a fourth embodiment of the present invention, a method for manufacturing another semiconductor element using quantum dots will be described.
[0079]
FIG. 4 shows a process of a manufacturing method of a field effect transistor (FET) using quantum dots, for example, a high electron mobility transistor (HEMT).
[0080]
First, as shown in FIG. 4A, a non-doped GaAs buffer layer 64 is formed on a semi-insulating semiconductor substrate, for example, a semi-insulating (100) GaAs substrate 62 by MBE, which is a growth method capable of controlling monoatomic layer growth. Of 500 nm, non-doped Al_0.3Ga_0.7An As barrier layer 66 is formed to 200 nm.
[0081]
Next, Si-doped Al_0.3Ga_0.7As donor layer 68 (Si concentration: 3 × 10¹⁸cm^-3) 10 nm, non-doped GaAs spacer layer (barrier layer) 10 nm, Zn-doped GaAs layer 72 serving as a mask (Zn concentration: 1 × 10^{1 7}cm^{- Three}) Are each formed by 3 nm epitaxial growth.
[0082]
Next, the epitaxial substrate 11 is once taken out from an MBE apparatus (not shown) and etched in sulfuric acid at a predetermined temperature for a predetermined time as shown in FIG. For example, etching is performed in a sulfuric acid solution heated to 90 ° C. for 1 minute. By this etching, dip-shaped dots 18 are formed on the surface of the Zn-doped GaAs layer 72 in the same manner as shown in the first and second embodiments.
[0083]
Then, when the required dot size is obtained, the wet etching is stopped and washed with water, and this washed and washed epitaxial substrate 11 is set again in an MBE apparatus (not shown), and the remaining epitaxial layer portion constituting the required device structure is formed. Re-grow.
[0084]
That is, first, as shown in FIG. 4C, for example, non-doped In_0.2Ga_0.8The As channel layer 74 is formed to 10 nm, and the non-doped GaAs Schottky layer 76 is formed to 10 nm.
[0085]
Next, the n-GaAs contact layer 78 (Si concentration: 3 × 10¹⁸cm^-3) By 100 nm epitaxial growth.
[0086]
The InGaAs channel layer 74 sandwiched between the non-doped GaAs barrier layer 70 and the non-doped GaAs Schottky layer 76 forms a 10-nm thick two-dimensional quantum well layer 74A on the (100) plane, and at the same time, the bottom of the dip-shaped dot Then, a 0-dimensional quantum well structure having a larger In composition than that on the (100) plane, that is, quantum dots 74B is formed.
[0087]
Then, the source and drain ohmic contacts 80S and 80D and the gate Schottky contact 80G are formed on the epitaxial substrate 11 by a semiconductor process similar to that of a normal field effect transistor, for example, a HEMT structure. For example, the gate length is 500 nm and the doping concentration of Zn is 1 × 10¹⁷cm^{- Three}In this case, it can be estimated that there are about 20 dots (Zn atoms) in a straight line between the source and the drain, and a dot array in which these dots are uniformly distributed in the two-dimensional quantum well is formed. FIG. 4 shows a case where one quantum dot is formed as a gate in order to prevent complexity. In this way, the field effect transistor 90 is manufactured.
[0088]
As described in the second and third embodiments, non-doped In_0.2Ga_0.8Carriers in the As channel layer 74 initially stay in the two-dimensional quantum well layer 74A that occupies a large area of the channel, but the quantum dot 74B has a higher In composition and a lower energy level in the conduction band. Thus, it falls into the zero-dimensional well layer of the quantum dot 74B.
[0089]
In the drain current-gate voltage characteristics of the semiconductor element having such a structure, by changing the gate voltage, the spread of the depletion layer is modulated, and at the same time, the potential inside the dot is modulated. For this reason, in addition to the normal FET characteristics as the gate voltage changes, a spike-like drain current peculiar to quantum dots can be obtained at a certain gate voltage.
That is, so-called single electron transistor operation is shown.
[0090]
In this manner, by using the Zn-doped GaAs layer thin film as a mask, a contamination-free clean surface is formed at the regrowth interface of the channel layer and the barrier layer, as described in the second and third embodiments. And a single electron transistor with little carrier depletion can be manufactured. The dot size and in-plane density can be arbitrarily designed by changing the etching time and Zn doping concentration, respectively.
[0091]
In this embodiment, a semi-insulating GaAs substrate is used. For example, a semi-insulating InP substrate is used, and a non-doped InP substrate is formed on the InP substrate._yAl_1-yAs (y = 0.52) buffer layer is 500 nm, n-In_yAl_1-yAs donor layer (Si concentration: 3 × 10¹⁸cm^{- Three}) 10 nm, non-doped In_yAl_1-yAs spacer layer (barrier layer) 10 nm, Zn-doped InP mask layer (Zn concentration: 1 × 10¹⁷cm^{- Three}) After 3nm epitaxial growth and sulfuric acid etching, again non-doped In_zGa_1-zAs (Z = 0.53) channel layer 10 nm, non-doped In_yAl_1-yAs Schottky layer 10nm, n-In_zGa_1-zAs contact layer (Si concentration: 3 × 10¹⁸cm^{- Three}) Is epitaxially grown by 50 nm, and a single-electron transistor can be produced on the InP substrate by producing source, drain and gate electrodes in a normal FET.
[0092]
【The invention's effect】
As described above, according to the present invention, first, since the epitaxial growth method capable of controlling the monoatomic layer growth is used for forming the mask layer, the hole-like dot pattern formed by etching is nano-sized. A very fine meter size can be obtained, and secondly, a hole-like dot pattern for forming quantum dots can be formed without using a resist or an oxide film. Can be a clean surface with few impurities.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a process of a semiconductor process according to a first embodiment.
FIG. 2 is a drawing for explaining a process of a method for manufacturing a semiconductor device according to a second embodiment.
FIG. 3 is a diagram for explaining a process of a semiconductor device manufacturing method according to a third embodiment.
FIG. 4 is a diagram for explaining a process of a method for manufacturing a semiconductor device according to a fourth embodiment.
FIG. 5 is a diagram for explaining a process of a semiconductor device manufacturing method according to a conventional example.
[Explanation of symbols]
10 Quantum dot laser
11 Epitaxial substrate
12 Semi-insulating (100) GaAs substrate
14 Non-doped GaAs buffer layer
16 Zn-doped GaAs layer (mask layer)
18 dots

Claims (11)

Forming a mask layer made of GaAs or InP doped with Zn atoms on the first semiconductor layer made of GaAs or InP by epitaxial growth capable of controlling monoatomic layer growth;
Forming a hole-like dot pattern in the mask layer and the first semiconductor layer by removing at least the Zn atoms on the outermost surface of the mask layer using a solution for removing the Zn atoms;
A method for manufacturing a semiconductor device, comprising: A first semiconductor layer made of GaAs or InP;
A mask layer made of GaAs or InP doped by Zn atoms and formed by epitaxial growth capable of controlling monoatomic layer growth;
A hole-like dot pattern formed in the mask layer and the first semiconductor layer by removing at least the Zn atoms on the outermost surface of the mask layer using a solution for removing the Zn atoms;
An active layer formed on the mask layer;
A second semiconductor layer formed on the active layer;
A semiconductor device comprising: The semiconductor device according to claim 2, wherein the active layer is made of In _z Ga _1-z As (0 <z <1).   The mask layer, the first semiconductor layer, and the second semiconductor layer are each made of GaAs, and the first semiconductor layer is formed on a first conductivity type substrate, a buffer layer, a first cladding layer, and a second cladding layer. The second semiconductor layer is formed by sequentially laminating a second conductivity type second cladding layer and a second conductivity type contact layer on the second barrier layer. The semiconductor element according to claim 2. The mask layer is made of GaAs, and the first semiconductor layer is a buffer layer made of Al _x Ga _1-x As (0 <x <0.4) on the first conductivity type substrate made of GaAs. A second barrier layer made of Al _x Ga _{1 -x} As (0 <x <0.4), respectively. A second conductivity type second cladding layer and a second conductivity type contact layer are sequentially stacked, and the active layer has energy higher than that of the Al _x Ga _1-x As (0 <x <0.4). 3. The semiconductor device according to claim 2, comprising an epitaxial layer having a small gap.   The mask layer, the first semiconductor layer, and the second semiconductor layer are each made of InP, and the first semiconductor layer is formed on a first conductivity type substrate with a buffer layer, a first cladding layer, and a first layer. The second semiconductor layer is formed by sequentially laminating a second conductivity type second cladding layer and a second conductivity type contact layer on the second barrier layer. The semiconductor element according to claim 2. The mask layer is made of InP, the first semiconductor layer is a buffer layer made of In _y Al _1-y As (0 <y <1) and a first cladding on a first conductivity type substrate made of InP. A second barrier layer made of In _y Al _1-y As (0 <y <1), and a second conductivity type. The second cladding layer and the second conductivity type contact layer are sequentially stacked, and the active layer is formed of an epitaxial layer having an energy gap smaller than that of In _y Al _{1 -y} As (0 <y <1). The semiconductor element according to claim 2, wherein the semiconductor element is formed. Before SL first semiconductor layer, and said second semiconductor layer is composed of _{A l x Ga 1-x As} (0 <x <0.4), the first semiconductor layer is semi-insulating substrate A buffer layer, a donor layer doped with an n-type impurity, and a spacer layer are sequentially stacked, and the second semiconductor layer is formed by stacking a contact layer doped with an n-type impurity on a Schottky layer. The semiconductor element according to claim 2, wherein the semiconductor element is formed. Before SL first semiconductor layer, and said second semiconductor layer is composed of _{I n y Al 1-y As} (0 <y <1), the first semiconductor layer, the buffer a semi-insulating substrate The second semiconductor layer is formed by stacking a contact layer doped with n-type impurities on a Schottky layer. The semiconductor element according to claim 2.   3. The semiconductor device according to claim 2, wherein the epitaxial growth capable of controlling the monoatomic layer growth uses a molecular beam epitaxy method or a metal organic vapor phase epitaxy method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the epitaxial growth capable of controlling the monoatomic layer growth uses a molecular beam epitaxy method or a metal organic vapor phase epitaxy method.

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