CN111341751A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN111341751A
CN111341751A CN201911088966.4A CN201911088966A CN111341751A CN 111341751 A CN111341751 A CN 111341751A CN 201911088966 A CN201911088966 A CN 201911088966A CN 111341751 A CN111341751 A CN 111341751A
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China
Prior art keywords
redistribution
layer
semiconductor package
layers
disposed
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Pending
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CN201911088966.4A
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English (en)
Inventor
朴正镐
金钟润
裵珉准
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN111341751A publication Critical patent/CN111341751A/zh
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Abstract

一种半导体封装包括：重分配基底，具有彼此相对的第一表面与第二表面，且包括绝缘构件、多个重分配层及重分配通孔，所述多个重分配层在所述绝缘构件中位于不同的水平层级上，所述重分配通孔具有在第一方向上从所述第二表面朝所述第一表面变窄的形状；多个球下金属(UBM)层，各自包括球下金属焊盘及球下金属通孔，所述球下金属焊盘位于所述重分配基底的所述第一表面上，所述球下金属通孔具有在与所述第一方向相反的第二方向上变窄的形状；以及至少一个半导体芯片，位于所述重分配基底的所述第二表面上，且具有多个接触焊盘，所述多个接触焊盘电连接到所述多个重分配层中与所述第二表面相邻的重分配层。

Description

半导体封装
[相关申请的交叉参考]
本申请主张在2018年12月18日在韩国知识产权局提出申请的韩国专利申请第10-2018-0164403号的优先权，所述韩国专利申请的公开内容全文以引用方式并入本申请。
技术领域
本发明概念涉及一种半导体封装。更具体来说，本发明概念涉及一种包括具有锥形形状的通孔的半导体封装。
背景技术
半导体封装可为当以适合用于电子产品中的形式实施半导体芯片(例如集成电路)时的结果。随着近年来电子产业的发展，已经针对减小大小、降低重量以及降低制造成本以各种方式对半导体封装进行了开发。
可提供一种晶片级封装(wafer level packaging，WLP)工艺作为制造半导体封装的方法。随着半导体芯片变得具有更高的集成度，半导体芯片的大小正在逐渐减小。然而，随着半导体芯片变得更小，变得难以附装所需数目的焊球，且焊球的处置及测试变得困难。
另外，可能存在的问题在于要安装的板的数目取决于半导体芯片的大小。为解决此问题，可使用包含重分配层(redistribution layer，RDL)技术的扇出面板级封装。
发明内容
本发明概念的态样可为通过减小在具有重分配层的重分配基底中造成的波动来提供一种可靠性高的半导体封装。
根据某些示例性实施例，本公开涉及一种半导体封装，所述半导体封装包括：重分配基底，具有被设置成彼此相对的第一表面与第二表面，且包括绝缘构件、多个重分配层及重分配通孔，所述多个重分配层在所述绝缘构件中设置在不同的水平层级上，所述重分配通孔对设置在邻近的水平层级上的所述重分配层进行连接且具有在第一方向上从所述第二表面朝所述第一表面变窄的形状；多个球下金属(under bump metallurgy，UBM)层，所述多个球下金属层中的每一者包括球下金属焊盘及球下金属通孔，所述球下金属焊盘设置在所述重分配基底的所述第一表面上，所述球下金属通孔连接到所述多个重分配层中与所述第一表面相邻的重分配层且连接到所述球下金属焊盘，并且所述球下金属通孔具有在与所述第一方向相反的第二方向上变窄的形状；以及至少一个半导体芯片，设置在所述重分配基底的所述第二表面上，且具有多个接触焊盘，所述多个接触焊盘电连接到所述多个重分配层中与所述第二表面相邻的重分配层。
根据某些示例性实施例，本公开涉及一种半导体封装，所述半导体封装包括：重分配基底，具有被设置成彼此相对的第一表面与第二表面，且包括多个绝缘层及设置在所述多个绝缘层之间的多个重分配层，其中所述多个重分配层包括与所述第一表面相邻的第一重分配层以及设置在所述第一重分配层与所述第二表面之间的至少一个第二重分配层，每一第二重分配层具有重分配通孔，所述重分配通孔连接到所述第一重分配层或所述至少一个第二重分配层中的邻近的第二重分配层；多个球下金属(UBM)层，设置在所述重分配基底的所述第一表面上，所述球下金属层中的每一者具有连接到所述第一重分配层的球下金属通孔；至少一个半导体芯片，设置在所述重分配基底的所述第二表面上，且具有接触焊盘，所述接触焊盘电连接到所述至少一个第二重分配层；以及模制部分，设置在所述重分配基底的所述第二表面上且覆盖所述至少一个半导体芯片，其中所述重分配通孔具有在第一方向上从所述第二表面朝所述第一表面变窄的形状，且所述球下金属通孔具有在与所述第一方向相反的第二方向上变窄的形状。
根据某些示例性实施例，本公开涉及一种半导体封装，所述半导体封装包括：重分配基底，具有被设置成彼此相对的第一表面与第二表面，且包括绝缘构件及在所述绝缘构件中设置在不同的水平层级上的多个重分配层；球下金属(UBM)层，包括球下金属焊盘及球下金属通孔，所述球下金属焊盘设置在所述重分配基底的所述第一表面上，所述球下金属通孔电连接所述球下金属焊盘与所述多个重分配层且具有在从所述第一表面朝所述第二表面的方向上变窄的形状；以及至少一个半导体芯片，设置在所述重分配基底的所述第二表面上，且具有接触焊盘，所述接触焊盘电连接到所述多个重分配层，其中所述多个重分配层包括：第一重分配层，在所述绝缘构件中设置在与所述第一表面相邻的水平层级上，且由平面状导电图案构成，以及多个第二重分配层，在所述绝缘构件中设置在不同的水平层级上，所述多个第二重分配层中的每一者具有重分配通孔，所述重分配通孔连接到所述第一重分配层或所述多个第二重分配层中的邻近的第二重分配层。
附图说明
结合附图阅读以下详细说明，将更清楚地理解本公开的以上及其他态样、特征及优点，在附图中：
图1是示出根据示例性实施例的半导体封装的剖视图。
图2是示出图1所示半导体封装的部分“A”的放大剖视图。
图3到图10是示出根据示例性实施例的制造半导体封装的方法的主要工艺的剖视图。
图11是示出根据示例性实施例的半导体封装的剖视图。
图12是示出根据示例性实施例的半导体封装的剖视图。
图13是图12所示半导体封装的平面图。
图14是示出根据示例性实施例的半导体封装的配置的方块图。
[符号的说明]
1：第一方向
2：第二方向
100、100'、100”、1000：半导体封装
110、110'：绝缘构件
111：绝缘层/第一绝缘层
112：绝缘层/第二绝缘层
113：绝缘层/第三绝缘层
115：绝缘层/基底绝缘层
120、120'：重分配结构
121：重分配层/第一重分配层
122：重分配层/第二重分配层
122a、122b：第二重分配层
122V：重分配通孔
125：接合焊盘
125V：通孔部分/UBM通孔
130、130'、130”：重分配基底
130A：第一表面
130B：第二表面
140：球下金属(UBM)层
140P：UBM焊盘
140V：UBM通孔
150：半导体芯片
150A：半导体芯片/第一半导体芯片
150B：半导体芯片/第二半导体芯片
150P：接触焊盘
150T：上表面
161：底部填充树脂
165：模制部分
170：钝化层
180：外部连接件
191：导热材料层
195：散热板
210：第一载体
220：第二载体
1010：微处理器
1020：存储器
1030：接口
1040：图形处理器
1050：功能块
A：部分
B：连接凸块
d1a、d2a、Da：下部宽度
d1b、d2b、Db：上部宽度
H：开口
h1：第一孔
h2：第二孔
t、T：厚度
具体实施方式
在下文中，将参照附图阐述本发明概念的各种实施例。
图1是示出根据示例性实施例的半导体封装的剖视图，且图2是示出图1所示半导体封装的部分“A”的放大剖视图。
参照图1，根据示例性实施例的半导体封装100可为呈扇出晶片级封装(fan-outwafer level package，FOWLP)形式的半导体封装。半导体封装100可包括重分配基底130，重分配基底130具有被设置成彼此相对且彼此背离的第一表面130A与第二表面130B。半导体封装100还可包括球下金属(UBM)层140及半导体芯片150，球下金属(UBM)层140设置在重分配基底130的第一表面130A上，半导体芯片150设置在重分配基底130的第二表面130B上。
半导体芯片150可包括半导体基底，所述半导体基底具有上面形成有各种分立的器件的有源表面以及与有源表面相对的非有源表面(inactive surface)。半导体基底可为单一半导体(例如硅(Si)及锗(Ge))或化合物半导体(例如SiC(碳化硅)、砷化镓(GaAs)、砷化铟(InAs)及磷化铟(InP))或者可具有绝缘体上硅(silicon on insulator，SOI)结构。举例来说，构成半导体芯片150的半导体基底可包括氧化物埋层(buried oxide，BOX)。各种分立的器件可包括各种微电子器件，例如金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field effect transistor，MOSFET)(例如互补金属-绝缘体-半导体(complementary metal-insulator-semiconductor，CMOS)晶体管)、系统大规模集成电路(systemlarge scale integration，LSI)、图像传感器(例如CMOS成像传感器(CMOSimaging sensor，CIS))、微机电系统(microelectro-mechanical system，MEMS)、有源器件、无源器件等。
半导体芯片150可包括多个接触焊盘150P，所述多个接触焊盘150P电连接到分立的器件且设置在有源表面上。
半导体芯片150可为存储器芯片或逻辑芯片。举例来说，存储器芯片可为易失性存储器芯片(例如动态随机存取存储器(dynamic randomaccess memory，DRAM)或静态随机存取存储器(static random access memory，SRAM))或者非易失性存储器芯片(例如相变随机存取存储器(phase-change random access memory，PRAM)、磁阻随机存取存储器(magnetoresistive random access memory，MRAM)、铁电随机存取存储器(ferroelectricrandom access memory，FeRAM)或电阻式随机存取存储器(resistive randomaccessmemory，RRAM))。另外，逻辑芯片可为例如微处理器、模拟器件或数字信号处理器。
重分配基底130可用作中间层以对半导体芯片150进行封装，从而将半导体芯片150安装在主板上。如图1所示，重分配基底130可包括绝缘构件110及重分配结构120，重分配结构120在绝缘构件110中设置在不同的水平层级上。绝缘构件110可包括多个绝缘层111、112及115，且重分配结构120可包括多个重分配层121及122，所述多个重分配层121及122分别设置在所述多个绝缘层111、112及115的边界表面上。
所述多个绝缘层111、112及115的边界表面可界定重分配层121及122的形成位置，但是根据一些实施例(例如，当所述多个绝缘层111、112及115由相同材料形成时)，所述多个绝缘层111、112及115的边界表面在最终结构中可能无法直接可视地观察到。所述多个重分配层121及122的一部分可包括重分配通孔122V，重分配通孔122V对设置在邻近的水平层级上的重分配层121及122进行连接。
在一些实施例中，所述多个绝缘层111、112及115可由树脂(例如环氧树脂或聚酰亚胺)制成。举例来说，所述多个绝缘层111、112及115可由感光性绝缘材料形成。重分配层121及122以及重分配通孔122V可包含例如铜、镍、不锈钢或铜合金(例如铍铜)。
具体来说，参照图2，将详细阐述此实施例中采用的重分配基底130的结构。图2是示出图1所示半导体封装的部分“A”的放大剖视图。
参照图2，所述多个重分配层121及122可包括第一重分配层121以及第二重分配层122，第一重分配层121设置在基底绝缘层115与第一绝缘层111之间，第二重分配层122设置在第一绝缘层111与第二绝缘层112之间。举例来说，第一重分配层121可设置在基底绝缘层115上且被第一绝缘层111覆盖，且第二重分配层122可设置在第一绝缘层111上且被第二绝缘层112覆盖。第一重分配层121可构成平面状导电图案，而不具有用于层间连接的通孔结构。同时，第二重分配层122可具有重分配通孔122V，重分配通孔122V穿过第一绝缘层111并连接到第一重分配层121。举例来说，重分配通孔122V可将第二重分配层122电连接到第一重分配层121。
如上所述，在绝缘构件110中设置在与第一表面130A相邻的水平层级上的第一重分配层121可构成平面状导体图案，且在绝缘构件110中设置在不同的水平层级上的第二重分配层122可具有重分配通孔122V，重分配通孔122V用于在邻近的水平层级之间进行连接。
UBM层140可部分地穿过绝缘构件110，且可连接到第一重分配层121。如图2所示，UBM层140可包括UBM焊盘140P及UBM通孔140V，UBM焊盘140P设置在重分配基底130的第一表面130A上，UBM通孔140V穿过基底绝缘层115且连接到第一重分配层121及UBM焊盘140P。举例来说，UBM通孔140V的上表面可与基底绝缘层115的上表面共面，且UBM通孔140V的下表面可处于比基底绝缘层的下表面高的垂直水平层级。此外，UBM焊盘140P的上表面可与基底绝缘层115的下表面相邻，且UBM焊盘140P的下表面可处于比基底绝缘层115的下表面低的垂直水平层级。
在此实施例中，重分配通孔122V及UBM通孔140V可具有在彼此相反的方向上渐缩的形状。
重分配通孔122V可具有在从第二表面130B朝第一表面130A的第一方向1上渐缩的形状。在一些实施例中，当在剖面中观察时，重分配通孔122V的在第一方向1上延伸的侧表面可为平面状表面。重分配通孔122V可具有比上部宽度d1b窄的下部宽度d1a。同时，UBM通孔140V可具有在与第一方向1相反的第二方向2上变窄的形状。在一些实施例中，当在剖面中观察时，UBM通孔140V的在第二方向2上延伸的侧表面可为平面状表面。UBM通孔140V可具有比上部宽度Db宽的下部宽度Da。UBM层140的厚度T可大于重分配层121或122的厚度t。举例来说，UBM层140的厚度T可为约10μm或大于10μm。UBM层140的厚度T可为与UBM通孔140V的上表面共面的垂直水平层级和与UBM焊盘140P的下表面共面的垂直水平层级之间的垂直距离。
在此实施例中，第二重分配层122可被示出为单个层，但是在另一个实施例中，可包括呈多个层的第二重分配层122(参见图12及图13)。
如图2所示，UBM焊盘140P可具有沿着绝缘构件110的位于重分配基底130的第一表面130A上的表面延伸的部分。举例来说，UBM焊盘140P的上表面可面向绝缘构件110的下表面并接触重分配层121的下表面。如上所述，在此实施例中采用的UBM焊盘140P可为并非由基底绝缘层115界定的非焊料掩模界定(non-solder mask defined，NSMD)类型，且可确保热冲击下的板级可靠性。
另外，重分配基底130可包括设置在第二表面130B上的多个接合焊盘125。所述多个接合焊盘125可分别部分地穿过绝缘构件110，且可具有通孔部分125V，通孔部分125V连接到所述多个重分配层中与第二表面130B相邻的第二重分配层122。接合焊盘125的通孔部分125V可以与重分配通孔122V相似的方式具有在从第二表面130B朝第一表面130A的第一方向1上变窄的形状。UBM通孔125V可具有比上部宽度d2b窄的下部宽度d2a。在一些实施例中，当在剖面中观察时，UBM通孔125V的在第一方向1上延伸的侧表面可为平面状表面。
举例来说，接合焊盘可以与重分配层121及122以及重分配通孔122V相似的方式包含铜、镍、不锈钢或铜合金(例如铍铜)。
半导体芯片150可安装在重分配基底130的第二表面130B上。半导体芯片150的接触焊盘150P可分别使用连接凸块B(例如焊料)连接到接合焊盘125。半导体芯片150可电连接到重分配结构120。半导体封装100还可包括底部填充树脂161，底部填充树脂161设置在半导体芯片150的有源表面与重分配基底130的第二表面130B之间。底部填充树脂161可被形成为环绕连接凸块B的侧表面。举例来说，底部填充树脂161可包含环氧树脂。
在重分配基底130的第二表面130B上可形成覆盖半导体芯片150的模制部分165。半导体芯片150的上表面150T可通过模制部分165的上表面暴露出，且可通过半导体芯片150的暴露出的上表面来促进散热。可对模制部分165的上表面进行研磨以暴露出半导体芯片150的上表面150T。半导体芯片150的上表面150T可与模制部分165的上表面实质上共面。举例来说，模制部分165可由含有填料的烃环化合物形成。填料可为例如SiO2填料。在一些实施例中，模制部分165可由味之素积层膜(Ajinomoto Build-up Film，ABF)形成。
可将外部连接件180附装到重分配基底130的UBM层。外部连接件180可为例如焊球或凸块。外部连接件180可电连接半导体封装100与外部器件(例如，母板)。
因此，重分配通孔122V的形成方向可具有与UBM通孔140V的形成方向相反的方向。在重分配层的积层工艺之后，可通过在重分配基底130的积层工艺中使用附加载体引入转移工艺来最终形成相对厚的UBM层140。
这种工艺顺序的修改可大大减小波动问题。具体来说，在使用第一载体执行具有相对薄的厚度的重分配层的积层工艺之后，可在转移到第二载体的转移工艺之后形成具有相对厚的厚度的UBM层。因此，可大大减小波动问题。
图3到图10是示出根据示例性实施例的制造半导体封装的方法的主要工艺的剖视图。
参照图3，可在第一载体210上设置第一重分配层121，且可在第一载体210上形成第一绝缘层111以覆盖第一重分配层121。
可提供第一载体210作为用于构建重分配结构的基底。如上所述，第一重分配层121可包括不具有层间通孔结构的平面状导体图案。第一重分配层121可包含例如铜、镍、不锈钢或铜合金(例如铍铜)。第一绝缘层111可包含树脂(例如环氧树脂或聚酰亚胺树脂)，且可为不含有填料的树脂。举例来说，第一绝缘层111可由感光性绝缘材料形成。
接下来，参照图4，可在第一绝缘层111中形成用于层间连接的第一孔h1。
当第一绝缘层111是感光性绝缘材料时，可以用于光刻工艺的精细节距形成具有微小大小的第一孔h1。举例来说，由于暴露出的面积在第一绝缘层111的厚度方向上逐渐减小，因此第一孔h1可具有随着其水平剖面积减小而变窄的形状。由此，由第一孔h1界定的层间通孔(例如，重分配通孔、UBM通孔)可具有在要形成的方向上逐渐变窄的锥形形状。在另一个实施例中，第一孔h1可通过使用紫外线(Ultraviolet，UV)激光器或准分子激光器的激光钻孔工艺形成。通过激光钻孔工艺形成的孔也可具有在朝下的方向上变窄的形状。
参照图5，可在第一绝缘层111上形成连接到第一重分配层121的第二重分配层122。
此操作可通过镀覆工艺执行。具体来说，第二重分配层122可通过沿着第一绝缘层111的上面形成有第一孔h1的表面形成晶种层、且接着通过使用掩模图案的镀覆工艺(例如，铜镀覆工艺)来形成。举例来说，第二重分配层可通过浸镀工艺、无电镀覆工艺、电镀工艺或其组合形成。第二重分配层122可通过移除掩模图案以使用灰化或剥离工艺移除不期望区域的被镀覆的部分、且接着在移除掩模图案之后，通过使用化学蚀刻工艺移除晶种层的被暴露出的部分来形成。
由于通过此工艺获得的第二重分配层122及重分配通孔122V是通过与上述相同的镀覆工艺形成的，因此第二重分配层122可具有与重分配通孔122V连续集成的结构。本文所用“连续集成的结构”是指不具有不连续的边界表面(例如，晶粒边界)的要连续集成的结构，其中两个组件不是通过不同的工艺形成而简单地接触(不连续)，而是通过相同的工艺由相同的材料形成。举例来说，连续集成的结构可为均质的单块式结构。
在此实施例中，第二重分配层122可被称为连续集成的结构，因为第二重分配层122是通过相同的镀覆工艺与重分配通孔122V一起形成的。同时，第一重分配层121及重分配通孔122V可不被称为连续集成的结构，因为它们是通过不同的工艺形成的，即使在它们连接到彼此时。
参照图6，在形成第二绝缘层112之后，可在第二绝缘层112上形成连接到第二重分配层122的接合焊盘125。
具体来说，此操作可包括形成具有第二孔h2的第二绝缘层112的第一操作以及形成具有通孔部分125V的接合焊盘125的第二操作，通孔部分125V通过第二孔h2连接到第二重分配层122。第一操作可参考图3及图4所述工艺，且第二操作可参考图5所述工艺。
具体来说，第二孔h2也可以与第一孔h1相似的方式具有其水平剖面积在朝下方向上变窄的形状。因此，由第二孔h2界定的接合焊盘125的通孔部分125V可以与重分配通孔122V相似的方式具有在朝下方向上变窄的形状。
参照图7，可在重分配结构(图6所示最终结构)上安装半导体芯片150以形成用于保护半导体芯片150的模制部分165。
可使用连接凸块B(例如焊料)将半导体芯片150的接触焊盘150P分别连接到接合焊盘125。如上所述，半导体芯片150可电连接到重分配结构120。可在半导体芯片150的有源表面与重分配结构的上表面之间形成底部填充树脂161以环绕连接凸块B的侧表面。举例来说，底部填充树脂161可包括环氧树脂。
可形成模制部分165以覆盖半导体芯片150，且可对模制部分165的上表面进行研磨以暴露出半导体芯片150的上表面150T。在图7中，虚线表示半导体芯片150及模制部分165中的每一者的要通过研磨工艺移除的部分。可通过研磨工艺暴露出半导体芯片150的上表面150T以改善散热效果并同时减小半导体封装的厚度。半导体芯片150的上表面150T可与模制部分165的上表面实质上共面。举例来说，模制部分165可由味之素积层膜(ABF)形成。
接下来，参照图8，在将重分配结构转移到第二载体220之后，可移除第一载体210，且可在移除的表面上形成基底绝缘层115。
基底绝缘层115可包含包括树脂(例如环氧树脂或聚酰亚胺树脂)。举例来说，基底绝缘层115可由与第一绝缘层111及第二绝缘层112相同的材料形成。在一些实施例中，基底绝缘层115可为感光性绝缘材料。
参照图9，可在基底绝缘层115中形成开口，在所述开口中暴露出第一重分配层121的一部分，且可形成连接到第一重分配层121的多个UBM层140。举例来说，可在基底绝缘层115中形成开口以暴露出第一重分配层121的上表面的部分，且可形成多个UBM层140以延伸到这些开口中。
UBM层140可包括设置在基底绝缘层115上的UBM焊盘140P以及连接到第一重分配层121的UBM通孔140V。UBM层140可以与第二重分配层122及接合焊盘125相似的方式使用镀覆工艺形成。因此，UBM焊盘140P及UBM通孔140V可形成连续集成的结构。举例来说，UBM层140可为均质的单块式结构。
采用与形成重分配结构120的操作不同的方式，UBM层140可在被转移(垂直反转)到第二载体220的状态下形成，使得UBM通孔140V可具有在与重分配通孔122V的变窄的方向相反的方向上变窄的形状。举例来说，参照图2，UBM通孔140V可具有比上部宽度Db宽的下部宽度Da。UBM层140的厚度可大于第一重分配层121或第二重分配层122的厚度，且举例来说可为约10μm或大于10μm。
接下来，参照图10，可在UBM层140上形成外部连接件180。外部连接件180可为例如焊球或凸块。外部连接件180可电连接半导体封装100与外部器件。
上述工艺可改变成各种形式。举例来说，可在形成UBM层140之后(在图9所示操作之后)执行安装半导体芯片的操作(参见图7)。重分配结构可被示出为两个水平层级的重分配层，且具有重分配通孔的第二重分配层可被示出为单个水平层级，但是可视需要将第二重分配层引入到多个重分配层中。在这种情形中，在形成接合焊盘(图6)的操作之前，可视需要将形成第二重分配层的操作(图3到图5)重复执行许多次。
图11是示出根据示例性实施例的半导体封装的剖视图。
参照图11，根据此示例性实施例的半导体封装100'可被理解为具有与图1及图2所示实施例相似的结构，不同之处在于提供具有不同配置的重分配基底130'且进一步添加钝化层170。因此，除非另外具体地说明，否则可将图1及图2所示实施例的说明与此实施例的说明进行组合。
在此实施例中采用的重分配基底130'可包括三个水平层级的重分配结构120'。绝缘构件110'可包括基底绝缘层115及第一绝缘层111、第二绝缘层112及第三绝缘层113，且还可包括第一重分配层121及两个第二重分配层122a及122b，第一重分配层121及两个第二重分配层122a及122b位于绝缘层115、111、112及113的各别的边界表面上。
采用与先前实施例不同的方式，重分配基底130'可不包括接合焊盘(例如，图1中的接合焊盘125)。具体来说，半导体芯片150与重分配结构120'之间的连接结构可通过在与重分配基底130'的第二表面130B相邻的绝缘层(第三绝缘层113)上形成开口H、并且通过使用连接凸块B直接连接半导体芯片150的接触焊盘150P与第二重分配层122b的被开口H暴露出的部分来制成。
半导体封装100'还可包括设置在重分配基底130'的第一表面130A上的钝化层170。钝化层170可暴露出UBM层140的至少一部分，且在开口UBM层140处可形成外部连接件180。在一些实施例中，绝缘层115、111、112及113与钝化层170可由相同的材料形成。举例来说，绝缘层115、111、112及113以及钝化层170可包含感光性绝缘材料。在一些实施例中，钝化层170可包含与绝缘构件110'不同的绝缘材料。举例来说，绝缘层115、111、112及113可包含感光性绝缘材料，且钝化层170可由含有填料的烃环化合物形成。举例来说，钝化层170可包含ABF。
同样在此实施例中，采用与先前实施例相似的方式，通过在重分配基底130'的积层工艺的后半部分中引入UBM层140，由于UBM层140的厚度而导致的波动问题可大大减小以提高半导体封装的可靠性。
图12是示出根据示例性实施例的半导体封装的剖视图，且图13是图12所示半导体封装的平面图。
参照图12及图13，根据此实施例的半导体封装100”可被理解成具有与图1及图2所示实施例相似的结构，不同之处在于包括多个半导体芯片150A及150B以及散热板195。因此，除非另外具体地说明，否则可将图1及图2所示实施例的说明与此实施例的说明进行组合。
在此实施例中采用的重分配基底可包括三个水平层级的重分配基底130”，此相似于图11所示重分配基底130'，且可包括设置在重分配基底的第一表面上的钝化层170。
在此实施例中，可将第一半导体芯片150A及第二半导体芯片150B安装在重分配基底130”的第二表面130B上。第一半导体芯片及第二半导体芯片的接触焊盘可通过连接凸块分别连接到接合焊盘。可形成覆盖第一半导体芯片150A及第二半导体芯片150B的一部分或全部的模制部分165。模制部分165可包含例如环氧模制化合物。采用与先前实施例相似的方式，模制部分165可与第一半导体芯片150A及第二半导体芯片150B的上表面共面。
根据此实施例的半导体封装100”还可包括依序排列在第一半导体芯片150A及第二半导体芯片150B的上表面上的导热材料层191及散热板195。导热材料层191可设置在散热板195与第一半导体芯片150A及第二半导体芯片150B以及模制部分165之间。导热材料层191可帮助将从第一半导体芯片150A及第二半导体芯片150B产生的热量平稳地排放到散热板195。导热材料层191可由热界面材料(thermal interface material，TIM)制成。举例来说，导热材料层191可由绝缘材料形成，或者可由包括绝缘材料的材料形成且能够维持电绝缘。导热材料层191可包含例如环氧树脂。导热材料层191的具体实例可包含矿物油、油脂、间隙填料油灰、相变凝胶、相变材料垫或填充颗粒的环氧树脂。
散热板195可设置在导热材料层191上。散热板195可为例如散热器、热扩散器、热管或液冷冷板(liquid cooled cold plate)。
图14是示出根据示例性实施例的半导体封装的配置的方块图。
参照图14，半导体封装1000可包括微处理器1010、存储器1020、接口1030、图形处理器(GPU)1040、功能块1050以及连接在它们之间的总线1060。半导体封装1000可包括微处理器1010及图形处理器1040二者，或者可仅包括其中一者。
微处理器1010可包括核心及L2高速缓存。举例来说，微处理器1010可包括多核心。所述多核心中的每一核心可具有相同或不同的性能。此外，所述多核心的核心可同时被激活，或者可在彼此不同的时间被激活。
存储器1020可存储在微处理器1010的控制下在功能块1050中进行处理的结果等。接口1030可与外部器件交换信息及信号。图形处理器1040可执行图形功能。举例来说，图形处理器1040可执行视频编解码或处理三维(three dimensional，3D)图形。功能块1050可执行各种功能。举例来说，当半导体封装1000是移动器件中使用的应用处理器(applicationprocessor，AP)时，功能块1050的一部分可执行通信功能。此处，半导体封装1000可包括图1、图11及图12中所述的半导体封装100、100'及100”中的一者或多者。
根据示例性实施例，通过在重分配基底的积层工艺的后半部分中引入UBM层，由于UBM层140的厚度而导致的波动问题可大大减小以增强半导体封装的可靠性。在一些实施例中，UBM层可以其中焊盘部分不与外绝缘层接触的非焊料掩模界定(NSMD)形式形成。
本发明概念的各种及有利的优点及效果可不限于以上说明，且可在阐述本发明概念的具体实施例的过程中更容易地理解。
尽管以上已示出并阐述了示例性实施例，然而对所属领域中的技术人员应显而易见的是在不背离由随附权利要求书所界定的本发明概念的范围的条件下，可作出修改及变型。

Claims (23)

1.一种半导体封装，包括：
重分配基底，具有被设置成彼此相对的第一表面与第二表面，且包括绝缘构件、多个重分配层及重分配通孔，所述多个重分配层在所述绝缘构件中设置在不同的水平层级上，所述重分配通孔对设置在邻近的水平层级上的所述重分配层进行连接且具有在第一方向上从所述第二表面朝所述第一表面变窄的形状；
多个球下金属层，所述多个球下金属层中的每一者包括球下金属焊盘及球下金属通孔，所述球下金属焊盘设置在所述重分配基底的所述第一表面上，所述球下金属通孔连接到所述多个重分配层中与所述第一表面相邻的重分配层且连接到所述球下金属焊盘，并且所述球下金属通孔具有在与所述第一方向相反的第二方向上变窄的形状；以及
至少一个半导体芯片，设置在所述重分配基底的所述第二表面上，且具有多个接触焊盘，所述多个接触焊盘电连接到所述多个重分配层中与所述第二表面相邻的重分配层。
2.根据权利要求1所述的半导体封装，
其中所述重分配基底还包括设置在所述第二表面上的多个接合焊盘，所述多个接合焊盘中的每一者连接到所述多个接触焊盘中的对应的一者，
其中所述多个接合焊盘中的每一者具有通孔部分，所述通孔部分局部地穿过所述绝缘构件且连接到所述多个重分配层中与所述第二表面相邻的所述重分配层。
3.根据权利要求2所述的半导体封装，其中所述通孔部分具有在所述第一方向上变窄的形状。
4.根据权利要求1所述的半导体封装，其中所述绝缘构件具有多个孔以暴露出与所述第二表面相邻的所述重分配层的部分，且所述多个接触焊盘经由所述多个孔分别连接到与所述第二表面相邻的所述重分配层。
5.根据权利要求1所述的半导体封装，其中所述绝缘构件包含感光性绝缘材料。
6.根据权利要求1所述的半导体封装，其中所述球下金属焊盘具有沿着所述绝缘构件的位于所述重分配基底的所述第一表面上的表面延伸的部分。
7.根据权利要求1所述的半导体封装，还包括：
钝化层，设置在所述重分配基底的所述第一表面上且暴露出所述多个球下金属层的至少部分；以及
多个外部连接件，分别设置在所述多个球下金属层上。
8.根据权利要求7所述的半导体封装，其中所述钝化层包含感光性绝缘材料。
9.根据权利要求7所述的半导体封装，其中所述钝化层包含与所述绝缘构件的材料不同的绝缘材料。
10.根据权利要求1所述的半导体封装，其中所述多个球下金属层中的每一者具有比与所述第一表面相邻的所述重分配层的厚度大的厚度。
11.根据权利要求1所述的半导体封装，还包括：
模制部分，设置在所述重分配基底的所述第二表面上且覆盖所述至少一个半导体芯片。
12.一种半导体封装，包括：
重分配基底，具有被设置成彼此相对的第一表面与第二表面，且包括多个绝缘层及设置在所述多个绝缘层之间的多个重分配层，其中所述多个重分配层包括与所述第一表面相邻的第一重分配层以及设置在所述第一重分配层与所述第二表面之间的至少一个第二重分配层，每一第二重分配层具有重分配通孔，所述重分配通孔连接到所述第一重分配层或所述至少一个第二重分配层中的邻近的第二重分配层；
多个球下金属层，设置在所述重分配基底的所述第一表面上，所述球下金属层中的每一者具有连接到所述第一重分配层的球下金属通孔；
至少一个半导体芯片，设置在所述重分配基底的所述第二表面上，且具有接触焊盘，所述接触焊盘电连接到所述至少一个第二重分配层；以及
模制部分，设置在所述重分配基底的所述第二表面上且覆盖所述至少一个半导体芯片，
其中所述重分配通孔具有在第一方向上从所述第二表面朝所述第一表面变窄的形状，且所述球下金属通孔具有在与所述第一方向相反的第二方向上变窄的形状。
13.根据权利要求12所述的半导体封装，其中所述第二重分配层具有与所述重分配通孔连续集成的结构，且所述球下金属层具有与所述球下金属通孔连续集成的结构。
14.根据权利要求12所述的半导体封装，其中所述球下金属层具有为10μm或大于10μm的厚度。
15.根据权利要求12所述的半导体封装，还包括：
钝化层，设置在所述重分配基底的所述第一表面上且暴露出所述球下金属层的至少部分。
16.根据权利要求15所述的半导体封装，其中所述多个绝缘层中的每一者及所述钝化层包含感光性绝缘材料。
17.根据权利要求12所述的半导体封装，其中所述至少一个半导体芯片的上表面与所述模制部分的上表面共面。
18.根据权利要求17所述的半导体封装，还包括：
散热板，设置在所述至少一个半导体芯片的上表面及所述模制部分的上表面上。
19.根据权利要求12所述的半导体封装，其中所述至少一个半导体芯片包括多个半导体芯片。
20.一种半导体封装，包括：
重分配基底，具有被设置成彼此相对的第一表面与第二表面，且包括绝缘构件及在所述绝缘构件中设置在不同的水平层级上的多个重分配层；
球下金属层，包括球下金属焊盘及球下金属通孔，所述球下金属焊盘设置在所述重分配基底的所述第一表面上，所述球下金属通孔电连接所述球下金属焊盘与所述多个重分配层且具有在从所述第一表面朝所述第二表面的方向上变窄的形状；以及
至少一个半导体芯片，设置在所述重分配基底的所述第二表面上，且具有接触焊盘，所述接触焊盘电连接到所述多个重分配层，
其中所述多个重分配层包括：
第一重分配层，在所述绝缘构件中设置在与所述第一表面相邻的水平层级上，且由平面状导电图案构成，以及
多个第二重分配层，在所述绝缘构件中设置在不同的水平层级上，所述多个第二重分配层中的每一者具有重分配通孔，所述重分配通孔连接到所述第一重分配层或所述多个第二重分配层中的邻近的第二重分配层。
21.根据权利要求20所述的半导体封装，其中所述球下金属层具有与所述球下金属通孔连续集成的结构。
22.根据权利要求20所述的半导体封装，其中所述重分配通孔具有在从所述第二表面朝所述第一表面的方向上变窄的形状。
23.根据权利要求20所述的半导体封装，其中所述第二重分配层具有与所述重分配通孔连续集成的结构，且所述第一重分配层不包括具有连续集成的结构的通孔。
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