CN111341751A - Semiconductor package - Google Patents

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Publication number
CN111341751A
CN111341751A CN201911088966.4A CN201911088966A CN111341751A CN 111341751 A CN111341751 A CN 111341751A CN 201911088966 A CN201911088966 A CN 201911088966A CN 111341751 A CN111341751 A CN 111341751A
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CN
China
Prior art keywords
redistribution
layer
semiconductor package
layers
disposed
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CN201911088966.4A
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Chinese (zh)
Inventor
朴正镐
金钟润
裵珉准
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN111341751A publication Critical patent/CN111341751A/en
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A semiconductor package includes: a redistribution substrate having a first surface and a second surface opposite to each other, and including an insulating member, a plurality of redistribution layers located on different horizontal levels in the insulating member, and redistribution through-holes having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of under-ball metal (UBM) layers each comprising an under-ball metal pad and an under-ball metal via, the under-ball metal pad located on the first surface of the redistribution substrate, the under-ball metal via having a shape that narrows in a second direction opposite the first direction; and at least one semiconductor chip on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer of the plurality of redistribution layers adjacent to the second surface.

Description

Semiconductor package
[ CROSS-REFERENCE TO RELATED APPLICATIONS ]
The present application claims priority of korean patent application No. 10-2018-.
Technical Field
The present inventive concept relates to a semiconductor package. More particularly, the present inventive concept relates to a semiconductor package including a through hole having a tapered shape.
Background
Semiconductor packages can be the result when semiconductor chips (e.g., integrated circuits) are implemented in a form suitable for use in electronic products. With the recent development of the electronics industry, semiconductor packages have been developed in various ways with respect to size reduction, weight reduction, and manufacturing cost reduction.
A Wafer Level Packaging (WLP) process may be provided as a method of manufacturing a semiconductor package. As semiconductor chips become more highly integrated, the sizes of the semiconductor chips are gradually decreasing. However, as semiconductor chips become smaller, it becomes difficult to attach the required number of solder balls, and handling and testing of the solder balls becomes difficult.
In addition, there may be a problem in that the number of boards to be mounted depends on the size of the semiconductor chip. To address this issue, fan-out panel level packaging including redistribution layer (RDL) technology may be used.
Disclosure of Invention
Aspects of the inventive concept may provide a semiconductor package with high reliability by reducing fluctuation caused in a redistribution substrate having a redistribution layer.
According to certain example embodiments, the present disclosure relates to a semiconductor package, comprising: a redistribution substrate having a first surface and a second surface disposed opposite to each other, and including an insulating member, a plurality of redistribution layers disposed on different horizontal levels in the insulating member, and redistribution through holes connecting the redistribution layers disposed on adjacent horizontal levels and having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of Under Ball Metal (UBM) layers, each of the plurality of UBM layers including an under ball metal pad disposed on the first surface of the redistribution substrate and an under ball metal via connected to a redistribution layer of the plurality of redistribution layers adjacent to the first surface and to the UBM layer, and the UBM layers having a shape that narrows in a second direction opposite the first direction; and at least one semiconductor chip disposed on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer of the plurality of redistribution layers adjacent to the second surface.
According to certain example embodiments, the present disclosure relates to a semiconductor package, comprising: a redistribution substrate having a first surface and a second surface disposed opposite to each other and comprising a plurality of insulating layers and a plurality of redistribution layers disposed between the plurality of insulating layers, wherein the plurality of redistribution layers comprises a first redistribution layer adjacent to the first surface and at least one second redistribution layer disposed between the first redistribution layer and the second surface, each second redistribution layer having a redistribution via connected to an adjacent second redistribution layer of the first redistribution layer or the at least one second redistribution layer; a plurality of under-ball metal (UBM) layers disposed on the first surface of the redistribution substrate, each of the under-ball metal layers having an under-ball metal via connected to the first redistribution layer; at least one semiconductor chip disposed on the second surface of the redistribution substrate and having contact pads electrically connected to the at least one second redistribution layer; and a molding portion disposed on the second surface of the redistribution substrate and covering the at least one semiconductor chip, wherein the redistribution via has a shape narrowing from the second surface toward the first surface in a first direction, and the ubm via has a shape narrowing in a second direction opposite to the first direction.
According to certain example embodiments, the present disclosure relates to a semiconductor package, comprising: a redistribution substrate having a first surface and a second surface disposed opposite to each other, and including an insulating member and a plurality of redistribution layers disposed on different horizontal levels in the insulating member; an under-ball metal (UBM) layer including an under-ball metal pad disposed on the first surface of the redistribution substrate and an under-ball metal via electrically connecting the under-ball metal pad with the plurality of redistribution layers and having a shape that narrows in a direction from the first surface toward the second surface; and at least one semiconductor chip disposed on the second surface of the redistribution substrate and having contact pads electrically connected to the plurality of redistribution layers, wherein the plurality of redistribution layers comprises: a first redistribution layer disposed on a horizontal level adjacent to the first surface in the insulating member and composed of a planar conductive pattern, and a plurality of second redistribution layers disposed on different horizontal levels in the insulating member, each of the plurality of second redistribution layers having a redistribution via connected to the first redistribution layer or an adjacent second redistribution layer in the plurality of second redistribution layers.
Drawings
The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description when read in conjunction with the accompanying drawings, in which:
fig. 1 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment.
Fig. 2 is an enlarged cross-sectional view illustrating a portion "a" of the semiconductor package shown in fig. 1.
Fig. 3 to 10 are sectional views illustrating main processes of a method of manufacturing a semiconductor package according to an exemplary embodiment.
Fig. 11 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment.
Fig. 12 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment.
Fig. 13 is a plan view of the semiconductor package shown in fig. 12.
Fig. 14 is a block diagram illustrating a configuration of a semiconductor package according to an exemplary embodiment.
[ description of symbols ]
1: a first direction
2: second direction
100. 100', 100 ", 1000: semiconductor package
110. 110': insulating member
111: insulating layer/first insulating layer
112: insulating layer/second insulating layer
113: insulating layer/third insulating layer
115: insulating layer/base insulating layer
120. 120': redistribution structure
121: redistribution layer/first redistribution layer
122: redistribution layer/second redistribution layer
122a, 122 b: second redistribution layer
122V: redistribution via
125: bonding pad
125V: via portion/UBM via
130. 130', 130 ": redistribution substrate
130A: first surface
130B: second surface
140: under Ball Metal (UBM) layer
140P: UBM pad
140V: UBM vias
150: semiconductor chip
150A: semiconductor chip/first semiconductor chip
150B: semiconductor chip/second semiconductor chip
150P: contact pad
150T: upper surface of
161: underfill resin
165: moulded part
170: passivation layer
180: external connector
191: layer of heat conducting material
195: heat radiation plate
210: first carrier
220: second carrier
1010: microprocessor
1020: memory device
1030: interface
1040: graphics processor
1050: function block
A: in part
B: connecting projection
d1a, d2a, Da: width of lower part
d1b, d2b, Db: upper width
H: opening of the container
h 1: first hole
h 2: second hole
T, T: thickness of
Detailed Description
In the following, various embodiments of the inventive concept will be explained with reference to the drawings.
Fig. 1 is a sectional view illustrating a semiconductor package according to an exemplary embodiment, and fig. 2 is an enlarged sectional view illustrating a portion "a" of the semiconductor package shown in fig. 1.
Referring to fig. 1, a semiconductor package 100 according to an exemplary embodiment may be a semiconductor package in the form of a fan-out wafer level package (FOWLP). The semiconductor package 100 may include a redistribution substrate 130, the redistribution substrate 130 having a first surface 130A and a second surface 130B disposed opposite and facing away from each other. The semiconductor package 100 may further include an Under Ball Metal (UBM) layer 140 disposed on the first surface 130A of the redistribution substrate 130, and a semiconductor chip 150 disposed on the second surface 130B of the redistribution substrate 130.
The semiconductor chip 150 may include a semiconductor substrate having an active surface on which various discrete devices are formed and an inactive surface (inactive surface) opposite the active surface. The semiconductor substrate may be a single semiconductor such as silicon (Si) and germanium (Ge) or a compound semiconductor such as SiC (silicon carbide), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP) or may have a Silicon On Insulator (SOI) structure. For example, the semiconductor substrate constituting the semiconductor chip 150 may include a Buried Oxide (BOX). The various discrete devices may include various microelectronic devices such as metal-oxide-semiconductor field effect transistors (MOSFETs), such as complementary metal-insulator-semiconductor (CMOS) transistors, system Large Scale Integration (LSI), image sensors, such as CMOS Imaging Sensors (CIS), micro-electro-mechanical systems (MEMS), active devices, passive devices, and the like.
The semiconductor chip 150 may include a plurality of contact pads 150P, the plurality of contact pads 150P being electrically connected to discrete devices and disposed on the active surface.
The semiconductor chip 150 may be a memory chip or a logic chip. For example, the memory chip may be a volatile memory chip (such as a Dynamic Random Access Memory (DRAM) or a Static Random Access Memory (SRAM)) or a nonvolatile memory chip (such as a phase-change random access memory (PRAM), a Magnetoresistive Random Access Memory (MRAM), a ferroelectric random access memory (FeRAM), or a Resistive Random Access Memory (RRAM)). In addition, the logic chip may be, for example, a microprocessor, an analog device, or a digital signal processor.
The redistribution substrate 130 may serve as an intermediate layer to package the semiconductor chip 150, thereby mounting the semiconductor chip 150 on a main board. As shown in fig. 1, the redistribution substrate 130 may include an insulating member 110 and redistribution structures 120, the redistribution structures 120 being disposed at different horizontal levels in the insulating member 110. The insulating member 110 may include a plurality of insulating layers 111, 112 and 115, and the redistribution structure 120 may include a plurality of redistribution layers 121 and 122, the plurality of redistribution layers 121 and 122 being disposed on boundary surfaces of the plurality of insulating layers 111, 112 and 115, respectively.
The boundary surfaces of the plurality of insulating layers 111, 112, and 115 may define the formation locations of the redistribution layers 121 and 122, but according to some embodiments (e.g., when the plurality of insulating layers 111, 112, and 115 are formed of the same material), the boundary surfaces of the plurality of insulating layers 111, 112, and 115 may not be directly visually observable in the final structure. A portion of the plurality of redistribution layers 121 and 122 may include a redistribution via 122V connecting the redistribution layers 121 and 122 disposed on adjacent horizontal levels.
In some embodiments, the plurality of insulating layers 111, 112, and 115 may be made of resin (e.g., epoxy or polyimide). For example, the plurality of insulating layers 111, 112, and 115 may be formed of a photosensitive insulating material. Redistribution layers 121 and 122 and redistribution vias 122V may comprise, for example, copper, nickel, stainless steel, or a copper alloy (e.g., beryllium copper).
Specifically, referring to fig. 2, the structure of the redistribution substrate 130 employed in this embodiment will be described in detail. Fig. 2 is an enlarged cross-sectional view illustrating a portion "a" of the semiconductor package shown in fig. 1.
Referring to fig. 2, the plurality of redistribution layers 121 and 122 may include a first redistribution layer 121 and a second redistribution layer 122, the first redistribution layer 121 being disposed between the base insulating layer 115 and the first insulating layer 111, and the second redistribution layer 122 being disposed between the first insulating layer 111 and the second insulating layer 112. For example, the first redistribution layer 121 may be disposed on the base insulating layer 115 and covered by the first insulating layer 111, and the second redistribution layer 122 may be disposed on the first insulating layer 111 and covered by the second insulating layer 112. The first redistribution layer 121 may constitute a planar conductive pattern without a via structure for interlayer connection. Meanwhile, the second redistribution layer 122 may have a redistribution via 122V, the redistribution via 122V passing through the first insulation layer 111 and being connected to the first redistribution layer 121. For example, redistribution via 122V may electrically connect second redistribution layer 122 to first redistribution layer 121.
As described above, the first redistribution layer 121 disposed on a horizontal level adjacent to the first surface 130A in the insulating member 110 may constitute a planar conductor pattern, and the second redistribution layer 122 disposed on a different horizontal level in the insulating member 110 may have the redistribution via 122V for connection between the adjacent horizontal levels.
The UBM layer 140 may partially pass through the insulating member 110 and may be connected to the first redistribution layer 121. As shown in fig. 2, the UBM layer 140 may include a UBM pad 140P disposed on the first surface 130A of the redistribution substrate 130 and a UBM via 140V passing through the substrate insulating layer 115 and connected to the first redistribution layer 121 and the UBM pad 140P. For example, an upper surface of the UBM via 140V may be coplanar with an upper surface of the base insulating layer 115, and a lower surface of the UBM via 140V may be at a higher vertical horizontal level than the lower surface of the base insulating layer. Further, an upper surface of the UBM pad 140P may be adjacent to a lower surface of the base insulating layer 115, and the lower surface of the UBM pad 140P may be at a lower vertical horizontal level than the lower surface of the base insulating layer 115.
In this embodiment, the redistribution via 122V and the UBM via 140V may have shapes that taper in opposite directions to each other.
The redistribution via 122V may have a tapered shape in the first direction 1 from the second surface 130B toward the first surface 130A. In some embodiments, when viewed in cross-section, the side surface of the redistribution via 122V extending in the first direction 1 may be a planar surface. The redistribution via 122V may have a lower width d1a that is narrower than the upper width d1 b. Meanwhile, the UBM via 140V may have a shape narrowed in a second direction 2 opposite to the first direction 1. In some embodiments, a side surface of the UBM via 140V extending in the second direction 2 may be a planar surface when viewed in cross section. The UBM via 140V may have a lower width Da wider than the upper width Db. Thickness T of UBM layer 140 may be greater than thickness T of redistribution layer 121 or 122. For example, the thickness T of the UBM layer 140 may be about 10 μm or greater than 10 μm. The thickness T of the UBM layer 140 may be a vertical distance between a vertical horizontal level coplanar with an upper surface of the UBM via 140V and a vertical horizontal level coplanar with a lower surface of the UBM pad 140P.
In this embodiment, the second redistribution layer 122 may be shown as a single layer, but in another embodiment, the second redistribution layer 122 may be included in multiple layers (see fig. 12 and 13).
As shown in fig. 2, the UBM pad 140P may have a portion extending along a surface of the insulating member 110 on the first surface 130A of the redistribution substrate 130. For example, an upper surface of the UBM pad 140P may face a lower surface of the insulating member 110 and contact a lower surface of the redistribution layer 121. As described above, the UBM pad 140P employed in this embodiment may be of a non-solder mask defined (NSMD) type that is not defined by the base insulating layer 115, and may ensure board-level reliability under thermal shock.
In addition, the redistribution substrate 130 may include a plurality of bonding pads 125 disposed on the second surface 130B. The plurality of bonding pads 125 may partially pass through the insulating member 110, respectively, and may have a via portion 125V connected to the second redistribution layer 122 adjacent to the second surface 130B among the plurality of redistribution layers. The via portion 125V of the bonding pad 125 may have a shape narrowing in the first direction 1 from the second surface 130B toward the first surface 130A in a similar manner to the redistribution via 122V. The UBM via 125V may have a lower width d2a that is narrower than the upper width d2 b. In some embodiments, a side surface of the UBM via 125V extending in the first direction 1 may be a planar surface when viewed in cross section.
For example, the bond pads may comprise copper, nickel, stainless steel, or a copper alloy (e.g., beryllium copper) in a similar manner to redistribution layers 121 and 122 and redistribution vias 122V.
The semiconductor chip 150 may be mounted on the second surface 130B of the redistribution substrate 130. The contact pads 150P of the semiconductor chip 150 may be connected to the bonding pads 125 using connection bumps B (e.g., solder), respectively. The semiconductor chip 150 may be electrically connected to the redistribution structure 120. The semiconductor package 100 may further include an underfill resin 161, the underfill resin 161 being disposed between the active surface of the semiconductor chip 150 and the second surface 130B of the redistribution substrate 130. The underfill resin 161 may be formed to surround the side surfaces of the connection bumps B. For example, the underfill resin 161 may comprise an epoxy resin.
A molding portion 165 covering the semiconductor chip 150 may be formed on the second surface 130B of the redistribution substrate 130. The upper surface 150T of the semiconductor chip 150 may be exposed through the upper surface of the molding portion 165, and heat dissipation may be promoted by the exposed upper surface of the semiconductor chip 150. The upper surface of the molding portion 165 may be ground to expose the upper surface 150T of the semiconductor chip 150. The upper surface 150T of the semiconductor chip 150 may be substantially coplanar with the upper surface of the molding portion 165. For example, mold portion 165 may be formed from a hydrocarbon ring compound containing a filler. The filler may be, for example, SiO2And (4) filling. In some embodiments, the molded portion 165 may be formed of Ajinomoto Build-up Film (ABF).
The external connection member 180 may be attached to the UBM layer of the redistribution substrate 130. The external connections 180 may be, for example, solder balls or bumps. The external connection member 180 may electrically connect the semiconductor package 100 with an external device (e.g., a motherboard).
Accordingly, the formation direction of the redistribution via 122V may have a direction opposite to the formation direction of the UBM via 140V. After the lamination process of the redistribution layer, the relatively thick UBM layer 140 may be finally formed by introducing a transfer process using an additional carrier in the lamination process of the redistribution substrate 130.
This modification of the process sequence can greatly reduce the problem of fluctuations. Specifically, after a build-up process of a redistribution layer having a relatively thin thickness is performed using a first carrier, a UBM layer having a relatively thick thickness may be formed after a transfer process to a second carrier. Thus, the problem of fluctuations can be greatly reduced.
Fig. 3 to 10 are sectional views illustrating main processes of a method of manufacturing a semiconductor package according to an exemplary embodiment.
Referring to fig. 3, a first redistribution layer 121 may be disposed on a first carrier 210, and a first insulating layer 111 may be formed on the first carrier 210 to cover the first redistribution layer 121.
The first carrier 210 may be provided as a base for building the redistribution structure. As described above, the first redistribution layer 121 may include a planar-shaped conductor pattern without an interlayer via structure. First redistribution layer 121 may comprise, for example, copper, nickel, stainless steel, or a copper alloy (e.g., beryllium copper). The first insulating layer 111 may include a resin (e.g., an epoxy resin or a polyimide resin), and may be a resin containing no filler. For example, the first insulating layer 111 may be formed of a photosensitive insulating material.
Next, referring to fig. 4, a first hole h1 for interlayer connection may be formed in the first insulating layer 111.
When the first insulating layer 111 is a photosensitive insulating material, the first hole h1 having a minute size may be formed at a fine pitch for a photolithography process. For example, since the exposed area is gradually reduced in the thickness direction of the first insulating layer 111, the first hole h1 may have a shape that is narrowed as its horizontal sectional area is reduced. Thus, the interlayer via (e.g., redistribution via, UBM via) defined by the first hole h1 may have a tapered shape that gradually narrows in the direction to be formed. In another embodiment, the first hole h1 may be formed by a laser drilling process using an Ultraviolet (UV) laser or an excimer laser. The hole formed by the laser drilling process may also have a shape that narrows in the downward direction.
Referring to fig. 5, a second redistribution layer 122 connected to the first redistribution layer 121 may be formed on the first insulating layer 111.
This operation may be performed by a plating process. Specifically, the second redistribution layer 122 may be formed by forming a seed layer along the surface of the first insulating layer 111 on which the first hole h1 is formed, and then by a plating process (e.g., a copper plating process) using a mask pattern. For example, the second redistribution layer may be formed by an immersion plating process, an electroless plating process, an electroplating process, or a combination thereof. The second redistribution layer 122 may be formed by removing the mask pattern to remove the plated portions of the undesired regions using an ashing or stripping process, and then, after removing the mask pattern, removing the exposed portions of the seed layer using a chemical etching process.
Since the second redistribution layer 122 and the redistribution via 122V obtained by this process are formed by the same plating process as described above, the second redistribution layer 122 may have a structure continuously integrated with the redistribution via 122V. As used herein, "continuously integrated structure" refers to a structure to be continuously integrated that does not have discontinuous boundary surfaces (e.g., grain boundaries), in which two components are not simply in contact (discontinuous) by being formed by different processes, but are formed of the same material by the same process. For example, the continuously integrated structure may be a homogeneous monolithic structure.
In this embodiment, the second redistribution layer 122 may be referred to as a continuously integrated structure because the second redistribution layer 122 is formed with the redistribution via 122V through the same plating process. Meanwhile, the first redistribution layer 121 and the redistribution via 122V may not be referred to as a continuously integrated structure because they are formed through different processes even when they are connected to each other.
Referring to fig. 6, after forming the second insulating layer 112, a bonding pad 125 connected to the second redistribution layer 122 may be formed on the second insulating layer 112.
Specifically, this operation may include a first operation of forming the second insulating layer 112 having the second hole h2 and a second operation of forming the bonding pad 125 having the via portion 125V, the via portion 125V being connected to the second redistribution layer 122 through the second hole h 2. The first operation may refer to the processes described with reference to fig. 3 and 4, and the second operation may refer to the process described with reference to fig. 5.
Specifically, the second hole h2 may also have a shape whose horizontal sectional area narrows in the downward direction in a similar manner to the first hole h 1. Accordingly, the via portion 125V of the bonding pad 125 defined by the second hole h2 may have a shape narrowing in the downward direction in a similar manner to the redistribution via 122V.
Referring to fig. 7, the semiconductor chip 150 may be mounted on the redistribution structure (final structure shown in fig. 6) to form a molding portion 165 for protecting the semiconductor chip 150.
The contact pads 150P of the semiconductor chip 150 may be connected to the bonding pads 125, respectively, using connection bumps B (e.g., solder). As described above, the semiconductor chip 150 may be electrically connected to the redistribution structure 120. An underfill resin 161 may be formed between the active surface of the semiconductor chip 150 and the upper surface of the redistribution structure to surround the side surfaces of the connection bumps B. For example, the underfill resin 161 may comprise an epoxy resin.
The molding portion 165 may be formed to cover the semiconductor chip 150, and the upper surface of the molding portion 165 may be ground to expose the upper surface 150T of the semiconductor chip 150. In fig. 7, the broken line represents a portion of each of the semiconductor chip 150 and the molding portion 165 to be removed by the grinding process. The upper surface 150T of the semiconductor chip 150 may be exposed through a grinding process to improve heat dissipation and simultaneously reduce the thickness of the semiconductor package. The upper surface 150T of the semiconductor chip 150 may be substantially coplanar with the upper surface of the molding portion 165. For example, the molded portion 165 may be formed of an ajinomoto laminated film (ABF).
Next, referring to fig. 8, after transferring the redistribution structure to the second carrier 220, the first carrier 210 may be removed, and the base insulating layer 115 may be formed on the removed surface.
The base insulating layer 115 may include a resin (e.g., an epoxy resin or a polyimide resin). For example, the base insulating layer 115 may be formed of the same material as the first insulating layer 111 and the second insulating layer 112. In some embodiments, the base insulating layer 115 may be a photosensitive insulating material.
Referring to fig. 9, an opening in which a portion of the first redistribution layer 121 is exposed may be formed in the base insulating layer 115, and a plurality of UBM layers 140 connected to the first redistribution layer 121 may be formed. For example, openings may be formed in the base insulating layer 115 to expose portions of the upper surface of the first redistribution layer 121, and a plurality of UBM layers 140 may be formed to extend into these openings.
The UBM layer 140 may include a UBM pad 140P disposed on the base insulating layer 115 and a UBM via 140V connected to the first redistribution layer 121. The UBM layer 140 may be formed using a plating process in a similar manner as the second redistribution layer 122 and the bond pads 125. Accordingly, the UBM pad 140P and the UBM via 140V may form a continuously integrated structure. For example, the UBM layer 140 may be a homogeneous monolithic structure.
In a manner different from the operation of forming the redistribution structure 120, the UBM layer 140 may be formed in a state of being transferred (vertically reversed) to the second carrier 220, so that the UBM via 140V may have a shape that is narrowed in a direction opposite to the direction of narrowing of the redistribution via 122V. For example, referring to fig. 2, the UBM via 140V may have a lower width Da wider than an upper width Db. The thickness of UBM layer 140 may be greater than the thickness of first redistribution layer 121 or second redistribution layer 122, and may be about 10 μm or greater than 10 μm, for example.
Next, referring to fig. 10, an external connection 180 may be formed on the UBM layer 140. The external connections 180 may be, for example, solder balls or bumps. The external connection member 180 may electrically connect the semiconductor package 100 with an external device.
The above-described process may be changed into various forms. For example, the operation of mounting the semiconductor chip (see fig. 7) may be performed after the UBM layer 140 is formed (after the operation shown in fig. 9). The redistribution structure may be shown as two horizontal levels of redistribution layers, and the second redistribution layer with redistribution vias may be shown as a single horizontal level, but the second redistribution layer may be introduced into multiple redistribution layers as desired. In this case, the operation of forming the second redistribution layer (fig. 3 to 5) may be repeated as many times as necessary before the operation of forming the bonding pad (fig. 6).
Fig. 11 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment.
Referring to fig. 11, a semiconductor package 100 'according to this exemplary embodiment may be understood to have a structure similar to that of the embodiment shown in fig. 1 and 2, except that a redistribution substrate 130' having a different configuration is provided and a passivation layer 170 is further added. Thus, the description of the embodiments shown in fig. 1 and 2 can be combined with the description of this embodiment, unless specifically stated otherwise.
The redistribution substrate 130 'employed in this embodiment may include three horizontal levels of redistribution structures 120'. The insulating member 110' may include a base insulating layer 115 and a first insulating layer 111, a second insulating layer 112 and a third insulating layer 113, and may also include a first redistribution layer 121 and two second redistribution layers 122a and 122b, the first redistribution layer 121 and the two second redistribution layers 122a and 122b being located on respective boundary surfaces of the insulating layers 115, 111, 112 and 113.
In a different manner than the previous embodiments, redistribution substrate 130' may not include bond pads (e.g., bond pads 125 in fig. 1). Specifically, the connection structure between the semiconductor chip 150 and the redistribution structure 120 'may be made by forming an opening H on the insulating layer (the third insulating layer 113) adjacent to the second surface 130B of the redistribution substrate 130' and directly connecting the contact pad 150P of the semiconductor chip 150 and a portion of the second redistribution layer 122B exposed by the opening H using the connection bump B.
The semiconductor package 100 'may further include a passivation layer 170 disposed on the first surface 130A of the redistribution substrate 130'. The passivation layer 170 may expose at least a portion of the UBM layer 140, and an external connection 180 may be formed at the opening UBM layer 140. In some embodiments, the insulating layers 115, 111, 112, and 113 and the passivation layer 170 may be formed of the same material. For example, the insulating layers 115, 111, 112, and 113 and the passivation layer 170 may include a photosensitive insulating material. In some embodiments, the passivation layer 170 may include a different insulating material than the insulating member 110'. For example, the insulating layers 115, 111, 112, and 113 may include a photosensitive insulating material, and the passivation layer 170 may be formed of a hydrocarbon ring compound containing a filler. For example, the passivation layer 170 may include ABF.
Also in this embodiment, in a similar manner to the previous embodiment, by introducing the UBM layer 140 in the latter half of the lamination process of the redistribution substrate 130', the problem of fluctuation due to the thickness of the UBM layer 140 can be greatly reduced to improve the reliability of the semiconductor package.
Fig. 12 is a sectional view illustrating a semiconductor package according to an exemplary embodiment, and fig. 13 is a plan view of the semiconductor package shown in fig. 12.
Referring to fig. 12 and 13, the semiconductor package 100 ″ according to this embodiment may be understood to have a structure similar to that of the embodiment shown in fig. 1 and 2, except that it includes a plurality of semiconductor chips 150A and 150B and a heat dissipation plate 195. Thus, the description of the embodiments shown in fig. 1 and 2 can be combined with the description of this embodiment, unless specifically stated otherwise.
The redistribution substrate employed in this embodiment may include three horizontal levels of redistribution substrate 130 ", similar to redistribution substrate 130' shown in fig. 11, and may include a passivation layer 170 disposed on a first surface of the redistribution substrate.
In this embodiment, the first semiconductor chip 150A and the second semiconductor chip 150B may be mounted on the second surface 130B of the redistribution substrate 130 ″. The contact pads of the first semiconductor chip and the second semiconductor chip may be connected to the bonding pads, respectively, by connection bumps. A molding portion 165 covering a part or all of the first semiconductor chip 150A and the second semiconductor chip 150B may be formed. The molding portion 165 may comprise, for example, an epoxy molding compound. In a similar manner to the previous embodiment, the molding portion 165 may be coplanar with the upper surfaces of the first and second semiconductor chips 150A and 150B.
The semiconductor package 100 ″ according to this embodiment may further include a heat conductive material layer 191 and a heat dissipation plate 195 sequentially arranged on the upper surfaces of the first and second semiconductor chips 150A and 150B. The heat conductive material layer 191 may be disposed between the heat dissipation plate 195 and the first and second semiconductor chips 150A and 150B and the molding portion 165. The heat conductive material layer 191 may help smoothly discharge heat generated from the first and second semiconductor chips 150A and 150B to the heat dissipation plate 195. The thermal conductive material layer 191 may be made of Thermal Interface Material (TIM). For example, the thermally conductive material layer 191 may be formed of an insulating material, or may be formed of a material including an insulating material and capable of maintaining electrical insulation. The layer 191 of thermally conductive material may comprise, for example, an epoxy. Specific examples of the thermal conductive material layer 191 may include mineral oil, grease, gap filler putty, phase change gel, a phase change material mat, or a particle-filled epoxy.
The heat dissipation plate 195 may be disposed on the thermally conductive material layer 191. The heat dissipation plate 195 may be, for example, a heat sink, a heat spreader, a heat pipe, or a liquid cooled cold plate (liquid cooled cold plate).
Fig. 14 is a block diagram illustrating a configuration of a semiconductor package according to an exemplary embodiment.
Referring to fig. 14, the semiconductor package 1000 may include a microprocessor 1010, a memory 1020, an interface 1030, a Graphics Processor (GPU)1040, functional blocks 1050, and a bus 1060 connected therebetween. The semiconductor package 1000 may include both the microprocessor 1010 and the graphics processor 1040, or may include only one of them.
Microprocessor 1010 may include a core and an L2 cache. For example, the microprocessor 1010 may include multiple cores. Each of the multiple cores may have the same or different performance. Further, the cores of the multi-core may be activated simultaneously, or may be activated at different times from each other.
The memory 1020 may store the results of processing in function block 1050 under the control of the microprocessor 1010, and the like. The interface 1030 may exchange information and signals with external devices. Graphics processor 1040 may perform graphics functions. For example, graphics processor 1040 may perform video coding or process three-dimensional (3D) graphics. The function block 1050 may perform various functions. For example, when the semiconductor package 1000 is an Application Processor (AP) used in a mobile device, a portion of the functional blocks 1050 may perform communication functions. Here, the semiconductor package 1000 may include one or more of the semiconductor packages 100, 100', and 100 ″ described in fig. 1, 11, and 12.
According to an exemplary embodiment, by introducing the UBM layer in the latter half of the build-up process of redistributing the substrate, the problem of fluctuation due to the thickness of the UBM layer 140 may be greatly reduced to enhance the reliability of the semiconductor package. In some embodiments, the UBM layer may be formed in a non-solder mask defined (NSMD) form in which the solder pad portion is not in contact with the outer insulating layer.
Various and advantageous advantages and effects of the inventive concept may not be limited to the above description, and may be more easily understood in the course of describing specific embodiments of the inventive concept.
While exemplary embodiments have been shown and described above, it should be apparent to those skilled in the art that changes and modifications may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims (23)

1. A semiconductor package, comprising:
a redistribution substrate having a first surface and a second surface disposed opposite to each other, and including an insulating member, a plurality of redistribution layers disposed on different horizontal levels in the insulating member, and redistribution through holes connecting the redistribution layers disposed on adjacent horizontal levels and having a shape narrowing from the second surface toward the first surface in a first direction;
a plurality of under-ball metal layers, each of the plurality of under-ball metal layers including an under-ball metal pad and an under-ball metal via, the under-ball metal pad being disposed on the first surface of the redistribution substrate, the under-ball metal via being connected to a redistribution layer adjacent to the first surface among the plurality of redistribution layers and to the under-ball metal pad, and the under-ball metal via having a shape that narrows in a second direction opposite to the first direction; and
at least one semiconductor chip disposed on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer of the plurality of redistribution layers adjacent to the second surface.
2. The semiconductor package of claim 1, wherein the semiconductor package,
wherein the redistribution substrate further comprises a plurality of bond pads disposed on the second surface, each of the plurality of bond pads connected to a corresponding one of the plurality of contact pads,
wherein each of the plurality of bond pads has a via portion that partially passes through the insulating member and connects to the redistribution layer of the plurality of redistribution layers that is adjacent to the second surface.
3. The semiconductor package according to claim 2, wherein the through-hole portion has a shape that narrows in the first direction.
4. The semiconductor package of claim 1, wherein the insulating member has a plurality of holes to expose portions of the redistribution layer adjacent to the second surface, and the plurality of contact pads are respectively connected to the redistribution layer adjacent to the second surface via the plurality of holes.
5. The semiconductor package of claim 1, wherein the insulating member comprises a photosensitive insulating material.
6. The semiconductor package of claim 1, wherein the under ball metal pad has a portion extending along a surface of the insulating member on the first surface of the redistribution substrate.
7. The semiconductor package of claim 1, further comprising:
a passivation layer disposed on the first surface of the redistribution substrate and exposing at least portions of the plurality of ubm layers; and
and a plurality of external connection members respectively disposed on the plurality of under-ball metal layers.
8. The semiconductor package of claim 7, wherein the passivation layer comprises a photosensitive insulating material.
9. The semiconductor package of claim 7, wherein the passivation layer comprises an insulating material different from a material of the insulating member.
10. The semiconductor package of claim 1, wherein each of the plurality of ubm layers has a thickness greater than a thickness of the redistribution layer adjacent to the first surface.
11. The semiconductor package of claim 1, further comprising:
a molding portion disposed on the second surface of the redistribution substrate and covering the at least one semiconductor chip.
12. A semiconductor package, comprising:
a redistribution substrate having a first surface and a second surface disposed opposite to each other and comprising a plurality of insulating layers and a plurality of redistribution layers disposed between the plurality of insulating layers, wherein the plurality of redistribution layers comprises a first redistribution layer adjacent to the first surface and at least one second redistribution layer disposed between the first redistribution layer and the second surface, each second redistribution layer having a redistribution via connected to an adjacent second redistribution layer of the first redistribution layer or the at least one second redistribution layer;
a plurality of under-ball metal layers disposed on the first surface of the redistribution substrate, each of the under-ball metal layers having an under-ball metal via connected to the first redistribution layer;
at least one semiconductor chip disposed on the second surface of the redistribution substrate and having contact pads electrically connected to the at least one second redistribution layer; and
a molding portion disposed on the second surface of the redistribution substrate and covering the at least one semiconductor chip,
wherein the redistribution via has a shape narrowing in a first direction from the second surface toward the first surface, and the ubm via has a shape narrowing in a second direction opposite to the first direction.
13. The semiconductor package of claim 12, wherein the second redistribution layer has a structure continuously integrated with the redistribution via and the ubm layer has a structure continuously integrated with the ubm via.
14. The semiconductor package of claim 12, wherein the ubm layer has a thickness of 10 μ ι η or greater than 10 μ ι η.
15. The semiconductor package of claim 12, further comprising:
a passivation layer disposed on the first surface of the redistribution substrate and exposing at least a portion of the ubm layer.
16. The semiconductor package of claim 15, wherein each of the plurality of insulating layers and the passivation layer comprise a photosensitive insulating material.
17. The semiconductor package of claim 12, wherein an upper surface of the at least one semiconductor chip is coplanar with an upper surface of the molded portion.
18. The semiconductor package of claim 17, further comprising:
and a heat dissipation plate disposed on an upper surface of the at least one semiconductor chip and an upper surface of the mold part.
19. The semiconductor package of claim 12, wherein the at least one semiconductor chip comprises a plurality of semiconductor chips.
20. A semiconductor package, comprising:
a redistribution substrate having a first surface and a second surface disposed opposite to each other, and including an insulating member and a plurality of redistribution layers disposed on different horizontal levels in the insulating member;
an under-ball metal layer including an under-ball metal pad disposed on the first surface of the redistribution substrate and an under-ball metal via electrically connecting the under-ball metal pad and the plurality of redistribution layers and having a shape narrowing in a direction from the first surface toward the second surface; and
at least one semiconductor chip disposed on the second surface of the redistribution substrate and having contact pads electrically connected to the plurality of redistribution layers,
wherein the plurality of redistribution layers comprises:
a first redistribution layer disposed on a horizontal level adjacent to the first surface in the insulating member and composed of a planar conductive pattern, an
A plurality of second redistribution layers disposed on different horizontal levels in the insulating member, each of the plurality of second redistribution layers having a redistribution via connected to the first redistribution layer or an adjacent second redistribution layer of the plurality of second redistribution layers.
21. The semiconductor package of claim 20, wherein the ubm layer has a structure that is continuously integrated with the ubm via.
22. The semiconductor package of claim 20, wherein the redistribution via has a shape that narrows in a direction from the second surface toward the first surface.
23. The semiconductor package of claim 20, wherein the second redistribution layer has a structure continuously integrated with the redistribution vias, and the first redistribution layer does not include vias having a continuously integrated structure.
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