TWI557819B - Interposer and manufacturing method thereof - Google Patents

Interposer and manufacturing method thereof Download PDF

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TWI557819B
TWI557819B TW103142202A TW103142202A TWI557819B TW I557819 B TWI557819 B TW I557819B TW 103142202 A TW103142202 A TW 103142202A TW 103142202 A TW103142202 A TW 103142202A TW I557819 B TWI557819 B TW I557819B
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layer
blind
conductive seed
forming
dielectric layer
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TW201622026A (en
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曾子章
譚瑞敏
胡迪群
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欣興電子股份有限公司
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Description

中介板及其製造方法 Intermediary board and manufacturing method thereof

本發明是有關於一種中介板及其製造方法。 The present invention relates to an interposer and a method of manufacturing the same.

覆晶接合技術是一種晶片封裝技術,其經常應用於晶片與封裝載板(Substrate)之間的接合。具體而言,晶片的主動面可經由多個焊錫凸塊連接至封裝載板的頂面。接著,封裝載板的底面則可經由導電球連接至印刷線路板(PCB)。 The flip chip bonding technique is a chip packaging technique that is often applied to the bonding between a wafer and a package carrier. In particular, the active face of the wafer can be connected to the top surface of the package carrier via a plurality of solder bumps. Then, the bottom surface of the package carrier can be connected to the printed wiring board (PCB) via the conductive balls.

然而,晶片的接點密度增加的速度逐漸大於封裝載板的接點密度增加的速度,這使得晶片的接點密度與封裝載板的接點密度之間存在落差。為了緩衝這樣的落差,中介板便發展出來。中介板是配置在晶片與封裝載板或電路板之間的訊號傳輸媒介。對於中介板而言,導通孔及細線路的製作都面臨挑戰。 However, the junction density of the wafer increases at a faster rate than the junction density of the package carrier, which causes a drop in the junction density of the wafer and the junction density of the package carrier. In order to buffer such a gap, the interposer has developed. The interposer is a signal transmission medium disposed between the wafer and the package carrier or circuit board. For the interposer, the fabrication of vias and thin lines is challenging.

中介板結構之材質可以為有機聚合物、矽、玻璃或陶瓷。為了進一步改善中介板結構的各項特性,相關領域莫不費盡心思開發。如何能提供一種具有較佳特性的中介 板結構,實屬當前重要研發課題之一,亦成為當前相關領域亟需改進的目標。 The material of the interposer structure may be organic polymer, germanium, glass or ceramic. In order to further improve the various characteristics of the interposer structure, the related fields are not intensively developed. How can we provide an intermediary with better characteristics? The plate structure is one of the most important research and development topics at present, and it has become an urgent target for improvement in related fields.

本發明提供一種中介板的製造方法,用以解決在使用二次雷射燒蝕製程製作導通孔時容易在導通孔之頸部殘留介電層的問題。 The invention provides a method for manufacturing an interposer, which solves the problem that a dielectric layer is easily left in the neck of the via hole when the via hole is formed by using the second laser ablation process.

根據本發明一實施方式,一種中介板的製造方法,包含以下步驟。首先,形成第一盲孔於介電層之第一面上,再形成第一導電晶種層於第一盲孔中。接著,形成第二盲孔於介電層之相對於第一面的第二面,其中第一盲孔與第二盲孔相對,且第二盲孔裸露第一導電晶種層。然後,形成第二導電晶種層於第二盲孔中,且與第一導電晶種層接觸。最後,分別形成第一導體層與第二導體層填補第一盲孔與第二盲孔,以形成導體柱於介電層中。 According to an embodiment of the present invention, a method of manufacturing an interposer includes the following steps. First, a first blind via is formed on the first surface of the dielectric layer, and a first conductive seed layer is formed in the first blind via. Next, a second blind via is formed on the second side of the dielectric layer opposite to the first side, wherein the first blind via is opposite the second blind via and the second blind via exposes the first conductive seed layer. Then, a second conductive seed layer is formed in the second blind via and in contact with the first conductive seed layer. Finally, the first conductor layer and the second conductor layer are respectively formed to fill the first blind hole and the second blind hole to form a conductor pillar in the dielectric layer.

根據本發明另一實施方式,一種中介板的製造方法,包含以下步驟。首先,形成第一盲孔於介電層之第一面上,形成第一導電晶種層於第一盲孔中。接著,形成第一導體層填補第一盲孔。接著,形成第二盲孔於介面層之相對於第一面的第二面,其中第一盲孔與第二盲孔相對,且第二盲孔裸露第一導電晶種層。然後,形成第二導電晶種層於第二盲孔中,且與第一導電晶種層接觸。最後,形成第二導體層填補第二盲孔中,以形成導體柱於介電層中。 According to another embodiment of the present invention, a method of manufacturing an interposer includes the following steps. First, a first blind via is formed on the first side of the dielectric layer to form a first conductive seed layer in the first blind via. Next, a first conductor layer is formed to fill the first blind via. Next, a second blind via is formed on the second side of the interface layer opposite to the first side, wherein the first blind via is opposite the second blind via, and the second blind via exposes the first conductive seed layer. Then, a second conductive seed layer is formed in the second blind via and in contact with the first conductive seed layer. Finally, a second conductor layer is formed to fill the second blind via to form a conductor pillar in the dielectric layer.

根據本發明又一實施方式,一種中介板的製造方 法,包含以下步驟。首先,提供基材,基材包含支承基板與設置於支承基板上的介電層。形成第一盲孔於介電層之第一面上,再形成第一導電晶種層於第一盲孔中。接著,分離介電層與支承基板,並將介電層倒置於支承基板上。然後,形成第二盲孔於介面層之相對於第一面的第二面,其中第一盲孔與第二盲孔相對,且第二盲孔裸露第一導電晶種層。接著,形成第二導電晶種層於第二盲孔中,且接觸第一導電晶種層。最後,移除支承基板,形成第一導體層填補第一盲孔,以及形成第二導體層填補第二盲孔,以形成導體柱於介電層中。 According to still another embodiment of the present invention, a manufacturer of an interposer The method contains the following steps. First, a substrate is provided, the substrate comprising a support substrate and a dielectric layer disposed on the support substrate. Forming a first blind via on the first side of the dielectric layer, and forming a first conductive seed layer in the first blind via. Next, the dielectric layer and the support substrate are separated, and the dielectric layer is placed on the support substrate. Then, a second blind hole is formed on the second surface of the interface layer opposite to the first surface, wherein the first blind hole is opposite to the second blind hole, and the second blind hole exposes the first conductive seed layer. Next, a second conductive seed layer is formed in the second blind via and contacts the first conductive seed layer. Finally, the support substrate is removed, a first conductor layer is formed to fill the first blind via, and a second conductor layer is formed to fill the second blind via to form a conductor pillar in the dielectric layer.

根據本發明再一實施方式,一種中介板的製造方法,包含以下步驟。首先,提供基材,基材包含支承基板與設置於支承基板上的介電層。形成第一盲孔於介電層之第一面上,並形成第一導電晶種層於第一盲孔中,再形成第一導體層填補第一盲孔。接著,分離介電層與支承基板,並將介電層倒置於支承基板上。然後,形成第二盲孔於介面層之相對於第一面的第二面,其中第一盲孔與第二盲孔相對,且第二盲孔裸露第一導電晶種層。接著,形成第二導電晶種層於第二盲孔中,且與第一導電晶種層接觸。最後,形成第二導體層填補第二盲孔,以形成導體柱於介電層中。 According to still another embodiment of the present invention, a method of manufacturing an interposer includes the following steps. First, a substrate is provided, the substrate comprising a support substrate and a dielectric layer disposed on the support substrate. Forming a first blind via on the first side of the dielectric layer, and forming a first conductive seed layer in the first blind via, and forming a first conductive layer to fill the first blind via. Next, the dielectric layer and the support substrate are separated, and the dielectric layer is placed on the support substrate. Then, a second blind hole is formed on the second surface of the interface layer opposite to the first surface, wherein the first blind hole is opposite to the second blind hole, and the second blind hole exposes the first conductive seed layer. Next, a second conductive seed layer is formed in the second blind via and in contact with the first conductive seed layer. Finally, a second conductor layer is formed to fill the second blind via to form a conductor pillar in the dielectric layer.

於本發明之一或多個實施方式中,位於第一盲孔之底部之第一導電晶種層的厚度大於第一導電晶晶種層之其他部份的厚度。 In one or more embodiments of the present invention, the thickness of the first conductive seed layer at the bottom of the first blind via is greater than the thickness of other portions of the first conductive crystal seed layer.

於本發明之一或多個實施方式中,第一盲孔與第二盲孔的形成方法為雷射燒蝕或經曝光顯影改變材質後再經化學藥液蝕刻成形,其中曝光的光源可為雷射光源。 In one or more embodiments of the present invention, the first blind via and the second blind via are formed by laser ablation or by exposure and development, and then chemically etched, wherein the exposed light source can be Laser source.

於本發明之一或多個實施方式中,介電層之材質為玻璃。 In one or more embodiments of the present invention, the dielectric layer is made of glass.

根據本發明再一實施方式,一種中介板,包含介電層、第一導體層、第二導體層以及導電晶種層。介電層具有導通孔。第一導體層設置於導通孔之上半部份中。第二導體層設置於導通孔之下半部份中。導電晶種層設置於介電層、第一導體層以及第二導體層之間。 According to still another embodiment of the present invention, an interposer includes a dielectric layer, a first conductor layer, a second conductor layer, and a conductive seed layer. The dielectric layer has via holes. The first conductor layer is disposed in the upper half of the via hole. The second conductor layer is disposed in the lower half of the via hole. The conductive seed layer is disposed between the dielectric layer, the first conductor layer, and the second conductor layer.

於本發明之一或多個實施方式中,位於第一導體層與第二導體層之間的導電晶種層的厚度大於導電晶種層之其他部份的厚度。 In one or more embodiments of the present invention, the thickness of the conductive seed layer between the first conductor layer and the second conductor layer is greater than the thickness of other portions of the conductive seed layer.

本發明上述實施方式藉由先形成第一導電晶種層於第一盲孔中,再使用雷射燒蝕介電層而形成與第一盲孔對向之第二盲孔,因為第一導電晶種層可以作為雷射燒蝕製程的阻擋層,所以不用擔心雷射可能穿透介電層,因此雷射強度可以調強,第一盲孔與第二盲孔所形成之導通孔也就不會有介電層殘留於其頸部的問題。 The above embodiment of the present invention forms a first conductive seed layer in the first blind via, and then uses a laser ablation dielectric layer to form a second blind via opposite the first blind via because the first conductive The seed layer can be used as a barrier layer for the laser ablation process, so there is no need to worry that the laser may penetrate the dielectric layer, so the laser intensity can be adjusted, and the via holes formed by the first blind hole and the second blind hole are also There is no problem with the dielectric layer remaining on its neck.

100‧‧‧基材 100‧‧‧Substrate

110‧‧‧支承基板 110‧‧‧Support substrate

120、140‧‧‧介電層 120, 140‧‧‧ dielectric layer

121、141‧‧‧第一面 121, 141‧‧‧ first side

122、142‧‧‧第二面 122, 142‧‧‧ second side

123、143、126、146‧‧‧盲孔 123, 143, 126, 146‧‧ ‧ blind holes

124、144、127、147‧‧‧外端 124, 144, 127, 147‧ ‧ outside

125、145、128、148‧‧‧內端 125, 145, 128, 148‧ ‧ inner end

129‧‧‧導通孔 129‧‧‧through holes

151、153、155、157、159‧‧‧導電晶種層 151, 153, 155, 157, 159‧‧‧ conductive seed layer

161、163、165、167‧‧‧導體層 161, 163, 165, 167‧‧‧ conductor layers

200、202‧‧‧導體柱 200, 202‧‧‧ conductor column

D1、D2‧‧‧內端孔徑 D1, D2‧‧‧ inner end aperture

300‧‧‧中介板 300‧‧‧Intermediary board

第1A圖至第1J圖繪示依照本發明一實施方式之中介板的製程各步驟的剖面圖。 1A to 1J are cross-sectional views showing respective steps of a process of an interposer according to an embodiment of the present invention.

第1J’圖繪示依照本發明另一實施方式之中介板的剖面圖。 1J' is a cross-sectional view showing an interposer according to another embodiment of the present invention.

第2A圖至第2E圖繪示依照本發明又一實施方式之中介板的製程各步驟的剖面圖。 2A to 2E are cross-sectional views showing respective steps of a process of an interposer according to still another embodiment of the present invention.

以下將以圖式揭露本發明之複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。 The embodiments of the present invention are disclosed in the following drawings, and the details of However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.

為了滿足半導體元件高積集度(Integration)以及微型化(Miniaturization)的要求,中介板(Interposer)結構的間距(Pitch)要求亦越來越小,然而這可能會造成中介板結構製程上的困難。本發明不同實施方式提供一種中介板結構的製造方法,以解決相關問題。 In order to meet the requirements of high integration and miniaturization of semiconductor components, the pitch of the interposer structure is also smaller and smaller, but this may cause difficulties in the process of the interposer structure. . Different embodiments of the present invention provide a method of fabricating an interposer structure to solve related problems.

第1A圖至第1J圖繪示依照本發明一實施方式之中介板的製程各步驟的剖面圖。 1A to 1J are cross-sectional views showing respective steps of a process of an interposer according to an embodiment of the present invention.

如第1A圖所繪示,首先提供基材100,其中基材100包含支承基板110與設置於支承基板110之兩側的介電層120、140。 As shown in FIG. 1A, a substrate 100 is first provided, wherein the substrate 100 includes a support substrate 110 and dielectric layers 120, 140 disposed on both sides of the support substrate 110.

具體而言,介電層120、140之材質為玻璃。應了解到,以上所舉之介電層120、140之材質僅為例示,並非 用以限制本發明,本發明所屬技術領域中具有通常知識者,應視實際需要,彈性選擇介電層120、140之材質。 Specifically, the material of the dielectric layers 120 and 140 is glass. It should be understood that the materials of the dielectric layers 120 and 140 mentioned above are merely examples, not To limit the present invention, those having ordinary knowledge in the technical field of the present invention should flexibly select the materials of the dielectric layers 120 and 140 according to actual needs.

如第1B圖所繪示,分別形成盲孔123、143於介電層120之第一面121上與介電層140之第一面141上。盲孔123、143分別具有兩端,即外端124、144與內端125、145。 As shown in FIG. 1B, blind vias 123, 143 are formed on the first side 121 of the dielectric layer 120 and the first side 141 of the dielectric layer 140, respectively. The blind holes 123, 143 have two ends, namely an outer end 124, 144 and an inner end 125, 145.

具體而言,盲孔123、143的形成方法為雷射燒蝕。此外,盲孔123、143之孔徑大小會由外端124、144向內端125、145遞減。 Specifically, the method of forming the blind vias 123, 143 is laser ablation. In addition, the aperture sizes of the blind holes 123, 143 are reduced by the outer ends 124, 144 toward the inner ends 125, 145.

如第1C圖所繪示,分別形成導電晶種層151、153於介電層120之第一面121上與介電層140之第一面141上,也就是分別形成導電晶種層151、153於盲孔123、143中。 As shown in FIG. 1C, the conductive seed layers 151 and 153 are formed on the first surface 121 of the dielectric layer 120 and the first surface 141 of the dielectric layer 140, that is, the conductive seed layer 151 is formed respectively. 153 is in the blind holes 123, 143.

具體而言,導電晶種層151、153之材質可為金屬比如銅或鈦。導電晶種層151、153的形成方法可為化鍍如無電電鍍(Electoless plating)或化學氣相沉積(CVD)、物理氣相沉積(PVD)如濺鍍或蒸鍍等。 Specifically, the material of the conductive seed layers 151, 153 may be a metal such as copper or titanium. The method of forming the conductive seed layers 151, 153 may be a plating such as electroless plating or chemical vapor deposition (CVD), physical vapor deposition (PVD) such as sputtering or evaporation.

如第1D圖與第1E圖所繪示,分離介電層120、140與支承基板110,並分別將介電層120、140翻轉180°後再設置於支承基板110之兩側。 As shown in FIG. 1D and FIG. 1E , the dielectric layers 120 and 140 and the support substrate 110 are separated, and the dielectric layers 120 and 140 are respectively flipped by 180° and then disposed on both sides of the support substrate 110 .

如第1F圖所繪示,分別形成盲孔126、146於介電層120之相對於第一面121、141的第二面122、142。盲孔126與盲孔123相對,且盲孔126裸露導電晶種層151。盲孔146與盲孔143相對,且盲孔146裸露導電晶種層153。 盲孔126、146分別具有兩端,即外端127、147與內端128、148。 As shown in FIG. 1F, blind holes 126, 146 are formed in the second faces 122, 142 of the dielectric layer 120 with respect to the first faces 121, 141, respectively. The blind via 126 is opposite the blind via 123, and the blind via 126 exposes the conductive seed layer 151. The blind via 146 is opposite the blind via 143 and the blind via 146 exposes the conductive seed layer 153. The blind holes 126, 146 have respective ends, namely outer ends 127, 147 and inner ends 128, 148.

具體而言,盲孔126、146的形成方法為雷射燒蝕,因此盲孔126、146之孔徑大小會由外端127、147向內端128、148遞減。 Specifically, the blind holes 126, 146 are formed by laser ablation, so the aperture sizes of the blind holes 126, 146 are reduced by the outer ends 127, 147 toward the inner ends 128, 148.

如第1G圖所繪示,分別形成導電晶種層155、157於介電層120之第二面122上與介電層140之第二面142上,也就是分別形成導電晶種層155、157於盲孔126、146中。位於盲孔126之內端128的導電晶種層155接觸位於盲孔123之內端125的導電晶種層151,位於盲孔146之內端148的導電晶種層157接觸位於盲孔143之內端145的導電晶種層153。 As shown in FIG. 1G, the conductive seed layers 155, 157 are formed on the second surface 122 of the dielectric layer 120 and the second surface 142 of the dielectric layer 140, that is, the conductive seed layer 155 is formed, respectively. 157 is in the blind holes 126, 146. The conductive seed layer 155 at the inner end 128 of the blind via 126 contacts the conductive seed layer 151 at the inner end 125 of the blind via 123, and the conductive seed layer 157 at the inner end 148 of the blind via 146 contacts the blind via 143. Conductive seed layer 153 of inner end 145.

具體而言,導電晶種層155、157之材質可為金屬比如銅或鈦。導電晶種層155、157的形成方法可為化鍍如無電電鍍(Electoless plating)或化學氣相沉積(CVD)、物理氣相沉積(PVD)如濺鍍或蒸鍍等。 Specifically, the material of the conductive seed layers 155, 157 may be a metal such as copper or titanium. The method of forming the conductive seed layers 155, 157 may be a plating such as electroless plating or chemical vapor deposition (CVD), physical vapor deposition (PVD) such as sputtering or evaporation.

如第1H圖所繪示,分離介電層120、140與支承基板110,並移除支承基板110。 As shown in FIG. 1H, the dielectric layers 120, 140 and the support substrate 110 are separated, and the support substrate 110 is removed.

如第1I圖所繪示,以介電層120為例,接著為形成導體層163於導電晶種層155上,以及形成導體層161於導電晶種層151下方,也就是分別形成導體層161、163填補盲孔123、126。(此處僅描述介電層120與其相關製程,介電層140的相關製程與此處與以下描述類似)。 As shown in FIG. 1I, the dielectric layer 120 is taken as an example, followed by forming the conductor layer 163 on the conductive seed layer 155, and forming the conductor layer 161 under the conductive seed layer 151, that is, forming the conductor layer 161, respectively. 163 fills the blind holes 123, 126. (Only the dielectric layer 120 and its associated processes are described herein, and the associated process of the dielectric layer 140 is similar to that described below).

具體而言,導體層161、163之材質可為金屬比如 銅。導體層161、163的形成方法可為電鍍。 Specifically, the material of the conductor layers 161 and 163 may be a metal such as copper. The method of forming the conductor layers 161, 163 may be electroplating.

如第1I圖與第1J圖所繪示,移除位於盲孔123、126之外的導電晶種層151、155與導體層161、163。於是,形成由導電晶種層151、155與導體層161、163所組成的導體柱200於介電層120中,且介電層120之兩側僅有導體柱200之裸露部份為導體。 As shown in FIGS. 1I and 1J, the conductive seed layers 151, 155 and the conductor layers 161, 163 outside the blind vias 123, 126 are removed. Thus, the conductor post 200 composed of the conductive seed layers 151, 155 and the conductor layers 161, 163 is formed in the dielectric layer 120, and only the exposed portions of the conductor posts 200 on both sides of the dielectric layer 120 are conductors.

在製作中介板結構時,可能會以使用雷射分別燒蝕介電層之兩側的方式形成導通孔,為了避免雷射穿透介電層進而損害支承基板,通常雷射的強度必須控制而不能太強,然而如此可能造成位於導通孔之頸部的介電層沒有燒蝕乾淨,因而影響導體柱的製作與導通品質。為此,如第1C圖所繪示,在形成盲孔123、143之後,先形成導電晶種層151、153於盲孔123、143中,再如第1F圖所繪示,使用雷射燒蝕介電層120、140而形成盲孔126、146,因為導電晶種層151、153可以作為阻擋層,所以不用擔心雷射可能穿透介電層120、140,因此雷射強度可以調強,導通孔(即盲孔123、126之組合與盲孔143、146之組合)也就不會有介電層120、140殘留於其頸部。 When fabricating the interposer structure, the via holes may be formed by ablation of the sides of the dielectric layer by using lasers. In order to prevent the laser from penetrating the dielectric layer and thereby damaging the support substrate, the intensity of the laser must be controlled. It should not be too strong, but this may cause the dielectric layer located at the neck of the via hole to be ablated, thus affecting the fabrication and conduction quality of the conductor post. Therefore, as shown in FIG. 1C, after the blind vias 123 and 143 are formed, the conductive seed layers 151 and 153 are formed in the blind vias 123 and 143, and as shown in FIG. 1F, the laser is used. The dielectric layers 120, 140 are etched to form the blind vias 126, 146. Since the conductive seed layers 151, 153 can serve as a barrier layer, there is no fear that the laser may penetrate the dielectric layers 120, 140, so the laser intensity can be adjusted. The via holes (i.e., the combination of the blind vias 123, 126 and the blind vias 143, 146) will not have the dielectric layers 120, 140 remaining in the neck.

如第1C圖所繪示,位於盲孔123、143之底部之導電晶種層151、153的厚度可大於導電晶種層151、153之其他部份的厚度。如此一來,如第1F圖所繪示,在使用雷射燒蝕介電層120、140而形成盲孔126、146時,位於盲孔123、143之底部之導電晶種層151、153可以有效地阻擋雷射,因而避免雷射穿透介電層120、140。 As shown in FIG. 1C, the thickness of the conductive seed layers 151, 153 at the bottom of the blind vias 123, 143 may be greater than the thickness of other portions of the conductive seed layers 151, 153. As such, as shown in FIG. 1F, when the blind holes 126, 146 are formed by laser ablation of the dielectric layers 120, 140, the conductive seed layers 151, 153 at the bottom of the blind vias 123, 143 may be The laser is effectively blocked, thereby preventing the laser from penetrating through the dielectric layers 120, 140.

第1J’圖繪示依照本發明另一實施方式之中介板300的剖面圖。如第1J’圖所繪示,盲孔123具有內端孔徑D1,盲孔126具有內端孔徑D2,內端孔徑D1大於內端孔徑D2。由於在使用雷射分別燒蝕介電層120之兩側時,盲孔126可能無法完全對準盲孔123,為了避免因為盲孔126沒有對準盲孔123而影響導體柱200的製作與導通品質,盲孔123的內端孔徑D1稍微大於盲孔126的內端孔徑D2。於是,即使盲孔123、126的設置位置有些微誤差,仍然不會影響導體柱200的製作與導通品質。 1J' is a cross-sectional view of the interposer 300 in accordance with another embodiment of the present invention. As shown in FIG. 1J', the blind hole 123 has an inner end aperture D1, and the blind hole 126 has an inner end aperture D2, and the inner end aperture D1 is larger than the inner end aperture D2. Since the blind holes 126 may not be completely aligned with the blind holes 123 when the lasers are respectively ablated on both sides of the dielectric layer 120, in order to avoid that the blind holes 126 are not aligned with the blind holes 123, the fabrication and conduction of the conductor posts 200 are affected. The inner end aperture D1 of the blind hole 123 is slightly larger than the inner end aperture D2 of the blind hole 126. Therefore, even if the arrangement positions of the blind holes 123, 126 are slightly inaccurate, the fabrication and conduction quality of the conductor post 200 are not affected.

第2A圖至第2E圖繪示依照本發明又一實施方式之中介板的製程各步驟的剖面圖。本實施方式與前述實施方式類似,以下主要描述其相異處。 2A to 2E are cross-sectional views showing respective steps of a process of an interposer according to still another embodiment of the present invention. This embodiment is similar to the foregoing embodiment, and the differences are mainly described below.

如第2A圖所繪示,首先提供如第1C圖所繪示的基材100,接著形成導體層161於導電晶種層151上,並形成導體層165於導電晶種層153下方,也就是分別形成導體層161、165填補盲孔123、143。 As shown in FIG. 2A, the substrate 100 as shown in FIG. 1C is first provided, then the conductor layer 161 is formed on the conductive seed layer 151, and the conductor layer 165 is formed under the conductive seed layer 153, that is, The conductor layers 161 and 165 are formed to fill the blind holes 123 and 143, respectively.

具體而言,導體層161、165之材質可為金屬比如銅。導體層161、165的形成方法可為電鍍。 Specifically, the material of the conductor layers 161 and 165 may be a metal such as copper. The method of forming the conductor layers 161, 165 may be electroplating.

如第2B圖與第2C圖所繪示,分離介電層120、140與支承基板110,並分別將介電層120和導體層161與介電層140和導體層165翻轉180°後再設置於支承基板110之兩側。 As shown in FIG. 2B and FIG. 2C, the dielectric layers 120, 140 and the support substrate 110 are separated, and the dielectric layer 120 and the conductor layer 161 and the dielectric layer 140 and the conductor layer 165 are respectively flipped by 180°, and then set. On both sides of the support substrate 110.

如第2D圖所繪示,分別形成盲孔126、146於介電層120之相對於第一面121、141的第二面122、142。盲孔 126與盲孔123相對,且盲孔126裸露導電晶種層151。盲孔146與盲孔143相對,且盲孔146裸露導電晶種層153。盲孔126、146分別具有兩端,即外端127、147與內端128、148。 As shown in FIG. 2D, blind holes 126, 146 are formed in the second faces 122, 142 of the dielectric layer 120 with respect to the first faces 121, 141, respectively. Blind hole 126 is opposite to the blind via 123, and the blind via 126 exposes the conductive seed layer 151. The blind via 146 is opposite the blind via 143 and the blind via 146 exposes the conductive seed layer 153. The blind holes 126, 146 have respective ends, namely outer ends 127, 147 and inner ends 128, 148.

如第2E圖所繪示,分別形成導電晶種層155、157於介電層120之第二面122上與介電層140之第二面142上,也就是分別形成導電晶種層155、157於盲孔126、146中。位於盲孔126之內端128的導電晶種層155接觸位於盲孔123之內端125的導電晶種層151,位於盲孔146之內端148的導電晶種層157接觸位於盲孔143之內端145的導電晶種層153。 As shown in FIG. 2E, conductive seed layers 155, 157 are formed on the second surface 122 of the dielectric layer 120 and the second surface 142 of the dielectric layer 140, that is, the conductive seed layer 155 is formed, 157 is in the blind holes 126, 146. The conductive seed layer 155 at the inner end 128 of the blind via 126 contacts the conductive seed layer 151 at the inner end 125 of the blind via 123, and the conductive seed layer 157 at the inner end 148 of the blind via 146 contacts the blind via 143. Conductive seed layer 153 of inner end 145.

接著,形成導體層163於導電晶種層155上,以及形成導體層167於導電晶種層157上,也就是分別形成導體層163、167填補盲孔126、146。於是,分別形成導體柱200、202於介電層120、140中。 Next, a conductor layer 163 is formed on the conductive seed layer 155, and a conductor layer 167 is formed on the conductive seed layer 157, that is, the conductor layers 163, 167 are formed to fill the blind vias 126, 146, respectively. Thus, conductor posts 200, 202 are formed in dielectric layers 120, 140, respectively.

接下來的製程便與第1H圖至第1J圖類似,即分離導體層161、165與支承基板110,並移除支承基板110,再移除位於盲孔123、126外的導電晶種層151、155與導體層161、163,以及移除位於盲孔143、146外的導電晶種層153、157與導體層165、167。 The subsequent process is similar to the 1H to 1J, that is, the conductor layers 161, 165 and the support substrate 110 are separated, and the support substrate 110 is removed, and the conductive seed layer 151 outside the blind holes 123, 126 is removed. , 155 and conductor layers 161, 163, and the conductive seed layers 153, 157 and conductor layers 165, 167 located outside the blind vias 143, 146.

本實施方式與前述實施方式的主要差異在於,前述實施方式僅進行一次電鍍製程以形成導體層,本實施方式則進行兩次電鍍製程以形成導體層。另外,如第2D圖所繪示,本實施方式因為先形成導體層161、165才形成盲孔 126、146,所以導體層161、165亦有阻擋層的功用,因而更不用擔心雷射可能穿透介電層120、140,位於盲孔123、143之底部的導電晶種層151、153也不用特別加厚。 The main difference between this embodiment and the foregoing embodiment is that the foregoing embodiment performs only one electroplating process to form a conductor layer, and in the present embodiment, two electroplating processes are performed to form a conductor layer. In addition, as shown in FIG. 2D, the present embodiment forms a blind hole because the conductor layers 161 and 165 are formed first. 126, 146, so the conductor layers 161, 165 also have the function of a barrier layer, so there is no need to worry that the laser may penetrate the dielectric layers 120, 140, and the conductive seed layers 151, 153 located at the bottom of the blind holes 123, 143 are also No special thickening.

如第1J’圖所繪示,本發明再一實施方式提供一種中介板300。中介板300包含介電層120、導體層161、163以及導電晶種層159(即導電晶種層151、155之組合)。介電層120具有導通孔129。導體層163設置於導通孔129之上半部份(即盲孔126)中。導體層161設置於導通孔129之下半部份(即盲孔123)中。導電晶種層159設置於介電層120與導體層161、163之間。 As shown in FIG. 1J, another embodiment of the present invention provides an interposer 300. The interposer 300 includes a dielectric layer 120, conductor layers 161, 163, and a conductive seed layer 159 (ie, a combination of conductive seed layers 151, 155). The dielectric layer 120 has via holes 129. The conductor layer 163 is disposed in the upper half of the via 129 (ie, the blind via 126). The conductor layer 161 is disposed in the lower half of the via hole 129 (ie, the blind via 123). The conductive seed layer 159 is disposed between the dielectric layer 120 and the conductor layers 161, 163.

具體而言,導通孔129之上半部份具有內端孔徑D2,導通孔129之下半部份具有內端孔徑D1,內側孔徑D2小於內側孔徑D1。 Specifically, the upper half of the via hole 129 has an inner end aperture D2, and the lower half of the via hole 129 has an inner end aperture D1, and the inner aperture D2 is smaller than the inner aperture D1.

本發明上述實施方式藉由先形成導電晶種層151、153於盲孔123、143中,再使用雷射燒蝕介電層120、140而形成盲孔126、146,因為導電晶種層151、153可以作為阻擋層,所以不用擔心雷射可能穿透介電層120、140,因此雷射強度可以調強,導通孔129也就不會有介電層120、140殘留於其頸部。 The above embodiment of the present invention forms the blind vias 126, 146 by forming the conductive seed layers 151, 153 in the blind vias 123, 143, and then using the laser ablation dielectric layers 120, 140 because of the conductive seed layer 151. 153 can be used as a barrier layer, so there is no need to worry that the laser may penetrate the dielectric layers 120, 140, so the laser intensity can be adjusted, and the via holes 129 will not have the dielectric layers 120, 140 remaining in the neck.

雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

120‧‧‧介電層 120‧‧‧ dielectric layer

123、126‧‧‧盲孔 123, 126‧‧ ‧ blind holes

129‧‧‧導通孔 129‧‧‧through holes

151、155、159‧‧‧導電晶種層 151, 155, 159‧‧‧ conductive seed layer

161、163‧‧‧導體層 161, 163‧‧‧ conductor layer

200‧‧‧導體柱 200‧‧‧ conductor column

D1、D2‧‧‧內端孔徑 D1, D2‧‧‧ inner end aperture

300‧‧‧中介板 300‧‧‧Intermediary board

Claims (10)

一種中介板的製造方法,包含:形成一第一盲孔於一介電層之一第一面上;形成一第一導電晶種層於該第一盲孔中;形成一第二盲孔於該介電層之相對於該第一面的一第二面,其中該第一盲孔與該第二盲孔相對,且該第二盲孔裸露該第一導電晶種層;形成一第二導電晶種層於該第二盲孔中,且與該第一導電晶種層接觸;以及分別形成一第一導體層與一第二導體層填補該第一盲孔與該第二盲孔,以形成一導體柱於該介電層中。 A method for manufacturing an interposer includes: forming a first blind via on a first side of a dielectric layer; forming a first conductive seed layer in the first blind via; forming a second blind via a second surface of the dielectric layer opposite to the first surface, wherein the first blind hole is opposite to the second blind hole, and the second blind hole exposes the first conductive seed layer; forming a second The conductive seed layer is in the second blind hole and is in contact with the first conductive seed layer; and a first conductive layer and a second conductive layer are respectively formed to fill the first blind hole and the second blind hole, To form a conductor pillar in the dielectric layer. 一種中介板的製造方法,包含:形成一第一盲孔於一介電層之一第一面上;形成一第一導電晶種層於該第一盲孔中;形成一第一導體層填補該第一盲孔;形成一第二盲孔於該介面層之相對於該第一面的一第二面,其中該第一盲孔與該第二盲孔相對,且該第二盲孔裸露該第一導電晶種層;形成一第二導電晶種層於該第二盲孔中,且與該第一導電晶種層接觸;以及形成一第二導體層填補該第二盲孔中,以形成一導體柱於該介電層中。 A method for manufacturing an interposer includes: forming a first blind via on a first side of a dielectric layer; forming a first conductive seed layer in the first blind via; forming a first conductor layer to fill a first blind hole; a second blind hole is formed on a second surface of the interface layer opposite to the first surface, wherein the first blind hole is opposite to the second blind hole, and the second blind hole is exposed Forming a first conductive seed layer; forming a second conductive seed layer in the second blind via and contacting the first conductive seed layer; and forming a second conductive layer to fill the second blind via, To form a conductor pillar in the dielectric layer. 一種中介板的製造方法,包含:提供一基材,該基材包含一支承基板與設置於該支承基板上的一介電層;形成一第一盲孔於該介電層之一第一面上;形成一第一導電晶種層於該第一盲孔中;分離該介電層與該支承基板,並將該介電層倒置於該支承基板上;形成一第二盲孔於該介面層之相對於該第一面的一第二面,其中該第一盲孔與該第二盲孔相對,且該第二盲孔裸露該第一導電晶種層;形成一第二導電晶種層於該第二盲孔中,且接觸該第一導電晶種層;以及移除該支承基板,形成一第一導體層填補該第一盲孔,以及形成一第二導體層填補該第二盲孔,以形成一導體柱於該介電層中。 A method for manufacturing an interposer includes: providing a substrate, the substrate comprising a support substrate and a dielectric layer disposed on the support substrate; forming a first blind via on the first side of the dielectric layer Forming a first conductive seed layer in the first blind via; separating the dielectric layer from the support substrate, and depositing the dielectric layer on the support substrate; forming a second blind via at the interface a second surface of the layer opposite to the first surface, wherein the first blind hole is opposite to the second blind hole, and the second blind hole exposes the first conductive seed layer; forming a second conductive seed crystal Laying in the second blind via and contacting the first conductive seed layer; and removing the support substrate, forming a first conductor layer to fill the first blind via, and forming a second conductor layer to fill the second Blind holes to form a conductor post in the dielectric layer. 一種中介板的製造方法,包含:提供一基材,該基材包含一支承基板與設置於該支承基板上的一介電層;形成一第一盲孔於該介電層之一第一面上;形成一第一導電晶種層於該第一盲孔中;形成一第一導體層填補該第一盲孔;分離該介電層與該支承基板,並將該介電層倒置於該支承基板上; 形成一第二盲孔於該介面層之相對於該第一面的一第二面,其中該第一盲孔與該第二盲孔相對,且該第二盲孔裸露該第一導電晶種層;形成一第二導電晶種層於該第二盲孔中,且與該第一導電晶種層接觸;以及形成一第二導體層填補該第二盲孔,以形成一導體柱於該介電層中。 A method for manufacturing an interposer includes: providing a substrate, the substrate comprising a support substrate and a dielectric layer disposed on the support substrate; forming a first blind via on the first side of the dielectric layer Forming a first conductive seed layer in the first blind via; forming a first conductor layer to fill the first blind via; separating the dielectric layer from the support substrate, and placing the dielectric layer on the Supporting the substrate; Forming a second blind hole in a second surface of the interface layer opposite to the first surface, wherein the first blind hole is opposite to the second blind hole, and the second blind hole exposes the first conductive seed crystal Forming a second conductive seed layer in the second blind via and contacting the first conductive seed layer; and forming a second conductor layer to fill the second blind via to form a conductor pillar In the dielectric layer. 如請求項1至4任一項所述之製造方法,其中位於該第一盲孔之底部之該第一導電晶種層的厚度大於該第一導電晶晶種層之其他部份的厚度。 The manufacturing method according to any one of claims 1 to 4, wherein a thickness of the first conductive seed layer located at a bottom of the first blind via is greater than a thickness of other portions of the first conductive crystal seed layer. 如請求項1至4任一項所述之製造方法,其中該第一盲孔與該第二盲孔的形成方法為雷射燒蝕。 The manufacturing method according to any one of claims 1 to 4, wherein the first blind hole and the second blind hole are formed by laser ablation. 如請求項1至4任一項所述之製造方法,其中該介電層之材質為玻璃。 The manufacturing method according to any one of claims 1 to 4, wherein the dielectric layer is made of glass. 一種中介板,包含:一介電層,具有一導通孔;一第一導體層,設置於該導通孔之上半部份中;一第二導體層,設置於該導通孔之下半部份中;以及一導電晶種層,設置於該介電層、該第一導體層以及該第二導體層之間。 An interposer includes: a dielectric layer having a via hole; a first conductor layer disposed in the upper half of the via hole; and a second conductor layer disposed in the lower half of the via hole And a conductive seed layer disposed between the dielectric layer, the first conductor layer, and the second conductor layer. 如請求項8所述之中介板,其中位於該第一導體層與該第二導體層之間的該導電晶種層的厚度大於該導電晶種層之其他部份的厚度。 The interposer of claim 8, wherein the thickness of the conductive seed layer between the first conductor layer and the second conductor layer is greater than the thickness of other portions of the conductive seed layer. 如請求項8所述之中介板,其中該介電層之材質為玻璃。 The interposer of claim 8, wherein the dielectric layer is made of glass.
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