CN108447849A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN108447849A
CN108447849A CN201710850559.7A CN201710850559A CN108447849A CN 108447849 A CN108447849 A CN 108447849A CN 201710850559 A CN201710850559 A CN 201710850559A CN 108447849 A CN108447849 A CN 108447849A
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China
Prior art keywords
conducting shell
passivation layer
semiconductor packages
layer
hole
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CN201710850559.7A
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English (en)
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CN108447849B (zh
Inventor
宋元辅
赵兴华
刘明琪
陈鸿胜
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication of CN108447849A publication Critical patent/CN108447849A/zh
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Abstract

本发明之一半导体封装包括：一钝化层(passivation layer)，其具有一第一表面及与该第一表面相对之一第二表面该钝化层界定自该第一表面延伸至该第二表面之一通孔(through hole)，其自该第一面延伸至该第二表面，该通孔进一步由该钝化层之一第一侧壁及一第二侧壁所界定；一第一传导层，其在该钝化层之该第一表面及该第一侧壁上；一第二传导层，其在该钝化层之该第二表面及该第二侧壁上；及一第三传导层，其系介于该第一传导层与该第二传导层之间。

Description

半导体封装
技术领域
本发明系关于一种半导体封装，更特定而言，本发明系关于一种具有堆栈通路(stacked-via)之结构之半导体封装。
背景技术
自集成电路问世以来，由于各种电子组件与半导体封装之积体密度之持续增加，半导体工业因此经历持续快速成长，大体而言，系透过不断减缩组件之最小特征尺寸来增加积体密度，藉此允许将更多组件整合至一芯片或封装当中。一种用于将更多组件整合至一半导体结构之方式系三维集成电路(3D IC)堆栈技术之采用，其中多个通路系互相堆栈以形成一堆栈通路结构。制造习知堆栈通路结构时，因曝光不足造成之聚合物残余将导致经堆栈之各通路之间之高电阻甚至断路，因此需要额外之步骤来移除聚合物残余，此将增加堆栈通路结构之制造成本。综上，需要一种可避免聚合物残余之半导体封装。
发明内容
本发明之一实施例之一半导体封装包括：一钝化层(passivation layer)，其具有一第一表面及与该第一表面相对之一第二表面该钝化层界定自该第一表面延伸至该第二表面之一通孔(through hole)，其自该第一面延伸至该第二表面，该通孔进一步由该钝化层之一第一侧壁及一第二侧壁所界定；一第一传导层，其在该钝化层之该第一表面及该第一侧壁上；一第二传导层，其在该钝化层之该第二表面及该第二侧壁上；及一第三传导层，其系介于该第一传导层与该第二传导层之间。
本发明之一实施例之一半导体封装包括：一钝化层，其具有一第一表面及与该第一表面相对之一第二表面，该钝化层界定自第一表面延伸至该第二表面之一通孔，该通孔进一步由该钝化层之一侧壁所界定；一第一传导层，其在该钝化层之该第一表面及该第二表面之间并密封该通孔；一第二传导层，其系与该第一传导层相邻；及一第三传导层，其系与该第二传导层相对且与该第一传导层相邻。
本发明之一实施例之一种制造一半导体封装之方法包括：在一载体上提供一第一钝化层；图案化该第一钝化层以界定暴露该载体之一第一孔；通过该第一孔在该经暴露载体上设置一第一传导层；在该第一传导层上设置一第二传导层；以一第二钝化层取代该载体；图案化该第二钝化层以界定暴露该第一传导层之一第二孔；及通过该第二孔在该经暴露第一传导层上设置一第三传导层。
附图说明
图1A为依据本发明之一实施例之一半导体封装之示意图。
图1B为依据本发明之一实施例之一半导体封装之示意图。
图2A～2I为依据本发明之一实施例之制造一半导体封装之方法之示意图。
图3为依据本发明之一实施例之一半导体封装之示意图。
图4A～4J为依据本发明之一实施例之制造一半导体封装之方法之示意图。
图5A为依据本发明之一实施例之一半导体封装之示意图。
图5B为依据本发明之一实施例之一半导体封装之示意图。
图5C为依据本发明之一实施例之一半导体封装之示意图。
图5D为依据本发明之一实施例之一半导体封装之示意图。
图5E为依据本发明之一实施例之一半导体封装之示意图。
图5F为依据本发明之一实施例之一半导体封装之示意图。
贯穿图式及详细描述使用共同参考数字以指示相同或类似组件。本发明的实施例将从结合附图进行的以下详细描述更显而易见。
具体实施方式
以下揭露本发明之各种实施例之制造及使用，但应了解下文各实施例中所阐述之发明概念可体现于其他各种具体情境中，应理解下述揭示内容提供各实施例之不同特征之实施例或范例，特定组件或配置仅用于释例性说明，其并非用于局限本发明之范畴。
以下使用特定文字描述图标中所绘示之实施例或范例，需理解该等实施例或范例并非用于局限本发明之范畴，对于本发明中之实施例之任何改造或变更，或者针对本发明中实施例之原理之进一步应用，皆属于本发明之范畴。
此外，应理解可简明描述装置之制程步骤及/或特征，且在实施本发明之方法或使用本发明之系统或装置时，可加入额外之制程步骤及/或特征，且可移除或改变本发明之特定制程步骤及/或特征，故下文所述仅系本发明之实施例或范例，其并非用于局限本发明之范畴。
此外，本文中可于不同范例中使用相同之组件符号及/或字符，上述仅系出于简洁之目的而使用相同之组件符号及/或字符，其并不代表使用相同之组件符号及/或字符之不同范例或组态间应具有特定之关系。
此外，例如「上方」及「下方」等空间相对术语仅系便于描绘图标中组件之相对关系，但空间相对术语实际上可包含除图标中组件之定向以外之其他定向，例如图标中组件之定向可经翻转90度，此时空间相对术语则可被对应地解释。
参照图示内容，图1A系依据本发明之一实施例之一半导体封装结构100之横截面示意图，半导体封装结构100包括一钝化层101，钝化层101具有一表面106(第一表面)，钝化层101具有另一表面107(第二表面)，表面107系与表面106相对且实质上平行于表面106，钝化层101包括一通孔(through hole)102，通孔102自表面106延伸至表面107，通孔102系由侧壁102a及侧壁102b所界定，通孔102可具有一X形或者沙漏形之横截面。
半导体封装结构100进一步包括传导层103、传导层104及传导层105，传导层104系设置于钝化层101之表面106及侧壁102a上，传导层105系设置于钝化层101之表面107及侧壁102b上，传导层103系设置于传导层104及传导层105之间，传导层103可与传导层104直接接触，传导层103可与传导层105直接接触，传导层104及传导层105可由传导层103分隔，通孔102可由传导层103密封，传导层103、传导层104及传导层105形成本发明之一实施例之一堆栈通路结构。
传导层104包括部分104a、部分104b及部分104c，部分104a设置于表面106上，部分104b设置于侧壁102a上，部分104c系位于通孔102中并实质上平行于表面106而延伸，传导层105包括部分105a、部分105b及部分105c，部分105a设置于表面107上，部分105b设置于侧壁102b上，部分105c系位于通孔102中并实质上平行于表面107而延伸，传导层104之部分104c具有比传导层105之部分105c之尺寸(例如面积)更大之尺寸，举例而言，传导层104之部分104c所覆盖之表面106之面积大于传导层105之部分105c所覆盖之表面107之面积，于一实施例中，传导层104包括用于接收接合材质之顶部凸块下金属化层(UBM)，而传导层105包括底部UBM。
于一实施例中，传导层103包括金属层103a及金属层103b，金属层103a系与传导层104相邻，金属层103b系与传导层105相邻，于一实施例中，金属层103a具有设置于表面106上且与表面106直接接触之部分、设置于侧壁102a上且与侧壁102a直接接触之部分及位于通孔102中并实质上平行于表面106而延伸之部分，相同地，金属层103b具有设置于表面107上且与表面107直接接触之部分、设置于侧壁102b上且与侧壁102b直接接触之部分及位于通孔102中并实质上平行于表面107而延伸之部分，于一实施例中，金属层103a及金属层103b可分别做为用于电镀传导层104及传导层105之晶种层，传导层103之金属层103a及金属层103b可由一钛铜(TiCu)合金形成。
钝化层101可包括聚酰亚胺(PI)，钝化层101可由一感光材料所形成，钝化层101可包括聚合物层101a及聚合物层101b，侧壁102a系由聚合物层101a所界定，侧壁102b系由聚合物层101b所界定，于一实施例中，金属层103a系位于传导层104及聚合物层101a之间，金属层103b系位于传导层105及聚合物层101b之间，在通孔102中之传导层103、传导层104及传导层105之一总厚度(亦即部分104c、部分105c及通孔102中之传导层103之总厚度)可小于该钝化层101之一厚度，焊球(钖球)108可与传导层105之经暴露部份直接接触并囊封该传导层105之经暴露部份，由于厚度降低，半导体封装结构100内之导电路径缩短，故可大幅提高部分104c及部分105c之间之电导率。
图1B系依据本发明之一实施例之一半导体封装结构100b之横截面示意图，半导体封装结构100b包括与图1A之半导体封装结构100相似之封装结构，半导体封装结构100b包括一钝化层101及传导层103、传导层104及传导层105(传导层103系位于传导层104及传导层105之间且未示于图中)，传导层104经由焊球109而与半导体结构111耦接，半导体结构111可为一半导体晶粒，半导体结构111可被一模塑料(molding compound)110囊封。
图2A～2I为依据本发明之一实施例之制造一半导体封装之方法之示意图。
于图2A，提供一载体200，于图2B，在载体200上提供一聚合物层101a，于图2C，在聚合物层101a之一表面上提供一光阻层201，图案化光阻层201以暴露下方之聚合物层101a之部份，可藉由一蚀刻制程移除下方之聚合物层101a之经暴露部份，于图2D，在聚合物层101a之经移除部份中设置传导层103，传导层104(可藉由电镀)设置于传导层103上，于图2E，传导层104经由焊球109而与半导体结构(例如半导体晶粒)111耦接，半导体结构111接着被一模塑料110囊封，于图2F，移除载体200，于图2G，在聚合物层101a之一表面上提供一聚合物层101b，图案化聚合物层101b以暴露传导层103，于图2H，(可藉由电镀)将传导层105设置于聚合物层101b之经移除部份中，或者将一传导层设置于聚合物层101b之经移除部份中做为电镀传导层105之晶种层，于图2I，焊球108耦接至传导层105。
图3系依据本发明之一实施例之一半导体封装结构300之横截面示意图，半导体封装结构300包括与图1B.之半导体封装结构100b相似之封装结构，半导体封装结构300包括一钝化层101及传导层104'、传导层104”及传导层105，传导层104'经由焊球109而与半导体结构111耦接，传导层105经由焊球108而与外部电路结构电连接，半导体结构111可为一半导体晶粒，半导体结构111可被一模塑料110囊封。钝化层101包括聚合物层101a、101b及101c，传导层104”可为将传导层104'连接至传导层105之一重分布层(RDL)，可于传导层104'及传导层104”之间或传导层104”及传导层105之间形成额外之传导层(例如图1A中所示之传导层103)。
图4A～4J为依据本发明之一实施例之制造一半导体封装之方法之示意图。
于图4A，提供一载体200，在载体200上提供一聚合物层101c，于图4B，在聚合物层101c之一表面上提供一光阻层201，图案化光阻层201以暴露下方之聚合物层101c之部份，可藉由一蚀刻制程移除下方之聚合物层101c之经暴露部份，于图4C，在聚合物层101c之经移除部份中设置传导层103，传导层104”(可藉由电镀)设置于传导层103上，于图4D，另一聚合物层101a系设置于聚合物层101c上，图案化聚合物层101a以暴露传导层104”，于图4E，(可藉由电镀)将传导层104'设置于聚合物层101a之经移除部份中并在传导层104”之经暴露部份上，或者将一传导层设置于聚合物层101a之经移除部份中做为电镀传导层104'之晶种层，于图4F，传导层104'经由焊球109而与半导体结构(例如半导体晶粒)111耦接，半导体结构111接着被一模塑料110囊封，于图4G，移除载体200，于图4H，在聚合物层101a之一表面上提供一聚合物层101b，图案化聚合物层101b以暴露下方之传导层103，于图4I，(可藉由电镀)将传导层105设置于聚合物层101b之经移除部份中，或者将一传导层设置于聚合物层101b之经移除部份中做为电镀传导层105之晶种层，于图4J，焊球108耦接至传导层105。
图5A～5F系依据本发明之多个实施例之半导体封装结构之横截面示意图。
于图5A中，传导层104之宽度W104与传导层105之宽度W105实质相同。于图5B中，传导层104之宽度W104大于传导层105之宽度W105。于图5C中，传导层104之宽度W104小于传导层105之宽度W105，其中使用具有不同宽度之传导层104及传导层105可允许使用不同尺寸之接合材料或焊球。于图5D中，可于传导层104与传导层105之间设置一额外之传导层105'，传导层105'可在横向方向上延伸以电连接至其他半导体组件。于图5E中，可使传导层104连接至设置于一上钝化层之另一传导层104d。于图5F中，可于传导层104上方设置另一传导层104e。
如本文中所使用，词语“近似地”、“大体上”、“实质的”及“约”用以描述及说明小变化。当与事件或情形结合使用时，所述词语可指事件或情形明确发生的情况及事件或情形极近似于发生的情况。举例来说，当结合数值使用时，所述词语可指小于或等于彼数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(例如，小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％)，则可认为所述两个数值“大体上”相同。举另一例来说，如果第一角度和第二角度之间的差小于或等于±10°、小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°、或小于或等于±0.05°，则第一角度可以与第二角度近似地相同。
如果两个表面之间的位移仅为5微米、仅为2微米、仅为1微米或仅为0.5微米，那么可认为所述两个表面为共平面的或实质上共平面的。
另外，有时在本文中按范围格式呈现量、比率及其它数值。应理解，此类范围格式是为便利及简洁起见而使用，且应灵活地理解为不仅包含明确指定为范围极限的数值，且还包含涵盖于彼范围内的所有个别数值或子范围，就如同明确指定每一数值及子范围一般。
尽管已参考本发明的特定实施例描述并说明本发明，但这些描述及说明并不限制本发明。所属领域的技术人员应理解，在不脱离如由所附权利要求书界定的本发明的真实精神及范畴的情况下，可作出各种改变且可用等效物取代。说明可不一定按比例绘制。归因于工艺及容限，本发明中的艺术再现与实际装置之间可存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书及图式视为说明性而非限制性的。可作出修改，以使特定情形、材料、物质组成、方法或工艺适应于本发明的目标、精神及范畴。所有所述修改均意欲处于此处随附的权利要求书的范畴内。尽管已参看按特定次序执行的特定操作描述本文中所揭示的方法，但应理解，在不脱离本发明的教示的情况下，可组合、再分或重新定序这些操作以形成等效方法。因此，除非本文中具体指示，否则操作的次序及分组并非对本发明的限制。

Claims (25)

1.一种半导体封装，其包含：
一钝化层(passivation layer)，其具有一第一表面及与该第一表面相对之一第二表面，该钝化层界定自该第一表面延伸至该第二表面之一通孔(through hole)，其自该第一表面延伸至该第二表面，该通孔进一步由该钝化层之一第一侧壁及一第二侧壁所界定；
一第一传导层，其在该钝化层之该第一表面及该第一侧壁上；
一第二传导层，其在该钝化层之该第二表面及该第二侧壁上；及
一第三传导层，其系介于该第一传导层与该第二传导层之间。
2.如请求项1之半导体封装，其中该第三传导层直接接触该第一传导层。
3.如请求项1之半导体封装，其中该第三传导层直接接触该第二传导层。
4.如请求项1之半导体封装，其中该第一传导层及该第二传导层系由该第三传导层分隔。
5.如请求项1之半导体封装，其中该第三传导层包含与该第一传导层相邻之一第一晶种层(seed layer)及与该第二传导层相邻之一第二晶种层。
6.如请求项5之半导体封装，其中该第一晶种层延伸至该钝化层之该第一表面且该第二晶种层延伸至该钝化层之该第二表面。
7.如请求项5之半导体封装，其中该钝化层包含一第一聚合物层及一第二聚合物层。
8.如请求项7之半导体封装，其中该第一晶种层系介于该第一传导层与该第一聚合物层之间且该第二晶种层系介于该第二传导层与该第二聚合物层之间。
9.如请求项1之半导体封装，其中该第一传导层包含在该第一表面上之一第一部分、在该第一侧壁上之一第二部分及在该通孔中且实质上平行于该第一表面而延伸之一第三部分。
10.如请求项9之半导体封装，其中该第二传导层包含在该第二表面上之一第一部分、在该第二侧壁上之一第二部分及在该通孔中且实质上平行于该第二表面而延伸之一第三部分。
11.如请求项10之半导体封装，其中该第一传导层之该第一部分具有比该第二导电层之该第一部分之尺寸更大之尺寸。
12.如请求项1之半导体封装，其中该第三传导层系由一钛铜合金所形成。
13.如请求项1之半导体封装，其中在该通孔中之该第一传导层、该第二传导层及该第三传导层之一总厚度小于该钝化层之一厚度。
14.一半导体封装，其包含：
一钝化层，其具有一第一表面及与该第一表面相对之一第二表面，该钝化层界定自该第一表面延伸至该第二表面之一通孔，该通孔进一步由该钝化层之一侧壁所界定；
一第一传导层，其在该钝化层之该第一表面及该第二表面之间并密封该通孔；
一第二传导层，其系与该第一传导层相邻；及
一第三传导层，其系与该第二传导层相对且与该第一传导层相邻。
15.如请求项14之半导体封装，其进一步包含一接合金属及透过该接合金属而电连接至该第一传导层之一半导体晶粒。
16.如请求项14之半导体封装，其中该钝化层系由一感光材料所形成。
17.如请求项14之半导体封装，其中该感光材料系由一聚合物所形成。
18.如请求项17之半导体封装，其中该聚合物包含聚酰亚胺(polyimide)。
19.如请求项14之半导体封装，其中该第二传导层在该钝化层之该第一表面上延伸。
20.如请求项14之半导体封装，其中该第三传导层在该钝化层之该第二表面上延伸。
21.一种制造一半导体封装之方法，其包含：
在一载体上提供一第一钝化层；
图案化该第一钝化层以界定暴露该载体之一第一孔；
通过该第一孔在该经暴露载体上设置一第一传导层；
在该第一传导层上设置一第二传导层；
以一第二钝化层取代该载体；
图案化该第二钝化层以界定暴露该第一传导层之一第二孔；及
通过该第二孔在该经暴露第一传导层上设置一第三传导层。
22.如请求项21之方法，其进一步包含在该第三传导层上设置一第四传导层。
23.如请求项21之方法，其中取代该载体包含：
将该第二传导层耦接至一半导体晶粒；
以一模塑料(molding compound)囊封该半导体晶粒；
使该载体自该第一钝化层分离；及
在该第一钝化层上设置该第二钝化层。
24.如请求项21之方法，其中该第一钝化层及该第二钝化层包含聚酰亚胺。
25.如请求项21之方法，其中该第一传导层系由一钛铜合金所形成。
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