CN111341734A - 半导体封装和制作半导体封装的方法 - Google Patents

半导体封装和制作半导体封装的方法 Download PDF

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Publication number
CN111341734A
CN111341734A CN201911271514.XA CN201911271514A CN111341734A CN 111341734 A CN111341734 A CN 111341734A CN 201911271514 A CN201911271514 A CN 201911271514A CN 111341734 A CN111341734 A CN 111341734A
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Prior art keywords
layer
semiconductor package
top surface
semiconductor devices
mosfet
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CN201911271514.XA
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Inventor
张晓天
薛彦迅
王隆庆
何约瑟
牛志强
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Cayman Ltd
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Publication of CN111341734A publication Critical patent/CN111341734A/zh
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Abstract

本发明的半导体封装具有多根支柱或部分多根带状引脚、多个半导体器件、一个或两个塑封层以及多个电气互连。半导体封装不包括A电线和夹子。应用一特定方法，制作半导体封装。该方法包括：提供可拆卸载体；形成多根支柱或多根带状引脚；固定多个半导体器件；形成一个或两个塑封层；形成多个电气互连并拆除可拆卸载体。该方法可进一步包括切割分离过程。

Description

半导体封装和制作半导体封装的方法
技术领域
发明一般涉及半导体封装和制作半导体封装的方法。更具体地说，本发明涉及不包括电线和夹子的半导体封装。
背景技术
在电源管理应用中，一种非常流行的做法是在一个封装中合并打包一对高端(HS)和低端(LS)金属氧化物半导体场效应晶体管(MOSFET)。传统型驱动器和MOSFET模块(DrMOS)使用电线和夹子，将芯片接入芯片，并将芯片接入引线。电线导致较高的电阻和较高的电感。夹子导致较高应力于半导体器件。
发明内容
本发明的半导体封装不包括电线和夹子，本发明的优势包括电气可路由、能扩展到大型面板制造、不使用含引脚(不环保)的装片焊料、低电阻、低电感、较小应力、较高热耗散、较简单组装过程和较小形状因子。
本发明披露具有多根支柱或多根带状引脚、多个半导体器件、一个或两个塑封层以及多个电互相联接的半导体封装。该半导体封装不包括电线和夹子。应用一特定方法来制作半导体封装。该方法包括提供一可拆卸载体、形成多根支柱或多根带状引脚、连接多个半导体器件、形成一个或两个塑封层、形成多个电互相联接和拆除可拆卸载体。该方法可进一步包含切割分离过程。
半导体封装包含第一金属氧化物半导体场效应晶体管(MOSFET)和第二MOSFET。第一和第二MOSFET中的一个被翻转，以使源电极处于底部表面。
附图说明
图1是制作本发明示例中半导体封装过程的流程图。
图2是形成本发明示例中多个电气连接过程的流程图。
图3A、4A、5A、6A、7A、8A、9A、10A、11A、12A、13A、14A、15A、16A、17A和18A显示俯视图，而图3B、4B、5B、6B、7B、8B、9B、10B、11B、12B、13B、14B、15B、16B、17B和18B显示本发明示例中制作图1半导体封装过程中沿AA、BB、CC、DD、EE、FF、GG、HH、II、JJ、KK、LL、MM、NN、OO和PP步骤的截面图。
图19是本发明示例中制作半导体封装的另一过程的流程图。
图20A、21B、22B、23B、24B、25B、26B和27B显示俯视图，而图20B、21A、22A、23A、24A、25A、26A和27A显示本发明示例中制作图19半导体封装过程中沿QQ、RR、SS、TT、UU、VV、WW和XX步骤的截面图。
图28显示本发明示例中凹口和半导体器件之间膜的侧视图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1是本发明示例中制作半导体封装的过程100的流程图。过程100可以从步骤102开始。
在步骤102中，提供图3A和3B中的可拆卸载体310。在一个示例中，可拆卸载体310被应用于制作单个半导体封装(图3A和3B中左侧实线部分)的过程。在另一示例中，可拆卸载体310被应用于制作两个或多个半导体封装(例如：图3A和3B中左侧实线部分以及图3A和3B中右侧虚线部分)的过程。为简单起见，虚线部分的右侧(其结构与相应左侧实线部分相同)未显示于图4A、5A、6A、7A、8A、9A、10A、11A、12A、13A、14A、15A、16A和17A以及图4B、5B、6B、7B、8B、9B、10B、11B、12B、13B、14B、15B、16B和17B。在一个示例中，可拆卸载体310由不锈钢制成。步骤102之后可追随步骤104。
在步骤104中，图3A和3B中多根支柱320形成于可拆卸载体310的顶面312上。在发明示例中，多根支柱320由布置在可拆卸载体310顶面312上的铜材料制成，围绕用于安装半导体芯片的暴露顶面312区域。多根支柱320的高度最好基本等于或稍高于半导体器件的厚度。在一示例中，多根支柱320的高度为100微米或更高，而半导体器件的厚度为100微米或更高。步骤104之后可追随步骤106。
在步骤106中，图4A和4B中多个半导体器件430通过应用装片粘合剂固定在可拆卸载体310的顶面312。在本发明示例中，多个半导体器件430包括第一金属氧化物半导体场效应晶体管(MOSFET)440、第二MOSFET 450和集成电路(IC)460。在本发明示例中，第一MOSFET440、第二MOSFET 450和IC 460为长方柱体形状。第一MOSFET 440的顶面、第二MOSFET 450的顶面以及IC 460的顶面均平行于可拆卸载体310的顶面312。在本发明示例中，第一MOSFET 440具有可由其顶面上铜层形成的源电极442和栅电极444，以及可由其底面上铜层形成的漏电极446。在本发明示例中，第二MOSFET 450被翻转。第二MOSFET 450具有可由铜层形成的源电极452和可由其底面上铜层形成的栅电极454，以及可由其顶面上铜层形成的漏电极456。在本发明示例中，IC 460具有可由其顶面上铜层形成的多个接合焊盘462。装片时不使用芯片焊盘，因为形成每一半导体器件的半导体芯片电极的铜层由装片粘合剂固定在为多根支柱320所围绕的可拆卸载体310暴露顶面312。形成每一半导体器件顶面或底面电极的铜层最好在20至50微米之间。步骤106之后可追随步骤108。
在步骤108中，形成图5A和5B中的第一塑封层。在本发明示例中，第一塑封层520为透明显示。第一塑封层520装入大部分多根支柱320和大部分多个半导体器件430。第一塑封层520可具有稍大于半导体芯片厚度的高度，以致需要磨削或研磨过程来暴露遮蔽电极和支柱顶面。步骤108之后可追随步骤110。或者，第一塑封层520可具有与半导体器件厚度基本相同的高度，以致暴露每一器件电极的顶面和支柱顶面。在此情况下，可略过步骤110中步骤。
在步骤110中，将磨削或研磨过程应用于第一塑封层520图5A和5B中的顶面522，以致形成机加工第一塑封层620图6A和6B中的暴露表面622。多个半导体器件430的多个电极630暴露于机加工第一塑封层620表面622。步骤110之后可追随步骤112。
在步骤112中，将图7A和7B中的第一种晶层760涂覆于机加工第一塑封层620的暴露表面622。在一示例中，第一种晶层760由导电材料制成。在本发明示例中，于暴露的多个电极630由铜形成的情况下，可略过步骤112(用虚线表示)。步骤112之后可追随步骤114。
在步骤114中，将图8A和8B中的第一光阻层880涂覆于机加工第一塑封层620暴露表面622之上。在一示例中，涂覆图7A和7B中的第一种晶层760，第一光阻层880被直接固定在第一种晶层760。在另一示例中，未涂覆图7A和7B中的第一种晶层760，第一光阻层880被直接固定在机加工第一塑封层620暴露表面622。步骤114之后可追随步骤116。
在步骤116中，在第一曝光过程下应用第一图案掩蔽，形成图9A和9B中第一光阻图案990。步骤116之后可追随步骤118。
在步骤118中，将图10A和10B中第一再分布层(RDL)1020涂覆于第一塑封层620暴露表面622之上，以致形成第一多个电气互连。步骤118之后可追随步骤120。
在步骤120中，清除了(通过剥离)图9A和9B中的第一光阻图案990，留出图11A和11B中的空间1140。步骤120之后可追随步骤122。
在步骤122中，有一个示例，即涂覆图7A和7B中的第一种晶层760，且在当前步骤中蚀刻掉该种晶层。在另一示例中，未涂覆图7A和7B中的第一种晶层760，且未在当前步骤中蚀刻掉这种晶层。步骤122因而成为用虚线显示的可选步骤。步骤122之后可追随步骤124。
在步骤124中，形成图12A和12B中的第二塑封层1220。在本发明示例中，第二塑封层1220为透明显示。第二塑封层1220装入第一多个电气互连1240和所有其他顶面电极。电气互连1240将半导体器件上每一顶面电极接入支柱或者不同半导体器件(未显示)的另一顶面电极。步骤124之后可追随步骤126。
在步骤126中，清除了图3A和3B中的可拆卸载体310，留出图13A和13B中的暴露底面1310。步骤126之后可追随步骤128。
在步骤128中，于图13A和13B中暴露底面1310下(同时于图4A和4B中多个半导体器件430下)形成图18A和18B中第二多个电气互连1840。在图2中详细说明了步骤128。步骤128之后可追随步骤130。
在步骤130中，沿图18A和18B中平面1898应用切割分离过程。在切割分离过程之后形成半导体封装1800。用实线表示的封装与用虚线表示的封装互相分离。
图2是本发明示例中多个电气连接形成过程(步骤128)的流程图。过程(步骤128)的子步骤可从步骤212开始。
在步骤212中，将图14A和14B中的第二种晶层1460涂覆于图13A和13B中的暴露底面1310。在一示例中，第二种晶层1460由导电材料制成。在本发明示例中，由于存在图13A和13B中的多个暴露电极1330，步骤212为可选项(用虚线显示)。步骤212之后可追随步骤214。
在步骤214中，在图4A和4B中的多个半导体器件430下方涂覆图15A和15B中的第二光阻层1580。在一示例中，涂覆图14A和14B中的第二种晶层1460，且第二光阻层1580直接固定在第二种晶层1460。在另一示例中，未涂覆图14A和14B中的第二种晶层1460，且第二光阻层1580直接固定在图13A和13B中的暴露底面1310。步骤214之后可追随步骤216。
在步骤216中，于第二曝光过程中，通过应用第二图案掩蔽，形成图16A和16B中的第二光阻图案1690。步骤216之后可追随步骤218。
在步骤218中，于图4A和4B中的多个半导体器件430下方涂覆图17A和17B中的第二再分布层(RDL)1720。步骤218之后可追随步骤220。
在步骤220中，清除了(通过剥离)图16A和16B中的第二光阻图案1690，留出图18A和18B中的空间1841。步骤220之后可追随步骤222。
在步骤122中，有一个示例，即涂覆图14A和14B中的第二种晶层1460，且在当前步骤中蚀刻掉该种晶层。在另一示例中，未涂覆图14A和14B中的第二种晶层1460，且未在当前步骤中蚀刻掉种晶层。步骤222因而成为用虚线显示的可选步骤。
图18A和18B在本发明示例中显示半导体封装1800(用实线表示)。半导体封装1800包含多根支柱320、多个半导体器件430、第一塑封层620、第一塑封层620顶面上的第一多个电气互连1240、覆盖第一塑封层620顶面上第一多个电气互连1240的第二塑封层1220，以及布置在第一塑封层620底面上的第二多个电气互连1840。第一塑封层620装入大部分多根支柱320和大部分多个半导体器件430。第一多个电气互连1240将多根支柱320电气连接至多个半导体器件430或者不同半导体器件之间顶面上的电极。第二塑封层1220装入第一多个电气互连1240。底面上的第二多个电气互连1840将多根支柱320电气连接至多个半导体器件430。多根支柱320的底面和半导体器件的底部电极暴露于第一塑封层620底面。第二塑封层1220的底面直接固定在第一塑封层620的顶面。
在本发明示例中，整个第一多个电气互连1240被嵌入第二塑封层1220。于第一塑封层620下方暴露整个第二多个电气互连1840。
在本发明示例中，第一塑封层620和第二塑封层1220由同一材料制成。在本发明示例中，第一塑封层620和第二塑封层1220由不同材料制成。在本发明示例中，第一塑封层620的硬度高于第二塑封层1220，因为第一塑封层620经历过磨削或研磨过程(见步骤110)。在本发明示例中，第一塑封层620包含第一百分比的玻璃充填(例如，50％的玻璃充填)。第二塑封层1220包含第二百分比的玻璃充填(例如，25％的玻璃充填)。玻璃充填的第一百分比大于玻璃充填的第二百分比(50％大于25％)。
在本发明示例中，多个半导体器件包含集成电路(IC)460、第一金属氧化物半导体场效应晶体管(MOSFET)440和第二MOSFET450。第一MOSFET 440包含其顶面上的小面积栅电极444和大面积源电极442，且大面积漏电极446大幅延伸跨越整个第一MOSFET 440底面。第二MOSFET 450包含其底面上的小面积栅电极454和大面积源电极452，且大面积漏电极456大幅延伸跨越整个第二MOSFET 450顶面。第一多个电气互连1240之一将第一MOSFET 440顶面上的漏电极446和第二MOSFET 450顶面上的源电极452互相连接。在第一塑封层620顶面上电镀铜以形成电气互连1240的过程还可增大第一MOSFET 440和第二MOSFET 450顶面电极的铜厚度达相同数量。于是，第一塑封层620顶面上电气互连1240的铜层厚度为20至50微米，而第一MOSFET 640顶面和第二MOSFET 650顶面上的总体铜层厚度为40至100微米。第一MOSFET 640顶面和第二MOSFET 650顶面上的铜厚度最好不大于第一塑封层620顶面上电气互连1240铜厚度的两倍。出于同样的原因，第一塑封层620底面上电气互连1840的铜层厚度为20至50微米，而第一MOSFET 640底面和第二MOSFET 650底面上的总体铜层厚度为40至100微米。第一MOSFET 640底面和第二MOSFET 650底面上的铜厚度最好不大于第一塑封层620底面上电气互连1820铜厚度的两倍。
在本发明示例中，半导体封装1800不包括电线(例如：9,754,864号美国专利图6A中的电线)。半导体封装1800不包括夹子(例如：9,754,864号美国专利图6B中的夹子)。未将芯片焊盘用于芯片焊接，因而底部电镀铜电极通过封装底面暴露于外。
图19是本发明示例中半导体封装制作过程1900的流程图。过程1900可以从步骤1902开始。
在步骤1902中，制备有图20A中的多个晶片2000。多个晶片2000含有多个半导体器件2020。在本发明示例中，第一晶片含有多个金属氧化物半导体场效应晶体管(MOSFET)。第二晶片含有多个集成电路(IC)。步骤1902之后可追随步骤1904。
在步骤1904中，在多个晶片2000的多个顶面和多个底面上电镀铜。所选图20B(沿图20A中QQ的截面图)中的半导体器件包含顶镀铜2024和底镀铜2026，后者布置在每一金属触点之上，以形成电极。在本发明示例中，顶镀铜2024的厚度为20微米至50微米。在本发明示例中，底镀铜2026的厚度为20微米至50微米。步骤1904之后可追随步骤1906。
在步骤1906中，沿多个水平线2040和多个垂直线2060，对图20A中的多个晶片2000施加切割分离过程，从而形成图22A和22B中的多个分离半导体器件2230。作为一选项，多个分离半导体器件2230可在切割分离过程前后受到预成型层的保护。步骤1906之后可追随步骤1908。
在步骤1908中，提供图21A和21B中的可拆卸载体2110。在一示例中，可拆卸载体2110由不锈钢材料制成。步骤1908之后可追随步骤1910。
在步骤1910中，图21A和21B中的多根带状引脚2120形成于可拆卸载体2110的顶面2112上。在本发明示例中，未使用芯片焊盘。在本发明示例中，多根带状引脚2120由铜材料制成，在预定重复空间处以预定宽度布置于可拆卸载体2110上。在本发明示例中，多根带状引脚2120中的每一根都包含多根水平条，后者可在两端得到垂直条的连接，以形成引脚组。穿行通过多根水平条中心的垂直长条2129将带状引脚2120的每一根分成左侧的第一带状引脚部分2125和右侧的第二带状引脚部分2127。每组引脚包括一根或多根水平条，后者在一端与在同一端未连接的不同组相连。如图21B所示，第一带状引脚部分2125包含两组引脚，其中只有底部水平条2125A未于左端接入其他水平条，而第二带状引脚部分2127仅包含一组引脚，因为其所有水平条均在右端接入。在一示例中，在可拆卸载体2110的顶面2112上直接电镀铜，高度至少达到布置于可拆卸载体2110上半导体芯片的厚度，以便形成多根带状引脚2120。在另一示例中，多根预先成型铜条被接合至可拆卸载体2110的顶面2112，以便形成多根带状引脚2120。步骤1910之后可追随步骤1912。
在步骤1912中，图22A和22B中的多组分离半导体器件2230在由带状引脚2120分隔的重复空间内，固定在可拆卸载体2110的顶面2112；每一组分离半导体器件2230占有重复空间之一。在本发明示例中，一组分离半导体器件2230包含第一金属氧化物半导体场效应晶体管(MOSFET)2240和第二MOSFET 2250。在本发明示例中，第一MOSFET 2240和第二MOSFET 2250为长方柱体形状。第一MOSFET 2240的顶面和第二MOSFET 2250的顶面平行于可拆卸载体2110的顶面2112。在本发明示例中，第一MOSFET 2240为低端(LS)MOSFET。第一MOSFET 2240被翻转。第一MOSFET 2240在其底面上具有源电极2242和栅电极2244，在其顶面上具有漏电极2246。在本发明示例中，第二MOSFET 2250为高端(HS)MOSFET。第二MOSFET2250在其顶面上具有源电极2252和栅电极2254，在其底面上具有漏电极2256。每一顶面或底面电极分别由顶镀铜2024或底镀铜2026制成。步骤1912之后可追随步骤1914。
在步骤1914中，形成图23A和23B中的塑封层2320。在本发明示例中，塑封层2320为透明显示。塑封层2320装入大部分多根带状引脚2120和多个分离半导体器件2230。
在本发明示例中，步骤1914包含在模具凹口2834和多个分离半导体器件2230之间涂覆图28中可清除薄膜的子步骤，用以保护表面电极免受成型材料影响，以使表面电极在成型过程之后能暴露于外。或者，可形成包覆成型层，以覆盖全部多个分离半导体器件2230。步骤1914之后可追随步骤1916。
在步骤1916中，对图23A和23B中的塑封层2320顶面2322施加可选研磨过程(用虚线显示)。在本发明示例中,研磨过程去除塑封层厚度达1至3微米，同时磨削过程去除塑封层厚度达10至20微米。
多个分离半导体器件2230的多个电极2330和带状引脚2120暴露于塑封层2320顶面2322。步骤1916之后可追随步骤1918。
在步骤1918中，通过在塑封层2320顶面上电镀20至50微米的铜层，形成图24A和24B中的多个电气互连2486。多个电气互连2486将多个分离半导体器件2230的顶面电极接入围绕该多个器件的带状引脚2120，并使不同器件顶面上的电极互连。特别地，第一MOSFET2240顶面上的漏电极2246和第二MOSFET 2250顶面上的源电极2252得到互连，并接入邻近带状引脚2120内的一个或多个引脚组；第二MOSFET 2250顶面上的栅电极2254接入邻近带状引脚2120中的另一引脚组。如图所示，使第一MOSFET 2240顶面上漏电极2246和第二MOSFET 2250顶面上源电极2252互相连接的电气互连2486大幅延伸越过邻近带状引脚2120之间塑封层2320的整个顶面，但接入邻近带状引脚底部水平条2125A的第二MOSFET 2250顶面上的栅电极2254处分离除外。在塑封层2320顶面上电镀铜以形成电气互连2486的过程还可使分离半导体器件2230顶面电极的铜厚度提高达相同数量。于是，塑封层2320顶面上电气互连2486的铜层厚度为20至50微米，而第一MOSFET 2240和第二MOSFET 2250顶面上的总体铜层厚度为40至100微米。第一MOSFET 2240和第二MOSFET 2250顶面上的铜层厚度最好为塑封层2320顶面上电气互连2486铜层厚度的约两倍。布置于每一金属触点之上以形成第一MOSFET 2240和第二MOSFET 2250底面上底部电极的底镀铜2026不改变其厚度，保持在20至50微米。第一MOSFET 2240和第二MOSFET 2250底面上的铜厚度最好与塑封层2320顶面上电气互连2486的铜厚度近似相同。步骤1918之后可追随步骤1920。
在步骤1920中，拆除了图21A和21B中的可拆卸载体2110，留出图25A和25B中的暴露底面2510。第一MOSFET 2240底部的源电极2242和栅电极2244的底面以及第二MOSFET2250底部的漏电极2256的底面暴露于塑封层2320底面；多根带状引脚的底面也暴露于塑封层2320底面。步骤1920之后可追随步骤1922。
在步骤1922中，图26A和26B中的胶带接合于暴露底面2510。在本发明示例中,胶带2694由聚酰亚胺材料制成。步骤1922之后可追随步骤1924。
在步骤1924中，应用沿图27A和27B中的水平线2752和垂直线2754的切割分离过程。在切割分离过程之后形成半导体封装2700、2702、2704和2706。应用切割分离过程之后，图27B中多根带状引脚2120之一的第一带状引脚部分2125和其中之一的第二带状引脚部分2127得到电气隔离，并分离形成两个不同的半导体封装，且在切割分离过程期间拆除图21B中的垂直长条2129。每组引脚因而均于水平线一端得到连接。
在本发明示例中,图27A和27B显示于从切割胶带2694处拆除之前的半导体封装2700。半导体封装2700包含封装第一侧的第一带状引脚部分2125和第二侧的第二带状引脚部分2127、装入塑封层2320的多个分离半导体器件2230、暴露于塑封层2320底面(包含多个分离半导体器件2230的底部电极和第一带状引脚部分2125底面以及第二带状引脚部分2127)的第一多个铜垫2792、暴露于塑封层2320顶面(包含多个分离半导体器件2230的顶面电极和第一带状引脚部分2125顶面以及第二带状引脚部分2127)的第二多个铜垫2794以及塑封层2320顶面上的多个电气互连2486。塑封层2320装入大部分第一带状引脚部分2125和第二带状引脚部分2127，以及多个分离半导体器件2230。多个电气互连2486将多个分离半导体器件2230接入第一带状引脚部分2125和第二带状引脚部分2127的多个引脚组，使之通过第二多个铜垫2794。
在本发明示例中，整体多个电气互连2486处于塑封层2320上方。
在本发明示例中，多个半导体器件包含第一金属氧化物半导体场效应晶体管(MOSFET)2240和第二MOSFET 2250。第一MOSFET 2240为低端(LS)MOSFET且被翻转。第一MOSFET 2240具有第一MOSFET 2240底面上的源电极2242和栅电极2244以及第一MOSFET2240顶面上的漏电极2246。在本发明示例中，第二MOSFET 2250为高端(HS)MOSFET。第二MOSFET 2250具有其顶面上的源电极2252和栅电极2254以及第二MOSFET 2250底面上的漏电极2256。
在本发明示例中，第二MOSFET 2250的漏电极2256、第一MOSFET 2240的源电极2242和第一带状引脚部分2125和/或第二带状引脚部分2127的第一预定部分2191通过塑封层2320上方多个电气互连2486的第二部分2183得到连接；其中，第二MOSFET的栅电极通过塑封层2320上方多个电气互连2486的第二部分2183接入第一带状引脚部分2125的第二预定部分2193(2125A)。
在本发明示例中，半导体封装2700不包含电线(例如：9,754,864号美国专利图6A中的电线)。半导体封装2700不包含夹子(例如：9,754,864号美国专利图6B中的夹子)。未将芯片焊盘用于芯片焊接，因而底部电镀铜电极通过封装底面暴露于外。
专业技艺一般的那些人会认可：于此可以执行披露实施的修正。例如：半导体封装中的半导体器件总数可发生变化。也可能发生为专业技艺一般的那些人所认可的其他修正，且所有这类修正都被视为落入为要求所定义的本发明范围以内。

Claims (20)

1.一种制造半导体封装的方法，其特征在于，包含如下步骤：
提供一可拆卸载体；
在所述可拆卸载体顶面上形成多根支柱；
将多个半导体器件固定至可拆卸载体顶面；
形成第一塑封层包围多根支柱的大部分和多个半导体器件的大部分，以使所述多根支柱的顶面和所述多个半导体器件的顶面电极暴露于第一塑封层的顶面；
在第一塑封层的顶面上涂覆第一光阻层；
在第一曝光过程中，应用第一图案掩蔽，形成第一光阻图案；
在第一塑封层暴露顶面和多个半导体器件的顶面电极上涂覆第一再分布层(RDL)，形成第一多个电气互连；
清除所述第一光阻图案；
形成第二塑封层包覆所述第一多个电气互连；
拆除所述可拆卸载体；
在第一塑封层底面和多个半导体器件上涂覆第二光阻层；
在第二曝光过程中，应用第二图案掩蔽，形成第二光阻图案；
在第一塑封层暴露底面和多个半导体器件上涂覆第二再分布层(RDL)，形成第二多个电气互连；以及
清除所述第二光阻图案。
2.如权利要求1所述的制造半导体封装的方法，其特征在于，
所述可拆卸载体由不锈钢材料制成；所述多根支柱由铜材料制成。
3.如权利要求2所述的制造半导体封装的方法，其特征在于，
所述多个半导体器件包括：
一集成电路(IC)；
一第一金属氧化物半导体场效应晶体管MOSFET；以及
一第二MOSFET。
4.如权利要求3所述的制造半导体封装的方法，其特征在于，
第一MOSFET包含其顶面上的一栅电极和一源电极；且
第二MOSFET包含第二MOSFET底面上的一栅电极和一源电极。
5.如权利要求1所述的制造半导体封装的方法，其特征在于，
形成第一塑封层的步骤进一步包含形成第一包覆成型封装，随后是磨削或研磨第一包覆成型封装顶部的步骤。
6.如权利要求1所述的制造半导体封装的方法，其特征在于，
还包含涂覆第一种晶层于第一塑封层的顶面；且在清除所述第一光阻图案的步骤之后，进一步包含清除第一种晶层。
7.如权利要求6所述的制造半导体封装的方法，其特征在于，
在将所述第二光阻层涂覆于第一塑封层底面和多个半导体器件之上这一步骤前，还包括
将第二种晶层涂覆于第一塑封层底面和多个半导体器件之上；且
在清除所述第二光阻图案这一步骤之后，进一步包括清除第二种晶层。
8.如权利要求1所述的制造半导体封装的方法，其特征在于，
在清除所述第二光阻图案这一步骤之后，还包括应用切割分离过程，形成半导体封装。
9.如权利要求1所述的制造半导体封装的方法，其特征在于，
所述多根支柱的高度稍大于或等于多个半导体器件的厚度。
10.如权利要求1所述的制造半导体封装的方法，其特征在于，
所述第一塑封层的厚度基本上等于多个半导体器件的厚度。
11.一种半导体封装，其特征在于，包含：
多根支柱；
多个半导体器件；
第一塑封层，包围多根支柱的大部分和多个半导体器件的大部分；
布置于第一塑封层顶面上的第一多个电气互连，将所述多根支柱电气连接至所述多个半导体器件；
第二塑封层，包覆所述第一多个电气互连；和
布置于第一塑封层底面上的第二多个电气互连，将所述多根支柱电气连接至所述多个半导体器件；
所述第二塑封层的底面直接接合在第一塑封层顶面。
12.如权利要求11所述的半导体封装，其特征在于，
整个所述第一多个电气互连嵌入所述第二塑封层；且
所述第二多个电气互连暴露于第一塑封层底面。
13.如权利要求11所述的半导体封装，其特征在于，
所述第一塑封层的硬度大于所述第二塑封层的硬度。
14.如权利要求13所述的半导体封装，其特征在于，
第一塑封层包括第一百分比的玻璃充填；
第二塑封层包括第二百分比的玻璃充填；
玻璃充填的第一百分比大于玻璃充填的第二百分比。
15.如权利要求11所述的半导体封装，其特征在于，
所述第一塑封层和所述第二塑封层由同一材料制成。
16.如权利要求11所述的半导体封装，其特征在于，
所述多个半导体器件包括：
一集成电路(IC)；
一第一金属氧化物半导体场效应晶体管MOSFET；和
一第二MOSFET。
17.如权利要求16所述的半导体封装，其特征在于，
第一MOSFET包含其顶面上的一栅电极和一源电极；且第二MOSFET包含第二MOSFET底面上的一栅电极和一源电极。
18.如权利要求16所述的半导体封装，其特征在于，
布置于第一塑封层顶面上的第一多个电气互连由电镀铜材料构成；且第二MOSFET顶上的电镀铜层厚度为40至100微米，第一塑封层顶上的电镀铜层厚度为20至50微米。
19.如权利要求18所述的半导体封装，其特征在于，
第二MOSFET顶上电镀铜层的厚度不大于第一塑封层顶上电镀铜层厚度的两倍。
20.如权利要求18所述的半导体封装，其特征在于，
布置于第一塑封层底面上的第二多个电气互连由电镀铜材料构成；
第一MOSFET底上的电镀铜层厚度为40至100微米；
第一塑封层底面上的电镀铜层厚度为20至50微米；
且第一MOSFET底上的电镀铜层厚度不大于第一塑封层底面上电镀铜层厚度的两倍。
CN201911271514.XA 2018-12-18 2019-12-12 半导体封装和制作半导体封装的方法 Pending CN111341734A (zh)

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