CN111211087A - 具有改进的栅极电荷的功率半导体晶体管 - Google Patents
具有改进的栅极电荷的功率半导体晶体管 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000002955 isolation Methods 0.000 claims description 58
- 239000000463 material Substances 0.000 claims description 34
- 210000000746 body region Anatomy 0.000 claims description 28
- 238000009825 accumulation Methods 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims 3
- 238000000034 method Methods 0.000 description 19
- 230000007704 transition Effects 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 238000005530 etching Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
提供了一种具有改进的栅极电荷的功率半导体晶体管。该晶体管包括:衬底;在所述衬底上的绝缘层;以及在所述绝缘层上的栅电极层;其中,所述栅电极层包括穿过所述栅电极层到所述绝缘层的顶表面的一个或更多个开口。
Description
本申请是申请日为2015年3月18日,申请号为201510118084.3,发明名称为“具有改进的栅极电荷的功率半导体晶体管”的中国发明专利申请的分案申请。
技术领域
本公开内容总体上涉及半导体器件技术领域,并且具体地涉及具有开槽栅极结构(slotted gate structure)的横向扩散金属氧化物半导体场效应晶体管(LDMOS)以及其制造方法。
背景技术
电压稳压器,例如DC至DC转换器,提供用于电子系统的稳定电压源。低功率器件尤其需要有效的DC至DC转换器。其中一种类型的DC至DC转换器是开关式电压稳压器。开关式电压稳压器通过交替地将输入DC电压源和负载耦接和去耦接来生成输出电压。耦接动作和去耦接动作能够通过开关来执行,同时包括电容器和电感器的低通滤波器能够用于对开关的输出进行滤波,以提供DC输出电压。
图1示出了能够执行DC至DC降压转换的“降压(buck)”型开关稳压器的示例性实施方式。例如,参考图1,电路100包括:电压源103、开关稳压器102和负载113。开关式稳压器102通过输入端子114耦接至电压源103。开关式稳压器102还耦接至负载113,该负载113可以是经由输出端子112来汲取电流的另一电路。开关式稳压器102包括开关电路116,该开关电路116用作为用于交替地将输入端子114与中间端子109耦接和去耦接的功率开关。开关电路116包括第一晶体管107和第二晶体管108。通常晶体管107和晶体管108都能够实现为金属氧化物半导体场效应晶体管(MOSFET)。晶体管107具有连接至输入端子114的漏极,连接至中间端子109的源极,以及连接至控制线105的栅极。晶体管108具有连接至中间端子109的漏极,连接至低电压电位115(例如,接地)的源极,以及连接至控制线106的栅极。
开关稳压器102包括经由控制线105和控制线106控制开关电路116的操作的控制器104。开关式稳压器102还具有输出滤波器117,该输出滤波器117包括连接在中间端子109和输出端子112之间的电感器110以及与负载113并联连接的电容器111。控制器104使开关电路116在第一导通时段与第二导通时段之间交替,其中,在所述第一导通时段内,使第一晶体管107生效而第二晶体管108失效,以使中间端子109处于基本上等于输入电压的电压,在所述第二导通时段内,使第一晶体管107失效而第二晶体管108生效,以使中间端子109处于基本上等于低电压电位115的电压的电压。这产生在中间端子109处的矩形波形,该矩形波形基本上在输入电压与等于电压电位115的电压之间切换(toggle)。中间端子109经由输出滤波器117耦接至输出端子112。输出滤波器117将中间端子109处的矩形波形转换为输出端子112处的基本DC电压。在端子112处的输出DC电压的大小取决于中间端子109处的矩形波形的占空比。
随着BCD(双极型-CMOS-DMOS)技术的广泛使用,将控制器104、开关电路116和高精度反馈电路(图1中未示出)集成在同一芯片上是普遍的。在具有10V至200V的输入工作范围的大部分单片集成开关稳压器中,横向双扩散MOSFET(LDMOS)功率器件被用作开关元件。
图2示出了常规LDMOS器件的透视图。如图2所示,LDMOS器件200包括掺杂有P型材料或N型材料的衬底202。在衬底202之上,器件200具有掺杂有与衬底202相同类型材料的主体区203。器件200还包括掺杂有与主体区203相反类型材料(例如,如果主体区203为P型,则掺杂N型)的漂移区208。隔离区205,其可以是例如浅沟槽隔离(STI)区的氧化物填充沟槽,被形成在漂移区208内。器件200还包括源极区206和漏极区209,源极区206和漏极区209中的每一个掺杂有与主体区203相反类型材料。通过耦接至漏极区209的漏极端子215来达到(access)漏极。器件200还包括邻接源极区206的主体接触区204。邻接的区204和区206掺杂有相反类型的材料。区204和区206利用共享接触(shared contact)而被连接在一起,通过主体/源极端子214来达到该共享接触。器件200还包括栅极201,该栅极201包括栅电极层207(例如由多晶硅构成),栅极端子216,以及在栅电极层207下方的例如二氧化硅的绝缘层(图2中未示出)。绝缘层与区211重叠以形成沟道,并且与区202和区212重叠以形成积累区、过渡区或颈区(neck region)。绝缘层从源极区206的边缘延伸至与隔离区205重叠。重叠区通常被称为场板区(field plate region)(图2中表示为213)。
对于图2中所示的构造,在被称为反转的过程中,向栅极端子216施加正确极性的偏压能够导致在栅极氧化物之下的区211处形成电荷承载沟道(charge-carryingchannel),在该区211处,栅极201与主体区203重叠。端子214可以用作LDMOS器件的源极。可以通过向漏极端子215施加偏压来启动从漏极至源极的电流。在器件导通时,来自沟道211的沟道反转电荷通过过渡区212和隔离区205下的漂移区208流至漏极区209,并且然后流出漏极端子215。
在图2中的LDMOS器件200中,漂移区208能够容许高的截止状态漏极-源极电压,该漂移区208与沟道间隔开积累或过渡区。过渡区是在对器件导通电阻和击穿进行优化时的重要的设计参数。然而,因为过渡区被通常薄的栅极氧化物覆盖,所以过渡区引入相当大的密勒电容,并且构成整个栅极电荷的重要部分,其导致转换器电路中的大的开关损耗。存在用于减小密勒电容的先前尝试。例如,McGregor于2009年11月13日提交的题目为“MOSPower Transistor”的美国专利申请公开第2011/0115018号(在下文中称为“McGregor”)介绍了分裂栅极结构。虽然McGregor中的技术减少了在漂移区和过渡区上方的栅极面积,但是在McGregor中剩余的场板(通过分裂栅极而形成)需要到源极的额外线路连接。这使内部器件布线复杂,并且由于将漏极电容耦合至场板和源极而引入额外的输出电容。
因此,需要以下技术:该技术减小功率MOSFET(特别是LDMOS器件)的栅极电容,并且在其试图减小输入电容时也不需要额外布线,不会增加额外的器件输出电容。
发明内容
本公开内容的实施方式的另外方面和优点一部分将在随后描述中给出,一部分将在下面的描述中变得明显,或者可以通过本公开内容的实施方式的实践而获知。
根据一些实施方式,一种晶体管包括:衬底;在衬底上的栅极氧化物层以及在栅极氧化物层上的栅电极层;第一端子区;第二端子区;在栅极氧化物层下方的沟道区;以及在第二端子区与沟道区之间的积累区。栅电极层包括在积累区上方的一个或更多个开口。晶体管还包括在栅极氧化物层下方的漂移区。在一些实施方式中,晶体管还包括在栅极氧化物层下方的隔离区。在一些实施方式中,隔离区包括浅沟槽隔离(STI)区,或通过硅的局部氧化(LOCOS)而形成的区。在一些实施方式中,晶体管还包括在隔离区上方的一个或更多个开口。在一些实施方式中,开口被限定在栅电极层内。在一些实施方式中,晶体管的栅电极层上的所有区域在没有外部布线的情况下被电连接。
根据一些实施方式,一种晶体管包括:衬底;在衬底上的栅极氧化物层以及在栅极氧化物层上的栅电极层;第一端子区;第二端子区;在栅极氧化物层下方并且与第一端子区邻近的主体区;在栅极氧化物层下方并且与第二端子区邻近的漂移区;以及在漂移区上并且与第二端子区邻近的隔离区。栅电极层包括在主体区与隔离区之间的区域上方的一个或更多个开口。在一些实施方式中,隔离区包括浅沟槽隔离(STI)区。在一些实施方式中,隔离区包括通过硅的局部氧化(LOCOS)而形成的区。在一些实施方式中,晶体管还包括在隔离区上方的一个或更多个开口。
根据一些实施方式,一种用于制造晶体管的方法包括:在衬底中对第一区和第二区进行掺杂;在第二区中形成隔离区;在衬底上沉积栅极氧化物层;在栅极氧化物层上沉积栅电极层;以及在栅电极层上蚀刻一个或更多个开口。开口至少与形成第二区的衬底的部分重叠。在一些实施方式中,该方法还包括对第一区中的区域进行掺杂以形成源极区,以及对第二区中的区域进行掺杂以形成漏极区。在一些实施方式中,该方法还包括在对第一区中的区域进行掺杂以形成源极区以及对第二区中的区域进行掺杂以形成漏极区的同时,对所述一个或更多个开口进行遮挡,以防止掺杂剂进入开口。在一些实施方式中,在第二区中形成隔离区包括蚀刻沟槽以及使用氧化物填充沟槽,以形成隔离区。在一些实施方式中,在第二区中形成隔离区包括在所选区域处生长氧化物,以形成隔离区。在一些实施方式中,所述一个或更多个开口形成在第一区与隔离区之间的第二区的至少一部分上方。在一些实施方式中,该方法还包括在隔离区上方蚀刻一个或更多个开口。
附图说明
根据参考附图进行的以下描述,本公开内容的实施方式的这些和其他方面和优点将变得明显并且更容易理解,其中:
图1为现有技术降压(Buck)开关式稳压器的框图;
图2示出了常规LDMOS器件的透视图;
图3示出了根据本公开内容的实施方式的开槽栅极LDMOS器件的透视图;
图4示出了根据本公开内容的另一实施方式的开槽栅极LDMOS器件的透视图;
图5示出了常规LDMOS器件(例如图2所示的)的栅极电荷曲线,以及根据本公开内容的实施方式的开槽栅极LDMOS的栅极电荷曲线;
图6示出了根据本公开内容的另一实施方式的开槽栅极LDMOS器件的透视图;
图7示出了根据本公开内容的又一实施方式的开槽栅极LDMOS器件的透视图;以及
图8示出了用于制造根据本公开内容的实施方式的LDMOS器件的过程的流程图。
具体实施方式
将详细参考本公开内容的实施方式。本文中参考附图描述的实施方式是说明性的、解释性的,并且用于总体上理解本公开内容。实施方式不应被解释为限制本公开内容。贯穿说明书用相同的附图标记来表示相同或相似的元件或具有相同或相似功能的元件。在这点上,参考所描述的附图的定向来使用例如“顶”、“底”、“前”、“后”、“前导”、“尾随”等的方向性术语。因为本公开内容的实施方式的部件可以以许多不同的定向来定位,所以以说明为目的而使用方向性术语,并且方向性术语不是限制性的。应当理解的是可以利用其他实施方式,并且可以在不脱离本公开内容的范围的情况下进行结构或逻辑上的变化,包括改变过程步骤的顺序。
实施方式的描述仅是示例性的,并且不意味着限制。
图3示出了根据本公开内容的实施方式的开槽栅极LDMOS 300的透视图。如图3所示,器件300包括可以掺杂有P型材料或N型材料的衬底302。在衬底302之上,器件300包括可以掺杂有与衬底302相同类型材料的主体区303。器件300还包括可以掺杂有与主体区303相反类型材料(例如,如果主体区303为P型,则掺杂N型)的漂移区308。在漂移区308内可以形成有隔离区305,在一些实施方式中,该隔离区305可以是填充有氧化物的浅沟槽隔离(STI)。器件300还可以包括第一端子区和第二端子区,例如源极区306和漏极区309,它们中的每一个掺杂有与主体区303相反类型的材料。器件300还可以包括邻接源极区306的主体接触区304。主体接触区304和源极区306掺杂有相反类型材料。能够通过耦接至漏极区309的漏极端子315来达到漏极,而主体接触区304和源极区306可以利用共享接触而被连接在一起,可以通过主体/源极端子314来达到该共享接触。器件300还包括栅极301,该栅极301包括:通常由多晶硅构成的栅电极层307;栅极端子316;以及在栅电极层307下方的例如二氧化硅的绝缘层(图3中未示出)。绝缘层与区311重叠以形成沟道,与区302和区312重叠以形成积累区、过渡区或颈区。在一些实施方式中,栅极301可以与区303、区302、区308和区305的至少一部分重叠。栅极301与STI区305重叠的部分可以称为场板区(图3中表示为313)。
在一些实施方式中,器件300可以是N沟道LDMOS,其中主体区303和主体接触区304掺杂有P型材料,而漂移区308、源极区306和漏极区309掺杂有N型材料。在一些其他实施方式中,器件300可以是P沟道LDMOS,其中主体区303和主体接触区304掺杂有N型材料,而漂移区308、源极区306和漏极区309掺杂有P型材料。
如图3所示,器件300还可以包括在栅极301下面在主体区303中的沟道区311。当在栅极端子316处向栅极301施加电压时,在沟道区311中可以形成导电沟道。端子314可以用作器件300的源极。可以通过向漏极端子315施加偏压来启动从漏极至源极的电流。在器件导通时,来自沟道311的沟道反转电荷可以通过过渡区和STI区305下的漂移区308流至漏极区309,并且然后流出漏极端子315。
在一些实施方式中,栅极301可以包括在区312上方在栅电极层307中的开口340、开口341和开口342。如图3所示,在一些实施方式中,栅电极层307的所有区域被连接而不需要额外布线和外部布线。换言之,在图3所示的示例性的实施方式中,在栅电极层307上没有需要额外线路连接的、与剩余区域分隔开的区域。在一些示例性的实施方式中,开口340、开口341和开口342被限定在栅电极层307内,并且不延伸至栅电极层307的边缘。在一些其他实施方式中,开口340、开口341和开口342被限定在栅电极层307内,使得栅电极层307的两个相对侧(例如左侧和右侧)被连接。在一些实施方式中,开口340、开口341和开口342可以在STI区305的至少一部分上方延伸。在一些示例性的实施方式中,开口340、开口341和开口342具有基本上正方形形状。在整个多晶硅层上方保持了电连接性,而不需要额外布线和外部布线。本领域的普通技术人员应当理解的是,还可以使用其他形状和/或其他数量的开口。因为在开口中基本上没有栅极电荷,所以可以基本上减小密勒电容,该密勒电容包括在栅极301与过渡区之间的寄生电容,并且还可以基本上减小开关损耗。
图4示出了根据本公开内容的另一实施方式的开槽栅极LDMOS 400的透视图。如图4所示,器件400包括可以掺杂有P型材料或N型材料的衬底402。在衬底402之上,器件400包括可以掺杂有与衬底402相同类型材料的主体区403。器件400还包括可以掺杂有与主体区403相反类型材料(例如,如果主体区403为P型,则掺杂N型)的漂移区408。在漂移区408内可以形成隔离区405,在一些实施方式中,该隔离区405可以通过硅的局部氧化(LOCOS)而形成。器件400还可以包括第一端子区和第二端子区,例如源极区406和漏极区409,它们中的每一个掺杂有与主体区403相反类型的材料。器件400还可以包括邻接源极区406的主体接触区404。邻接的区404和区406可以掺杂有相反类型材料。能够通过耦接至漏极区409的漏极端子415来达到漏极,而主体接触区404和源极区406可以利用共享接触而被连接在一起,可以通过主体/源极端子414达到该共享接触。器件400还包括栅极401,其中栅极401包括:例如由多晶硅构成的栅电极层407;栅极端子416;以及在栅电极层407下方的例如氧化物的绝缘层(图4中未示出)。绝缘层与区411重叠以形成沟道,与区402和区412重叠以形成积累区、过渡区或颈区。在一些实施方式中,栅极401可以与区403、区402、区408和区405的至少一部分重叠。栅极401与LOCOS区405重叠的一部分可以称为场板区(图4中表示为413)。
在一些其他实施方式中,器件400可以是N沟道LDMOS,其中主体区403和主体接触区404掺杂有P型材料,而漂移区408、源极区406和漏极区409掺杂有N型材料。在一些其他实施方式中,器件400可以是P沟道LDMOS,其中主体区403和主体接触区404掺杂有N型材料,而漂移区408、源极区406和漏极区409掺杂有P型材料。
如图4所示,器件400还可以包括在栅极401下面在主体区403中的沟道区411。当在栅极端子416处向栅极401施加电压时,在沟道区411中可以形成导电沟道。端子414可以用作器件400的源极。可以通过向漏极端子415施加偏压来启动从漏极至源极的电流。在器件导通时,来自沟道411的沟道反转电荷可以通过过渡区和LOCOS区405之下的漂移区408流至漏极区409,并且然后流出漏极端子415。
在一些实施方式中,栅极401可以包括在区412上方在栅电极层407中的开口440、开口441和开口442。如图4所示,在一些其他实施方式中,栅电极层407的所有区域被连接而不需要额外布线和外部布线。换言之,在图4所示的示例性的实施方式中,在栅电极层407上没有需要额外线路连接的、与剩余区域分隔开的区域。在一些示例性的实施方式中,开口440、开口441和开口442被限定在栅电极层407内,并且不延伸至栅电极层407的边缘。在一些其他实施方式中,开口440、开口441和开口442被限定在栅电极层407内,使得栅电极层407的两个相对侧(例如左侧和右侧)被连接。在一些实施方式中,开口440、开口441和开口442可以在LOCOS区405的至少一部分上方延伸。在一些示例性的实施方式中,开口440、开口441和开口442具有基本上正方形形状。在整个多晶硅层上方保持了电连接性,而不需要额外布线和外部布线。本领域的普通技术人员应当理解的是,还可以使用其他形状和/或其他数量的开口。因为在开口中基本上没有栅极电荷,所以可以基本上减小密勒电容,该密勒电容包括栅极401与过渡区之间的寄生电容,并且还可以基本上减小开关损耗。
图5示出了常规LDMOS(例如图2所示的)的栅极电荷曲线501,以及根据本公开内容的实施方式的开槽栅极LDMOS器件的栅极电荷曲线500。栅极电荷曲线示出了在LDMOS器件开关时LDMOS器件的栅极电压的变化。可以通过以下步骤针对独立LDMOS器件来生成这样的曲线:经由负载电阻将LDMOS器件的漏极连接至标称电源电压;将LDMOS器件的源极连接至低电位(例如,接地);以及将恒定的充电电流提供至LDMOS器件的栅极。所述电流可以用于对栅极电容进行充电,并且可以记录栅极电压随时间的变化。如图5所示,常规的器件和开槽栅极器件都具有约1.7伏特的阈值电压。在栅极电荷曲线中有三个阶段。在第一阶段中,因为栅极至源极的电容正在被充电,所以存在着Vgs(栅极电压)相对于时间的基本上线性增加。一旦栅极电压达到用于沟道形成的阈值电压,栅极至漏极的密勒电容将被充电的第二阶段开始。在第二阶段期间(也被称为稳定(plateau)阶段),如图5所示,Vgs相对恒定。因为所储存的电荷量基本上等于稳定区的持续时间tplateau与栅极充电电流Ig的乘积,所以该稳定区的持续时间tplateau影响Qgd(密勒电容中所储存的电荷量)。如图5所示,因为密勒电容的减小,开槽栅极器件的稳定区的持续时间为约0.7毫秒,小于常规器件的稳定区持续时间。当器件开始传导时第三阶段开始,栅极至沟道的反转电容将被充电,并且Vgs重新开始增加。一旦栅极完全达到其额定值(在这种情况下为5伏特),这个阶段结束,并且器件完全导通。最终对于开槽栅极器件的充电过程比对于常规器件的充电过程早停止约1.5毫秒,这是由于减小的栅极至漏极密勒电容,其导致完全导通栅极所需要的总栅极电荷的总体减小。
图6示出了根据本公开内容的另一实施方式的开槽栅极LDMOS 600的透视图。如图6所示,除了图6中的实施方式包括在STI区305上方在多晶硅层307上的附加开口640、开口641和开口642之外,该实施方式与图3中所示的实施方式相似。图6和图3中的相同元件由相同的附图标记来表示并且不再描述。
图7示出了根据本公开内容的又一实施方式的开槽栅极LDMOS 700的透视图。如图7所示,除了图7中的实施方式包括在LOCOS区405上方在多晶硅层407上的附加开口740、开口741和开口742之外,该实施方式与图4中所示的实施方式相似。图7和图4中的相同元件由相同的附图标记表示并且不再描述。
图8是示出了用于制造根据本公开内容的实施方式的半导体器件(例如图3-7的LDMOS器件)的过程的流程图。例如,参考图3和图8,在步骤800中,准备硅晶片,并且通过使用N型材料或P型材料对其进行掺杂来形成衬底。在步骤801中,形成第一掺杂区和第二掺杂区。第一掺杂区可以是主体区303,而第二掺杂区可以是漂移区308。在步骤802中,可以在漂移区之上形成STI区或LOCOS区。例如,可以通过在衬底中蚀刻沟槽并且用氧化物填充沟槽来形成STI区。可以通过在所选区域处生长氧化物来形成LOCOS区。在步骤803中,在硅晶片之上沉积栅极氧化物。在步骤804中,在栅极氧化物之上沉积多晶硅层,以形成层307。在步骤805中,通过例如在例如区312上方在多晶硅层307中进行蚀刻来限定开口。在步骤806中,在第一掺杂区中形成源极区和主体接触区,并且通过对衬底中的所选区域进行掺杂,在第二掺杂区中形成漏极区。
贯穿本说明书,提及“实施方式”、“一些实施方式”、“一个实施方式”、“另一示例”、“一个示例”、“具体示例”或“一些示例”意味着结合该实施方式或示例描述的特定特征、结构、材料或特性被包括在本公开内容的至少一个实施方式或示例中。因此,在本说明书的各种位置出现例如“在一些实施方式中”、“在一个实施方式中”、“在实施方式中”、“在另一示例中”、“在示例中”、“在具体示例中”或“在一些示例中”的术语不一定指的是本公开内容的同一实施方式或示例。此外,特定特征、结构、材料或特性可以以任何合适的方式结合在一个或更多个实施方式或示例中。
虽然已经示出和描述了说明性的实施方式,但是本领域的普通技术人员应该理解上述实施方式不能被解释为限制本公开内容,并且在不脱离本公开内容的精神、原则和范围的情况下,可以对实施方式做出改变、替换和修改。
此外,本发明还可以被配置如下:
1.一种晶体管,包括:
衬底;
在所述衬底上的栅极氧化物层,以及在所述栅极氧化物层上的栅电极层;
第一端子区;
第二端子区;
在所述栅极氧化物层下方的沟道区;以及
在所述第二端子区与所述沟道区之间的积累区,其中,所述栅电极层包括在所述积累区上方的一个或更多个开口。
2.根据1所述的晶体管,还包括在所述栅极氧化物层下方的漂移区。
3.根据2所述的晶体管,还包括在所述栅极氧化物层下方的隔离区。
4.根据3所述的晶体管,其中,所述隔离区包括浅沟槽隔离STI区。
5.根据3所述的晶体管,其中,所述隔离区包括通过硅的局部氧化LOCOS而形成的区。
6.根据3所述的晶体管,还包括在所述隔离区上方的一个或更多个开口。
7.根据3所述的晶体管,其中,所述一个或更多个开口在所述隔离区的至少一部分上方延伸。
8.根据1所述的晶体管,其中,所述一个或更多个开口被限定在所述栅电极层内。
9.根据1所述的晶体管,其中,所述栅电极层上的所有区域在没有外部布线的情况下被电耦接。
10.一种用于制造晶体管的方法,包括:
在衬底内对第一区和第二区进行掺杂;
在所述第二区中形成隔离区;
在所述衬底上沉积栅极氧化物层;
在所述栅极氧化物层上沉积栅电极层;以及
在所述栅电极层上蚀刻一个或更多个开口,其中,所述开口至少与形成所述第二区的所述衬底的部分重叠。
11.根据10所述的方法,还包括:对所述第一区中的区域进行掺杂以形成源极区,以及对所述第二区中的区域进行掺杂以形成漏极区。
12.根据11所述的方法,还包括:在对所述第一区中的区域进行掺杂以形成源极区以及对所述第二区中的区域进行掺杂以形成漏极区的同时,对所述一个或更多个开口进行遮挡,以防止掺杂剂进入所述开口。
13.根据10所述的方法,其中,在所述第二区中形成隔离区包括蚀刻沟槽以及使用氧化物填充所述沟槽,以形成所述隔离区。
14.根据10所述的方法,其中,在所述第二区中形成隔离区包括在所选区域处生长氧化物,以形成所述隔离区。
15.根据10所述的方法,其中,所述一个或更多个开口在所述第一区与所述隔离区之间的所述第二区的至少一部分上方。
16.根据15所述的方法,还包括在所述隔离区上方蚀刻一个或更多个开口。
17.一种晶体管,包括:
衬底;
在所述衬底上的栅极氧化物层,以及在所述栅极氧化物层上的栅电极层;
第一端子区;
第二端子区;
在所述栅极氧化物层下方并且与所述第一端子区邻近的主体区;
在所述栅极氧化物层下方并且与所述第二端子区邻近的漂移区;以及
在所述漂移区上并且与所述第二端子区邻近的隔离区,其中,所述栅电极层包括在所述主体区与所述隔离区之间的区域上方的一个或更多个开口。
18.根据17所述的晶体管,其中,所述隔离区包括浅沟槽隔离STI区。
19.根据17所述的晶体管,其中,所述隔离区包括通过硅的局部氧化LOCOS而形成的区。
20.根据17所述的晶体管,其中,所述栅电极层包括在所述隔离区上方的一个或更多个开口。
Claims (19)
1.一种晶体管,包括:
衬底;
在所述衬底上的绝缘层;以及
在所述绝缘层上的栅电极层;
其中,所述栅电极层包括穿过所述栅电极层到所述绝缘层的顶表面的一个或更多个开口。
2.根据权利要求1所述的晶体管,还包括在所述绝缘层下方的漂移区。
3.根据权利要求2所述的晶体管,还包括在所述绝缘层下方的隔离区。
4.根据权利要求3所述的晶体管,其中,所述隔离区包括浅沟槽隔离STI区。
5.根据权利要求4所述的晶体管,其中,所述STI区是单个连续的STI区。
6.根据权利要求3所述的晶体管,其中,所述隔离区包括通过硅的局部氧化LOCOS而形成的区。
7.根据权利要求3所述的晶体管,其中,所述栅电极层还包括在所述隔离区上方的一个或更多个开口。
8.根据权利要求3所述的晶体管,其中,所述一个或更多个开口中的一个开口的至少一部分直接与所述隔离区的至少一部分重叠。
9.根据权利要求1所述的晶体管,其中,所述栅电极层上的所有区域在没有外部布线的情况下被电耦接。
10.根据权利要求1所述的晶体管,其中,在操作期间所述一个或更多个开口减少所述晶体管的栅极电荷和密勒电容。
11.根据权利要求1所述的晶体管,其中,所述晶体管是横向扩散金属氧化物半导体场效应晶体管。
12.根据权利要求1所述的晶体管,其中,所述衬底被掺杂有P型材料和N型材料中的一种。
13.根据权利要求1所述的晶体管,其中,积累区的至少一部分包括P型材料和N型材料中的另外一种。
14.根据权利要求1所述的晶体管,其中,所述栅电极层具有在所述绝缘层上的侧边缘。
15.根据权利要求1所述的晶体管,还包括:
端子区;
在所述绝缘层下方的沟道区;以及
在所述端子区和所述沟道区之间的积累区,
其中,所述一个或更多个开口中的一个开口的至少一部分直接与所述积累区的至少一部分重叠。
16.一种晶体管,包括:
衬底;
在所述衬底上的绝缘层以及在所述绝缘层上的栅电极层;
第一端子区;
第二端子区;
在所述绝缘层下方并且与所述第一端子区邻近的主体区;
在所述绝缘层下方并且与所述第二端子区邻近的漂移区;以及
在所述漂移区上并且与所述第二端子区邻近的隔离区,
其中,
所述栅电极层包括穿过所述栅电极层到所述绝缘层的顶表面的一个或更多个开口,以及
所述一个或更多个开口中的一个开口的至少一部分直接与所述主体区和所述隔离区之间的区域的至少一部分重叠。
17.一种晶体管,包括:
衬底;
在所述衬底上的绝缘层以及在所述绝缘层上的栅电极层;
端子区;
在所述绝缘层下方的沟道区;以及
在所述端子区和所述沟道区之间的积累区,
其中,
所述栅电极层包括穿过所述栅电极层到所述绝缘层的顶表面的一个或更多个开口,
所述一个或更多个开口中的一个开口的至少一部分直接与所述积累区的至少一部分重叠,以及
所述一个或更多个开口在由所述栅电极层的边缘限定的区域之内。
18.一种晶体管,包括:
衬底;
在所述衬底上的绝缘层以及在所述绝缘层上的栅电极层;
第一端子区;
第二端子区;
在所述绝缘层下方并且与所述第一端子区邻近的主体区;
在所述绝缘层下方并且与所述第二端子区邻近的漂移区;以及
在所述漂移区上并且与所述第二端子区邻近的隔离区,
其中,
所述栅电极层包括穿过所述栅电极层到所述绝缘层的顶表面的一个或更多个开口,
所述一个或更多个开口中的一个开口的至少一部分直接与所述主体区和所述隔离区之间的区域的至少一部分重叠,以及
所述一个或更多个开口在由所述栅电极层的边缘限定的区域之内。
19.一种晶体管,包括:
衬底;
在所述衬底上的绝缘层以及在所述绝缘层上的栅电极层;
端子区;
在所述绝缘层下方并且与所述端子区邻近的漂移区;以及
在所述漂移区上并且与所述端子区邻近的隔离区,
其中,所述隔离区包括单个连续的浅沟槽隔离(STI)区。
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KR20210062765A (ko) * | 2019-11-21 | 2021-06-01 | 삼성전자주식회사 | Mos 구조를 포함하는 반도체 소자 |
CN113707715A (zh) * | 2020-05-21 | 2021-11-26 | 无锡华润上华科技有限公司 | 半导体器件 |
CN114429954A (zh) * | 2020-10-29 | 2022-05-03 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
CN114914293A (zh) * | 2022-05-30 | 2022-08-16 | 无锡沃达科半导体技术有限公司 | 一种双扩散mos晶体管结构及其制造方法 |
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- 2015-03-18 CN CN201911005869.4A patent/CN111211087B/zh active Active
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Also Published As
Publication number | Publication date |
---|---|
US9673319B2 (en) | 2017-06-06 |
HK1215469A1 (zh) | 2016-08-26 |
US20150270389A1 (en) | 2015-09-24 |
US20160197180A1 (en) | 2016-07-07 |
CN104934477A (zh) | 2015-09-23 |
CN104934477B (zh) | 2019-11-19 |
KR101925668B1 (ko) | 2018-12-05 |
US9306059B2 (en) | 2016-04-05 |
CN111211087B (zh) | 2024-01-02 |
KR20150110346A (ko) | 2015-10-02 |
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