CN111094621A - 用于印刷电路板的半加成方法 - Google Patents

用于印刷电路板的半加成方法 Download PDF

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Publication number
CN111094621A
CN111094621A CN201880058591.4A CN201880058591A CN111094621A CN 111094621 A CN111094621 A CN 111094621A CN 201880058591 A CN201880058591 A CN 201880058591A CN 111094621 A CN111094621 A CN 111094621A
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Prior art keywords
foil
copper
catalytic
exposed
thin
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CN111094621B (zh
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肯尼斯·S·巴尔
康斯坦丁·卡拉瓦克斯
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Sierra Circuits Inc
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Sierra Circuits Inc
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/429Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601Process or apparatus
    • C23C18/1633Process of electroless plating
    • C23C18/1646Characteristics of the product obtained
    • C23C18/165Multilayered product
    • C23C18/1653Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601Process or apparatus
    • C23C18/1633Process of electroless plating
    • C23C18/1689After-treatment
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    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/18Pretreatment of the material to be coated
    • C23C18/1803Pretreatment of the material to be coated of metallic material surfaces or of a non-specific material surfaces
    • C23C18/1813Pretreatment of the material to be coated of metallic material surfaces or of a non-specific material surfaces by radiant energy
    • C23C18/182Radiation, e.g. UV, laser
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    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
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    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/02Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material
    • C23C28/023Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material only coatings of metal elements only
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    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00Electroplating: Baths therefor
    • C25D3/02Electroplating: Baths therefor from solutions
    • C25D3/30Electroplating: Baths therefor from solutions of tin
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    • C25D3/00Electroplating: Baths therefor
    • C25D3/02Electroplating: Baths therefor from solutions
    • C25D3/38Electroplating: Baths therefor from solutions of copper
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    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02Electroplating of selected surface areas
    • C25D5/022Electroplating of selected surface areas using masking means
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    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10Electroplating with more than one layer of the same or of different metals
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    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/34Pretreatment of metallic surfaces to be electroplated
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    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
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    • C25D7/00Electroplating characterised by the article coated
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
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    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0026Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
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    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0026Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0038Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
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    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0047Drilling of holes
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    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/007Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
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    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H05K3/182Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
    • H05K3/184Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
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    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
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    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
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    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
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    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/425Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
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    • H05K3/46Manufacturing multilayer circuits
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    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
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    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
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    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
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    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/425Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern

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  • Manufacturing & Machinery (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Electrochemistry (AREA)
  • Mechanical Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • General Physics & Mathematics (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Chemically Coating (AREA)

Abstract

一种电路板具有电介质芯、箔顶表面和薄箔底表面,其中,箔背衬的厚度足以吸收来自激光钻孔操作的热量,以防止在激光钻孔期间贯穿薄箔底表面。执行一系列步骤,所述一系列步骤包括激光钻孔步骤、去除箔背衬步骤、化学镀步骤、图案化抗蚀剂步骤、电镀步骤、抗蚀剂剥离步骤、镀锡步骤、和铜蚀刻步骤,这些步骤提供了细线宽和分辨率的点通孔。

Description

用于印刷电路板的半加成方法
发明领域
本发明涉及电路板和相关的制造方法。具体而言,本发明涉及用于形成细间距通孔(vias)和相关细间距迹线的电路板和方法。
发明背景
现有技术的印刷电路板(PCB)是使用在介电衬底上形成的导电金属互连(被称为“迹线”)来形成的。在电路板上形成导电洞,以桥接介电衬底相对侧面上的迹线,其中,具有较大直径并可用于安装元件的导电洞被称为“穿孔(through holes)”,并且用于互连在相对侧面上的迹线的最小直径导电洞被称为“点通孔”(在迹线形成之前)或简称为“通孔”(在迹线形成之后)。每个承载迹线导体的表面被称为“层”,并且在一个表面上或两个表面上形成有迹线的每个介电衬底形成“基板(sub)”,基板是多层板的基本子组件。通过堆叠若干这样的基板(每个基板包括电介质芯,该电介质芯具有迹线和散布有裸介电层的互连通孔)并且在温度和压力下将基板层压在一起,可以形成多层印刷电路。介电衬底可以包括嵌在纤维基体(诸如被编织到布内的玻璃纤维)中的环氧树脂。
现有技术电路板制造的一个困难是形成深(高纵横比)通孔和细间距通孔。因为电镀操作消耗溶液中的金属离子,所以难以形成具有高纵横比的通孔,因为相比于在离金属离子浴附近并由循环离子浴补充的通孔的区域,离金属离子浴较远的通孔区域具有更低的金属离子沉积浓度。小直径通孔的直径类似地受到通孔的纵横比的限制,该纵横比由将要形成的电路层的厚度决定。盲通孔(其仅一端是开口)限制了在该通孔的封闭端处溶液中的金属离子的循环。
细间距电路板制造的另一个困难是在第一步中形成点通孔结构,在单独的步骤中形成穿孔,并且在随后的步骤中形成迹线。期望在单个电镀步骤中形成点通孔、通孔镀覆和迹线。还期望形成具有单层的纵横比但连续穿过多层的通孔,从而形成堆叠通孔。还期望提供一种方法,该方法提供直径减小的通孔和细间距迹线以用于制造细间距PCB。
发明目的
本发明的第一个目的是一种用于形成电路层的方法,该电路层具有点通孔、堆叠的通孔、穿孔和迹线,该方法利用电介质,该电介质具有施加到底表面的薄导电箔层和施加到薄导电箔的较厚的背衬箔层,该电路层任选地还具有与底表面相对地施加的顶表面导电箔,该电路层随后具有盲通孔钻孔步骤,由此,激光将电介质烧蚀至底部薄箔层的水平,背衬层去除来自底部箔的热量,以防止在激光烧蚀电介质期间贯穿或熔化薄箔,以及任选的用于钻出穿过板的所有层和箔层的孔的穿孔步骤,厚背衬箔去除步骤,在化学镀沉积步骤中在薄箔和暴露的电介质表面上化学镀沉积铜,在电路层的至少一个表面上施加图案抗蚀剂步骤,在未掩模的铜区域上沉积铜的电镀步骤,在暴露的铜区域上沉积掩模材料(诸如锡)的第二镀覆掩模步骤,抗蚀剂剥离步骤,以及用于去除未涂覆有第二镀覆材料(诸如锡)的化学镀沉积材料(诸如铜)的快速蚀刻步骤,以及用于去除第二镀覆掩模材料(诸如锡)的快速蚀刻步骤。
本发明的第二个目的是一种电路板,该电路板是通过以下方式制造的:将薄箔施加到电介质的底表面上,将厚背衬箔施加到底表面锡箔上,任选地将箔施加到与底表面相对的电介质的顶表面上,从顶表面开始穿过电介质并且向下直到底部薄箔进行激光钻孔或烧蚀材料但是不贯穿底部薄箔,通过作为散热器的背衬箔的厚度选择来防止底部薄箔的贯穿,之后去除背衬箔,之后对电路板进行化学镀,之后将图案化的抗蚀剂施加到至少一个表面,之后电镀电路板(该电镀可在电路板的暴露的铜上操作),之后用掩模材料(诸如锡)镀覆暴露的铜,之后对暴露的铜执行快速蚀刻以去除没有用掩模材料(诸如锡)镀覆的铜,之后任选地执行快速蚀刻以去除任何暴露的锡。
本发明的第三个目的是一种多层电路板,该多层电路板通过以下步骤形成:
由在顶表面和底表面上具有薄导电层的电介质形成内层,导电层具有施加到每个表面上的较厚的箔,从顶表面去除该较厚的箔,(诸如通过激光)钻出穿过顶部箔和电介质的孔以形成通孔洞,凭借底表面较厚的箔的散热能力防止激光钻出的通孔洞贯穿顶部箔,去除底表面较厚的箔,对暴露的电介质表面和箔表面进行化学镀,将抗蚀剂图案施加到顶表面和底表面,对没有由抗蚀剂覆盖的暴露的铜表面进行电镀,直到至少一个通孔洞被堵塞,对没有由抗蚀剂覆盖的暴露的铜表面进行镀锡,剥离光致抗蚀剂,充分快速蚀刻暴露的铜表面以去除先前由光致抗蚀剂覆盖的铜,并且任选地蚀刻镀锡;
向内层添加一对或更多对外层,
每个外层通过以下步骤形成:将用箔覆盖一个表面的电介质的非箔侧层压到内层,之后在至少一个外层上钻出至少一个通孔洞(该至少一个通孔洞实质上在内层填充通孔上方),之后对通孔洞和暴露的箔表面进行化学镀,之后施加图案掩模,之后电镀通孔洞和暴露的箔表面,之后对暴露的铜表面进行镀锡,之后剥离图案掩模,之后快速蚀刻在图案掩模下的箔和化学镀,直到箔和化学镀被去除为止,之后任选地剥离锡,从而形成新的内层,以用于随后待施加的外层。
发明概述
在本发明的第一实施例中,在电路板上形成至少一个通孔,电路板具有覆盖有底部薄铜箔的底表面和放置在底部薄铜箔上方的可移除铜背衬箔的相对厚的层,电路板任选地具有施加到与底表面相对的顶表面的顶表面薄铜箔,之后,电路板具有从顶表面至底部薄铜箔但不贯穿薄铜箔而形成的激光钻出的盲孔,铜背衬箔具有足够的厚度以防止激光产生的热量通过将热能耦合到背衬箔和背衬箔的周围区域而烧蚀第一薄铜箔。在完成钻(drill)孔或通孔洞之后,去除背衬箔。诸如通过使用催化电介质层压板或者通过在去胶渣(desmear)操作期间向暴露的通孔洞表面施加催化剂,使烧蚀的通孔洞和任何穿孔具有催化内表面。电路板随后暴露于金属离子(诸如铜)的化学镀浴中,该金属离子与存在于通孔洞中的催化微粒结合并扩散,直到在通孔洞表面和穿孔洞表面以及在铜箔区域中进行连续的沉积,产生用于随后的电镀的均匀的导电表面。接下来施加图案化的抗蚀剂,这防止来自后续电镀操作的沉积物在抗蚀剂覆盖的区域中形成。使用连续的导电表面和没有抗蚀剂的暴露区域,电路板在所执行的电镀步骤中用作电极,直到化学镀铜沉积达到光致抗蚀剂的深度或者达到通常小于光致抗蚀剂厚度的期望深度为止。镀锡步骤随后在暴露的铜表面上沉积锡,沉积的锡用作随后的铜蚀刻操作的蚀刻掩模,之后光致抗蚀剂被剥离,留下锡掩模的铜和暴露的铜。快速蚀刻暴露的铜去除了包括薄的底部铜箔和任选的顶部铜箔的暴露的铜,该顶部铜箔在图案化的光致抗蚀剂区域中。在快速蚀刻步骤中去除暴露的铜之后,留下未改变的锡掩模的铜,任选地,锡被蚀刻。得到的通孔被导电性地堵塞,并且在机械上比通过现有技术方法生产的通孔更小。
附图简述
图1A、图1B、图1C、图1D、图1E、图1F、图1G、图1H、图1I、图1J、图1K、图1L、图1M和图1N显示了用于形成多层板或两层电路板的内层的迹线和点通孔的标准线宽方法的处理步骤的截面图。
图2A、图2B、图2C、图2D、图2E、图2F、图2G、图2H、图2I和图2J显示了用于形成多层板或两层电路板的内层的迹线和点通孔的处理步骤的截面图。
图3A、图3B、图3C、图3D、图3E、图3F、图3G和图3H显示了多层细线宽方法的处理步骤的截面图。
图4A、图4B、图4C、图4D、图4E、图4F、图4G和图4H显示了用于使用催化层压在多层板或两层板的内层上形成迹线和通孔的处理步骤的截面图。
图5A、图5B和图5C显示了使用催化层压的多层板细线宽方法的处理步骤的截面图。
发明的详细描述
图1A显示了电介质102的截面,该电介质102具有大约0.3密耳(mil)(7.5u)厚的任选的顶表面箔104A和底表面箔104B。电介质102包括增强纤维和环氧树脂的混合物。许多不同的材料可用于预浸料的纤维,包括编织玻璃纤维布、碳纤维、或其他纤维,并且各种不同的材料可用于树脂,包括环氧树脂、聚酰亚胺树脂、氰酸酯树脂、PTFE(Teflon)共混树脂、或其他树脂。可以使用两种不同的镀覆技术执行导体(诸如铜)的沉积。在第一化学镀技术中,通过将树脂与吸引铜离子的催化微粒混合来形成电介质层。化学镀金属铜沉积的速率比电镀慢,但是沉积发生在所有暴露催化微粒的表面上以及暴露铜的表面上。镀覆提供了更快的铜沉积速率,因为它利用了将具有正电压的牺牲铜阳极置于电解质镀浴中,其中待镀覆的表面连接到负电压。铜作为金属离子,从阳极迁移并通过电解质到达阴极表面。在本例中,阴极表面是需要镀铜的PCB。电镀要求所有表面都具有共同的电势,这通常通过使用预先存在的铜箔或先前在具有暴露的催化微粒的电介质表面上的化学镀步骤来实现,直到在整个板上的连续电导率允许板用作阳极铜源所需的阴极为止。化学镀可以在0.06密耳(1.5u)到0.12密耳(3u)的范围内,以便为电镀提供足够的表面导电率。
虽然描述是针对使用用于化学镀铜形成的催化剂来形成铜通孔和迹线,但是应当理解,本发明的范围可以扩展到适用于化学镀和电镀的其他金属。对于铜(Cu)的化学沉积,元素钯(Pd)作为催化剂是优选的,然而所选择的周期表过渡金属元素(诸如第9至11族铂(Pt)、铑(Rh)、铱(Ir)、镍(Ni)、金(Au)、银(Ag)、钴(Co)、或铜(Cu))或这些的其它化合物(包括其它金属(诸如铁(Fe)、锰(Mn)、铬(Cr)、钼(Mo)、钨(W)、钛(Ti)、锡(Sn)))或上述项的混合物或盐中的任何一种都可以用作催化微粒。本候选列表旨在示例,而不是全部,在本领域已知也可以使用用于吸引铜离子的其他催化剂。在本发明的适用于催化层压板的一个示例中,催化微粒是均匀催化微粒。在本发明的形成催化层压板的另一个示例中,催化微粒是无机微粒或耐高温塑料微粒,其被涂覆有几埃厚度的催化金属,从而形成具有薄催化外表面的非均匀催化微粒,该催化外表面包封非催化内微粒。对于较大的催化微粒(诸如最长尺寸在25u的数量级的微粒),这个配方可能是合乎需要的。这个配方的非均匀催化微粒可以包括无机、有机、或惰性填料(诸如二氧化硅(SiO2))、无机粘土(诸如高岭土)、或者用催化剂涂覆在表面上的高温塑料填料(诸如钯通过气相沉积或化学沉积吸附到填料的表面上)。为了使催化微粒具有有助于化学镀的理想性质,仅仅需要几个原子层的催化剂。
在形成非均匀催化微粒的一个示例中,(有机的或无机的)填料镀浴按尺寸被分类以包括在尺寸上小于25u的微粒,这些经分类的无机微粒在槽中被混合到水镀浴中、被搅拌,且然后钯盐(诸如PdCl(或任何其它催化剂(诸如其它催化剂的银盐))在有酸(诸如HCl)的情况下和有还原剂(诸如水合肼)的情况下被引入,混合物从而减少涂覆无机微粒的金属Pd,提供涂覆在填料上的几埃厚度的Pd,从而与使用均匀Pd金属微粒相比,产生了具有均匀Pd微粒的催化性质的非均匀催化微粒,且极大地减小了对Pd的体积要求。然而,对于在几nm数量级的极小催化微粒,均匀催化微粒(诸如纯Pd)可能是优选的。
示例无机填料包括可以包含可变数量的铁、镁、碱金属、碱土金属和其他阳离子的粘土矿物,诸如水合铝硅酸盐。这一族的示例无机填料包括二氧化硅、硅酸铝、高岭石(Al2Si2O5(OH)4)、聚硅酸盐或属于高岭土或瓷土家族(kaolin or china clay family)的其他粘土矿物。示例有机填料包括PTFE(Teflon)和具有耐高温性的其他聚合物。
钯盐的示例有:BrPd、CL2Pd、Pd(CN)2、I2Pd、Pd(NO3)2*2H20、Pd(NO3)2、PdSO4、Pd(NH3)4Br2、Pd(NH3)4Cl2H2O。本发明的催化粉末还可以包含非均匀催化微粒(例如,涂覆在无机填料微粒上方的催化材料)、均匀催化微粒(诸如元素钯)、以及非催化微粒(选自无机填料族)的混合物。
在催化剂当中,钯由于比较经济性、可用性、和机械性质而是优选的催化剂,但是也可以使用其他催化剂。
该树脂可以是聚酰亚胺树脂、环氧树脂和氰化酯的混合物(其在高温下提供固化)或者具有在涂覆期间的可选择的粘度和在冷却后的热固性的任何其他合适的树脂配方。可以添加阻燃剂,例如以符合可燃性标准或者与预浸料的标准FR系列之一(诸如FR-4或FR-10)相容。对高速电路的附加要求是介电常数ε(电容率)以及损耗角正切δ,介电常数ε常常约为4并控制在电介质上形成的传输线的特征阻抗,并且损耗角正切δ是在一段距离上的频率相关的能量吸收的度量,由此,损耗角正切是电介质如何与高频电场相互作用以不合意地将信号振幅减小传输线长度的dB/cm的可计算的量的度量。该树脂与按尺寸分类的催化微粒混合。在一个示例配方中,催化微粒包括均匀催化微粒(金属钯)或非均匀催化微粒(涂覆在无机微粒或高温塑料上的钯)中的至少一个,并且对于任一配方,催化微粒优选地具有小于25u的最大范围,并且按总数计有50%的微粒尺寸在12u和25u之间或者在1-25u的范围内或者比25u更小。这些是示例催化微粒尺寸实施例,其并不意欲限制本发明的范围。在一个示例实施例中,催化微粒(均匀或非均匀)在1u-25u的尺寸范围内。在本发明的另一个例子中,通过将金属钯研磨成微粒并使因而得到的微粒通过具有带有25u矩形开口的网孔的筛子从而所有小于25u的催化微粒被选择来形成均匀催化微粒,并且研磨操作确定微粒在最小尺寸方向上的纵横比。小于2∶1的纵横比是优选的,但不限于本示例性实施例的范围,并且催化微粒可以是非均匀或均匀催化微粒。在另一个例子中,通过按重量比(诸如按重量基本上为12%的催化微粒与树脂的重量之比)将均匀或非均匀催化微粒混合到预浸渍树脂中,来形成催化树脂混合物106。在树脂混合物中的催化微粒按重量的比可以可选地在催化微粒重量相对于树脂的总重量的8-16%的范围内。应当理解,也可以使用其他混合比,并且使用更小的微粒可能是优选的。在本发明的一个例子中,选择催化微粒密度以提供在3u-5u的数量级的催化微粒之间的平均距离。
图1A电介质102面对顶部箔104A和底部箔104B。图1B显示了激光钻孔方法,由此通过施加高功率光能,形成洞106,诸如来自激光器高功率光能将箔104A和电介质102的温度升高到足以烧蚀(蒸发)铜102和电介质104,直到到达底表面104B为止。激光钻孔通常的纵横比(通孔深度除以直径)在大约0.5至1.0的范围内,该纵横比是为了成功的后续电镀而提供的。图1B中激光钻孔106的目的是提供小尺寸的通孔,以用于随后将由第一箔104B形成的迹线互连到第二箔104A。箔104B的厚度与迹线宽度相关,箔104A、104B越厚,所得迹线将越宽,并且迹线越宽,在后续迹线图案化步骤中使用的干膜就越厚。与薄铜箔104B的需求相矛盾的是散热需求,即底部铜箔104B具有足够的厚度以承受激光钻孔步骤106。因此,第一铜表面104B的厚度是由承受激光钻出孔106而不穿透下部箔104B所需的最小厚度决定的,这也限制了所得迹线的线宽和间距可以有多窄。
钻出孔和通孔用于去除表面铜和下层电介质可以通过激光烧蚀进行,其中催化预浸料的温度立即升高,直到催化预浸料被蒸发为止。可以优选的是使用有具有低反射率的波长(诸如紫外(UV)波长)和对于被烧蚀的预浸渍材料该光学波长高吸收的激光器。这种UV激光器的示例是UV准分子激光器或钇铝石榴石(YAG)激光器,其由于窄光束直径和高可用功率因此也是良好的选择,窄光束直径和高可用功率用于形成具有精确机械深度和界限分明的侧壁的通道。
对于非催化层压板,已钻出的通孔可以接受催化表面处理,即所谓的“去胶渣”,以实现化学镀。图中的典型去胶渣方法包括通过剧烈氧化去除残余物的高锰酸盐处理、中和高锰酸盐的中和剂处理、用于实现化学镀铜的表面催化剂(诸如钯)的施加,在此之后,有可能执行化学镀步骤,由此,通孔和穿孔表面涂覆有铜,以用于将顶部铜箔连接到底部铜箔。可选的,可以将催化微粒添加到电介质的树脂中,以形成催化电介质,对于该催化电介质,可以在仅受到清洁操作的钻孔上进行化学镀。
图1C显示了后续化学镀步骤的完成。化学镀厚度108是均匀涂覆钻出的通孔106并为图1E所示的后续电镀操作而提供与箔层104A和104B的电连接所需的最小值。
图1D显示了图案化步骤,由此,抗蚀剂110A被施加在顶表面104A上,并且覆盖式抗蚀剂(blanket resist)被施加110B到底表面104B上。图1D的抗蚀剂(也称为用于通过暴露于光能形成图案的光致抗蚀剂)或掩模(形成所需图案的机械屏障)110A和110B或图2F的210A和210B可以是液体光致抗蚀剂、干膜光致抗蚀剂、金属掩模、或与周围暴露的铜的蚀刻速率相比具有低蚀刻速率的其它掩模材料。光致抗蚀剂的厚度通常是基于铜/光致抗蚀剂选择性来选择的,使得通过蚀刻去除铜在蚀刻结束时留下足够的抗蚀剂。典型的干膜厚度在0.8-2.5密耳(20-64u)的范围内,并且干膜厚度的选择与成品迹线的线(迹线宽度)/间距(迹线之间的间隙)分辨率相称。例如,0.8密耳的干膜厚度可用于1-1.5密耳迹线/间距要求,1.2密耳干膜可用于1.1-2密耳迹线/间距要求,并且1.5密耳干膜可用于1.75-2.5密耳迹线/间距要求。当电镀如步骤1E中所示发生时,只有暴露的铜区域接收铜沉积112,其形成所谓的“点通孔”(随后形成迹线)。
图1F显示了第一平滑化步骤的结果,由此从原始层114中部分多余的铜和光致抗蚀剂达到新的平面水平,并且点通孔112-1与抗蚀剂110A-1一起降低了高度。表面平滑化可以用许多不同的方式实现,例如使用在平坦表面上施加的420至1200粒度的磨料,在板和平坦表面之间有温和的压力和线性或旋转搅动以提供研磨操作。可以使用用于平面化表面的其他方法,包括使用化学方法、机械方法的铣削或机加工或用于形成平坦表面的其他方法。底表面抗蚀剂110B没有被平滑化,因为该方法仅旨在形成点通孔。
图1G显示了抗蚀剂剥离步骤,其中图1F的抗蚀剂110A-1和110B是使用溶剂或等离子体灰化方法去除的。
图1H显示了第二平滑化步骤,由此,图1G的底座点通孔区域112-1向下平坦化至箔表面104A。用于执行步骤1F的中间平坦化的原因是避免将金属和光致抗蚀剂研磨到箔表面104A上。通过在两步方法中执行该平坦化,第一平坦化1F提供了均匀的表面以及更少的材料在图1H的最终平坦化期间待去除。
图1I显示了钻出穿孔116,随后是在图1J中的化学镀,其在孔116的内表面上沉积铜,在步骤1K中向一侧或两侧施加图案抗蚀剂118,并在步骤1L中电镀,在暴露的铜表面(依赖于提供单个电极的暴露的电镀铜的顶部和底部覆盖层)和被镀覆的穿孔120的内表面上形成迹线。暴露的电镀铜区域随后在没有被抗蚀剂覆盖的任何暴露的铜上方接收一薄层镀锡作为抗蚀剂。
图1M显示了在剥离抗蚀剂118之后的板,抗蚀剂118也可以用于形成与通孔120互连的迹线(未显示)。在此时,通孔120具有镀锡的表面区域(从而抵抗氨基铜蚀刻剂,诸如氯化铵或硫酸铵)和在表面104A和104B上相对薄的暴露的铜化学镀沉积(和下层箔),在表面104A和104B上相对薄的暴露的铜化学镀沉积(和下层箔)是使用铜蚀刻剂(诸如氨基蚀刻剂)蚀刻的,产生图1N所示的结果。薄的锡沉积也是使用蚀刻剂(诸如硝酸)蚀刻掉的,留下铜迹线(未显示)、穿孔、以及通孔,如图1N所示。
图2A至图2J显示了用于形成直径约为3.5密耳(可选地在2-5密耳的范围内)的通孔和宽度约为1密耳且间距约为1密耳的迹线的替代方法,与图1A至图1N的系列中所示的步骤的约3密耳线宽能力相比,该方法极大地进行了改善,并且所需步骤的数量减少。图2A显示了电介质202,其层压有顶部薄箔204A和保护薄箔204A的背衬箔203。类似地,薄底部箔204B与可去除的背衬箔205一起层压到电介质202上,背衬箔205与薄背衬箔204B紧密接触。薄的顶部箔204A和薄的底部箔204B大约0.12至0.15密耳(3u-4u)厚,并且与背衬箔203和205层叠,每个背衬箔具有大约0.75密耳(18u)的厚度。尽管底部背衬箔205对于图2C的激光钻孔步骤来说是至关重要的,但是在步骤2E的化学镀之前,可以在任何时候从薄箔204A上去除顶部背衬箔203。图2B显示了图2A的详细区域207,显示了电介质202、薄底部铜箔204B、和相对较厚的背衬箔205。在本发明的一个实例中,薄的底部箔204B和背衬箔205是以薄片形式被提供的,并且在高温下(诸如350至400°F)和压力下(诸如200至250PSI下)与顶部箔204A一起层压到催化层压板202上,以将顶部箔204A和底部箔204B机械地附接到催化电介质202上。用于将箔204A和204B结合到层压板202的层压步骤不会改变去除背衬铜箔205的容易性,背衬铜箔205在图2C的激光钻孔操作期间充当薄箔204B的散热器。
图2C显示了钻盲通孔206(诸如通过激光烧蚀)以及诸如通过激光烧蚀或机械方式钻穿孔216的结果。如前所述,通过激光烧蚀或钻孔操作的盲通孔的纵横比应该在大约0.5至1的范围内。图2D显示了在去除图2C的下部背衬箔205(诸如通过从底部薄箔204剥掉背衬箔205)之后的电路板层。如图1B所示,在激光烧蚀或钻孔操作之后,可以是对非催化层压板的“去胶渣”操作,或者层压板本身可以是有催化性的,如前所述。任一方法都确保使用激光、机械手段、或化学手段钻盲孔或穿孔,从而形成具有提供如图2E所示的化学镀的暴露的表面催化材料的洞。
图2E显示了化学镀铜沉积后的截面图,其中,化学镀铜217沉积在盲通孔206、穿孔216、以及铜箔204A和204B的表面上。
图2F显示了在施加图案化的光致抗蚀剂210A和210B之后的截面图,其中没有抗蚀剂的区域是将要形成迹线的区域。
图2G显示了在铜电镀步骤之后的截面图,该步骤将铜沉积在没有被抗蚀剂隐藏的所有暴露的铜区域上,包括通孔、钻孔壁、和没有被图案化的光致抗蚀剂覆盖的任何其他铜迹线区域。
图2H是镀锡步骤,由此,任何暴露的铜区域接收薄镀锡板,该薄镀锡板在随后的铜蚀刻步骤期间充当抗蚀剂。
图2I显示了在剥离抗蚀剂后的截面图,以及图2J显示了蚀刻暴露的铜(在图2H的步骤中未涂覆锡的区域)并蚀刻暴露的锡之后(这留下了点通孔220、迹线、和经电镀的穿孔216)的完整电路板层。
产生图2J的两层板的方法可以扩展为形成具有被称为“堆叠通孔”的结构的多层板,其中单层的通孔具有0.5至0.1的纵横比,同时提供所需数量的层之间的连接,并且每个连续层的通孔与每个在前层的通孔轴向同心。图3A至图3H描述了从中部芯304开始形成多层电路板的附加处理步骤。
图3A显示了对应于图2J的芯的两层芯304,具有填充的通孔和迹线存在。添加了新的顶层302和新的底层306,顶层302包括具有顶部箔310的电介质308,底层306具有电介质312和底部箔314。这些也可以包括薄的箔,其具有已经被移除的背衬箔。图3B显示了新的顶层302和新的底层306激光钻的通孔320、322、324、326,并且图3C显示了通孔的内表面328具有暴露的催化微粒,或者通过去胶渣操作(其将催化微粒添加到钻出的通孔的内表面)暴露催化微粒,或者在新的顶层302电介质和新的底层电介质306中具有催化微粒,催化微粒通过步骤3B的钻孔操作被暴露。
图3D显示了化学镀沉积330,并且图3E显示了向新的顶层和新的底层添加图案化的抗蚀剂340。图3F显示了形成经填充的通孔和迹线的电镀沉积342的结果,以及图3G显示了抗蚀剂340被剥离。图3H显示了最终结果4层板,其中,堆叠的通孔彼此上下互连,并且通孔和迹线由层342、330和310形成,这些层在附图中单独显示,但是作为单个均匀的电层。图3A至图3H的方法步骤可以反复重复,以在每次迭代中增加两个额外的层,其中图3H的最后步骤的结果被视为从图3A开始至图3H的下一次迭代处理的新的芯。为了清楚地理解结构,迹线与电介质厚度的相对比例被夸大。
图4A至图4J显示了使用半加成方法形成的内芯电路层的截面图,其中,顶层迹线是使用催化层压板衬底402形成的,该催化层压板衬底402具有富含树脂的表面的特征,该富含树脂的表面排除催化微粒,除非在催化层压板的表面内形成通道。催化微粒通常在每个表面下方的排除深度以下的催化层压板中均匀分布。在图4A中,催化层压板的顶表面是裸露的,并且催化层压板的底表面具有薄箔404B和由铜形成的厚背衬405,薄箔404B层压到催化层压板404B,并且厚背衬箔405提供散热能力,如先前关于图2所述。图4B的细节407显示了催化层压板402、薄箔404B、和厚背衬箔405,它们具有如先前关于图2B所述的相应尺寸。步骤4C显示了激光钻出的孔406和穿孔416,其中钻出的洞使催化层压板402中的催化微粒暴露,并且在顶表面中形成随后将要形成迹线的通道407,其中,通道407足够深,以使在催化层压板的天然表面中不存在的下层催化微粒暴露,直到低于催化微粒排除深度为止。通孔洞406稍后将使用“快速化学镀铜”沉积方法(诸如可商购的乙二胺四乙酸(EDTA)方法)、或者使用利用硫酸铜、甲醛、和氢氧化钠的方法来填充铜,而不是图2G中描述的电镀方法来填充铜。为此,通孔洞406更小(诸如直径大约是2.5-3密耳),以允许使用快速化学镀铜方法填充通孔。如在图2C中所描述的,背衬箔405在通孔激光钻孔期间充当散热器,以防止在激光钻通孔406期间贯穿薄的底部箔404B。在形成通孔406之后,去除背衬箔405,如图4D所示。
图4E显示了快速化学镀铜浴(诸如EDTA方法)的结果,其中顶表面通道407、穿孔416内表面和内部体积、以及薄铜箔404B接收铜沉积417。在该步骤期间,通孔洞406也被填充。
图4F显示了图案化的底侧抗蚀剂410和覆盖顶侧抗蚀剂411的施加,其覆盖了需要铜迹线和通孔的区域。随后,暴露的铜表面在图4G中受到蚀刻,并且其他区域受到抗蚀剂(诸如干膜410和411)保护。在步骤4H中的抗蚀剂剥离之后,双侧芯完成了,并且箔导体404B和化学镀区域417以及经填充的通孔406形成均匀的铜迹线和经填充的通孔,从而形成成品芯,该成品芯可以如图5A至图5C或图3A至图3H所示被进一步层压。
图5A至图5C显示了类似的多层加工步骤,使用催化层压板508和510作为外层,将催化层压板508和510层压到芯504上,该芯可以是使用图2A-2J或图4A-4J的方法形成的。
图5B显示了图5A的层压板具有通道512,通过去除在需要迹线的区域中的表面层,在催化层压板的顶表面和底表面上形成通道512。可选地,去除围绕每个通孔520、522、524、和526的环形材料环。可以通过激光烧蚀来去除表面材料,其中催化预浸料508和510的温度立即升高,直到催化预浸料被蒸发为止,同时保持周围的预浸料在结构上不变,但是暴露下层催化微粒。可能优选的是使用有具有低反射率的波长(诸如紫外(UV)波长)和对于被烧蚀的预浸渍材料该光学波长高吸收的激光器。这种UV激光器的示例是UV准分子激光器或钇铝石榴石(YAG)激光器,其由于窄光束范围和高可用功率因此也是良好的选择,窄光束范围和高可用功率用于形成具有精确机械深度和界限分明的侧壁的通道。示例激光器可以在由激光功率控制的深度和在整个表面上的移动的速度的情况下按照0.9-1.1密耳(23u至28u)直径宽度来去除材料。用于形成通道和相关环形圈的另一种表面去除技术是等离子蚀刻,其可以局部地或者通过用图案化掩模制备表面来完成,该图案化掩模(诸如是干膜光致抗蚀剂或与催化预浸料的蚀刻速率相比具有低蚀刻速率的其他掩模材料)将等离子从表面层508或510中排除。通常基于环氧树脂/光致抗蚀剂蚀刻选择性来选择光致抗蚀剂厚度(使得用于移除固化环氧树脂期望深度的等离子蚀刻在蚀刻结束时留下足够的光致抗蚀剂),或者在光致抗蚀剂用作电镀掩模的情况下,根据期望沉积厚度来选择厚度。一般干膜厚度在0.8-2.5密耳(20-64u)的范围内。适于蚀刻富含树脂的表面的等离子包括与惰性气体(诸如氮(N))混合的氧(O)和CF4等离子的混合物,或者氩(Ar)可以作为反应气体的载气而被添加。也可以用干膜掩模、金属掩模或任何其他类型的具有洞的掩模来形成掩模图案。在使用机械掩模的情况下,可以使用光刻法、丝网印刷、模版印刷、用涂刷器涂刷或涂敷抗蚀剂的任何方法来涂敷抗蚀剂。用于去除预浸料的表面层的另一种方法是机械研磨,诸如线性或旋转切割工具。在这个例子中,预浸料可以固定在真空板卡盘中,并且旋转切割器(或具有可移动真空板的固定切割器)可以行进限定诸如由Gerber格式照片文件的x、y坐标对限定的迹线的图案。在去除表面材料的另一个例子中,可以使用水切割工具,其中在流中夹带有磨蚀微粒的水喷射流可以撞击在表面上,从而去除在该表面下方的材料以暴露下层催化微粒。这些方法中的任何一种都可以单独或组合地被使用,以去除表面材料并形成到催化电介质508和510的通道512,优选地通道在暴露表面下的催化微粒的排除深度之下延伸。因此,最小通道深度是暴露下层催化微粒(这是固化的催化预浸料的特征((诸如根据同样是本发明人的第9,706,650号美国专利形成的预浸料)))所需的深度。因为催化材料均匀地分散在排除深度下方的整个固化预浸料中,最大通道深度受限于催化层压板508、510的编织纤维(诸如玻璃纤维)织物的深度,编织纤维往往使通道清洁变得复杂,因为纤维可能断裂并重新沉积在预定用于化学镀的通道中,或者以其他方式干扰后续的方法步骤。一般通道深度为1密耳(25u)至2密耳(70u)。在去除表面材料以形成通道510之后的最后步骤是清理掉被去除的材料的任何微粒,这可以使用超声波清洗、与表面活性剂混合的水喷射流或不导致在通道512周围的表面的材料被去除的任何其他清洗手段来完成。
接着诸如通过激光钻孔来钻出通孔520、522、524、526(优选地,通孔的直径是例如2.5至3密耳的小直径),以允许在随后的步骤中快速化学镀来填充通孔洞,并且通道512诸如通过激光烧蚀、水切割、等离子体蚀刻、或任何其他形式来形成,以将催化层压板的表面层去除到排除深度以下。在步骤5C中进行化学镀,在从催化层压板508、510上已经去除表面材料的区域上沉积铜530,从而在通道512、通孔520、522、524、和526的内表面中形成导电迹线530,填充通孔洞直到所添加的层502和506的外表面。图5A至图5C的方法步骤可以反复重复,以在每次迭代中增加两个额外的层,其中图5C中的产生的最终步骤被视为从图5A开始至图5C的下一次迭代处理的新的芯。
本发明可以以几种不同的方式实施。应当理解,图3A-3H的芯(中心)电路层304或图5A-5C的504可以由图2J的催化或非催化层压板202或图4J的催化层压板产生。从图2J或图4J的任一芯电路层开始,使用图3A至图3H的化学镀和电镀方法,或者图5A至图5C的化学镀方法,可以交替添加外层。
在本说明书中,一“密耳”被理解为0.001英寸,“近似”被理解为意指小于4倍或更大或更小,“基本上”被理解为意指小于2倍或更大或更小。值的“数量级”包括从0.1倍于该值到10倍于该值的范围。一“密耳”被理解为0.001英寸。
对于印刷电路板制造是通用的某些后处理操作未被示出,并且可以使用现有技术方法对根据新方法而生产的板来执行。这样的操作包括镀锡以改善的焊料流、镀金以改善的导电性和减少的腐蚀、焊料掩模操作、在电路板上的丝网印刷信息(零件号、参考指示符等)、刻划成品板或提供分离翼片等。

Claims (21)

1.一种用于在层压板上形成细间距点通孔的方法,所述层压板具有结合到所述层压板的底部薄箔、与所述底部薄箔相邻的相对较厚的背衬箔、以及任选的薄顶部箔,所述方法包括:
激光钻出穿过所述层压板的顶表面到所述底部薄箔的盲通孔,任选地,还钻出贯穿所述层压板、所述底部薄箔和所述背衬箔的穿孔;
去除所述背衬箔;
用催化剂处理激光钻出的通孔和钻出的孔的表面;
对任选的顶箔表面和底箔表面、所述通孔的内表面、以及任选地钻出的穿孔的内表面进行化学镀;
在所述顶表面和底表面上施加图案化的抗蚀剂;
电镀所述电路板,直到铜沉积到低于所述图案化的抗蚀剂的水平为止;
对所述电路板的暴露的铜区域进行镀锡;
剥离所述图案化的抗蚀剂;
将所述暴露的铜区域快速蚀刻到下层层压板;
任选地蚀刻所述镀锡。
2.根据权利要求1所述的方法,其中,所述底部薄箔或所述任选的顶部薄箔是厚度约为0.12密耳至0.15密耳的铜箔。
3.根据权利要求1所述的方法,其中,所述激光钻出的通孔的直径小于5密耳。
4.根据权利要求1所述的方法,其中,所述化学镀和所述电镀沉积铜。
5.根据权利要求1所述的方法,其中,所述催化剂是下列项中的至少一项:钯(Pd)、铂(Pt)、铑(Rh)、铱(Ir)、镍(Ni)、金(Au)、银(Ag)、钴(Co)、铜(Cu)、铁(Fe)、锰(Mn)、铬(Cr)、钼(Mo)、钨(W)、钛(Ti)或锡(Sn)。
6.根据权利要求1所述的方法,其中,所述用催化剂处理所述激光钻出的通孔和钻出的孔的表面包括所述电介质具有在所述激光钻孔步骤期间暴露的催化微粒。
7.根据权利要求1所述的方法,其中,所述化学镀步骤在所述底部薄箔或所述任选的顶部薄箔上沉积约0.06密耳至0.12密耳厚度的铜。
8.根据权利要求1所述的方法,其中,所述图案化的抗蚀剂是光学曝光的干膜。
9.根据权利要求1所述的方法,其中,所述快速蚀刻步骤使用铵基蚀刻剂,所述铵基蚀刻剂包括氯化铵或硫酸铵中的至少一。
10.一种用于在电路板上形成通孔和迹线的方法,所述电路板包括催化层压板,所述催化层压板具有结合到所述催化层压板的底部薄箔、施加到所述底部薄箔的相对较厚的能够去除的背衬箔、和任选的顶部箔,所述催化层压板具有催化剂的微粒,使得能够在已经被钻孔的表面上进行化学镀,所述方法包括:
激光钻出穿过所述催化层压板的顶表面到所述底部薄箔而不贯穿所述底部薄箔的盲通孔,任选地,还钻出贯穿所述层压板、底部薄箔和底部背衬箔的穿孔;
去除所述底部背衬箔;
对所述底部薄箔、任选的顶部箔、通孔表面和穿孔表面进行化学镀,以形成电连续的导电层;
向所述顶表面和底表面施加图案化的抗蚀剂;
电镀所述电路板,直到铜在暴露的铜区域上沉积到低于所述图案化的抗蚀剂的水平为止;
对所述电路板的暴露的铜区域进行镀锡;
剥离所述图案化的抗蚀剂;
蚀刻所述暴露的铜区域,直到电镀的铜和下层薄箔被去除为止;
任选地蚀刻所述镀锡;
任选地将附加的电介质层和箔层层压到所述电路板的所述顶表面或底表面。
11.根据权利要求10所述的方法,其中,所述底部薄箔或所述任选的顶部薄箔的厚度约为0.12至0.15密耳。
12.根据权利要求10所述的方法,其中,所述用催化剂处理所述激光钻出的通孔和钻出的孔的表面包括所述电介质具有在所述激光钻孔步骤期间暴露的催化微粒。
13.根据权利要求10所述的方法,其中,所述催化微粒包括下列项中的至少一项:钯(Pd)、铂(Pt)、铑(Rh)、铱(Ir)、镍(Ni)、金(Au)、银(Ag)、钴(Co)、铜(Cu)、铁(Fe)、锰(Mn)、铬(Cr)、钼(Mo)、钨(W)、钛(Ti)或锡(Sn)。
14.根据权利要求10所述的方法,其中,所述抗蚀剂是干膜,所述干膜被光学曝光以形成所述图案化的抗蚀剂。
15.一种用于形成多层板的方法,所述多层板具有内芯和一对或更多对外层,
所述内芯形成在电介质上,所述电介质具有施加到所述电介质的顶表面的薄顶部箔,所述薄顶部箔的相对表面任选地具有能够去除的相对较厚的背衬箔,所述电介质底表面具有施加的薄底部箔,所述薄底部箔的相对表面与相对较厚的能够去除的背衬箔接触,所述内芯通过以下步骤形成:
激光钻出穿过所述电介质到所述薄底部箔的深度而不贯穿所述薄底部箔的至少一个通孔,任选地钻出至少一个穿孔,
所述激光钻出的通孔和任选的穿孔具有含有暴露的催化微粒的表面;
之后,对暴露的催化微粒和所述顶部薄铜箔和所述底部薄铜箔进行化学镀;
之后,施加图案化的抗蚀剂,以产生暴露的铜区域和隐藏的铜区域;
之后,电镀所述暴露的铜区域;
之后,对所述暴露的铜区域进行镀锡;
之后,剥离所述图案化的抗蚀剂;
之后,快速蚀刻所述内芯,直到先前隐藏的铜区域被蚀刻掉铜为止;通过将电介质层施加到所述内芯的每一侧而形成所述外层对,每个电介质层的相对表面具有薄箔,对于每个外层对:
激光钻出至少一个通孔和任选的穿过所述电介质层到下层铜层的穿孔;
激光钻出的孔具有暴露的催化微粒;
对暴露的薄铜箔和暴露的催化微粒进行化学镀;
向至少一个表面施加图案化的抗蚀剂;
电镀暴露的表面;
在被电镀的区域上镀锡;
剥离所述图案化的抗蚀剂;
快速蚀刻暴露的铜。
16.根据权利要求15所述的方法,其中,所述箔层中的至少一层的厚度约为0.12至0.15密耳。
17.根据权利要求15所述的方法,其中,所述外层通孔中的至少一个堆叠在对应的内层通孔之上。
18.根据权利要求15所述的方法,其中,用氨基蚀刻剂进行所述蚀刻。
19.根据权利要求18所述的方法,其中,所述氨基蚀刻剂包括氯化铵或硫酸铵中的至少一种。
20.一种用于形成电路板芯的方法,所述电路板芯具有催化层压板,所述催化层压板具有层压在底表面上的薄箔,所述薄箔与厚背衬箔相邻;
在所述催化层压板的顶表面中形成通孔,所述通孔到达所述薄箔但不贯穿所述薄箔,所述厚背衬箔足够厚以防止所述薄箔熔化,还在所述催化层压板的顶表面中形成迹线通道,所述迹线通道具有足够的深度以暴露所述催化层压板中的下层催化微粒;
去除所述厚背衬箔;
对所暴露的铜表面和在催化层压板的具有暴露的催化微粒的区域中进行化学镀;
将覆盖式抗蚀剂掩模施加到整个顶表面,并将图案化的抗蚀剂掩模施加到所述底表面;
蚀刻所述底表面的未被抗蚀剂掩模覆盖的暴露区域;
剥离所述抗蚀剂掩模。
21.一种由具有填充通孔和迹线的中间芯形成多层电路板的方法,所述方法包括:
将催化层压板层压到所述中间芯的每个表面上;
在所述催化层压板的外表面中形成暴露下层催化微粒的通道,并且还形成与下层通孔的轴线同心的通孔,在所述催化层压板中形成的通孔暴露了下层填充通孔;
对所述催化层压板进行化学镀,从而在所述通道中形成迹线并且填充所述催化层压板中的通孔,使得所述催化层压板中的通孔与所述芯的填充通孔电连续。
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