CN111081629B - 带空腔soi晶圆的对准标记制作方法和空腔位置确定方法 - Google Patents
带空腔soi晶圆的对准标记制作方法和空腔位置确定方法 Download PDFInfo
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- CN111081629B CN111081629B CN201911066355.XA CN201911066355A CN111081629B CN 111081629 B CN111081629 B CN 111081629B CN 201911066355 A CN201911066355 A CN 201911066355A CN 111081629 B CN111081629 B CN 111081629B
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- cavity
- soi wafer
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- silicon wafers
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 235000012431 wafers Nutrition 0.000 claims abstract description 76
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 38
- 239000010703 silicon Substances 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000000227 grinding Methods 0.000 claims abstract description 12
- 238000001259 photo etching Methods 0.000 claims abstract description 8
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 239000000126 substance Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 230000008685 targeting Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201911066355.XA CN111081629B (zh) | 2019-11-04 | 2019-11-04 | 带空腔soi晶圆的对准标记制作方法和空腔位置确定方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201911066355.XA CN111081629B (zh) | 2019-11-04 | 2019-11-04 | 带空腔soi晶圆的对准标记制作方法和空腔位置确定方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111081629A CN111081629A (zh) | 2020-04-28 |
CN111081629B true CN111081629B (zh) | 2022-08-16 |
Family
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Family Applications (1)
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CN201911066355.XA Active CN111081629B (zh) | 2019-11-04 | 2019-11-04 | 带空腔soi晶圆的对准标记制作方法和空腔位置确定方法 |
Country Status (1)
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CN (1) | CN111081629B (zh) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5236118A (en) * | 1992-05-12 | 1993-08-17 | The Regents Of The University Of California | Aligned wafer bonding |
FR2947948A1 (fr) * | 2009-07-09 | 2011-01-14 | Commissariat Energie Atomique | Plaquette poignee presentant des fenetres de visualisation |
CN109643700A (zh) * | 2018-11-21 | 2019-04-16 | 长江存储科技有限责任公司 | 接合界面处的接合对准标记 |
CN110223917A (zh) * | 2019-05-09 | 2019-09-10 | 上海华力集成电路制造有限公司 | 降低铜化学机械研磨对后端套准精度的影响的方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI272654B (en) * | 2003-07-18 | 2007-02-01 | Asia Pacific Microsystems Inc | Method for keeping the precision of photolithography alignment after wafer bonding |
-
2019
- 2019-11-04 CN CN201911066355.XA patent/CN111081629B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5236118A (en) * | 1992-05-12 | 1993-08-17 | The Regents Of The University Of California | Aligned wafer bonding |
FR2947948A1 (fr) * | 2009-07-09 | 2011-01-14 | Commissariat Energie Atomique | Plaquette poignee presentant des fenetres de visualisation |
CN109643700A (zh) * | 2018-11-21 | 2019-04-16 | 长江存储科技有限责任公司 | 接合界面处的接合对准标记 |
CN110223917A (zh) * | 2019-05-09 | 2019-09-10 | 上海华力集成电路制造有限公司 | 降低铜化学机械研磨对后端套准精度的影响的方法 |
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CN111081629A (zh) | 2020-04-28 |
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Effective date of registration: 20220407 Address after: 315832 e2025, zone a, Room 401, building 1, No. 88, Meishan Qixing Road, Beilun District, Ningbo, Zhejiang Province Applicant after: Ningbo Huazhang enterprise management partnership (L.P.) Address before: 430072 Hubei Province, Wuhan city Wuchang District of Wuhan University Luojiashan Applicant before: WUHAN University |
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Effective date of registration: 20220902 Address after: No.01, 4th floor, building D7, phase 3, Wuhan Software New Town, No.9 Huacheng Avenue, Donghu New Technology Development Zone, Wuhan City, Hubei Province, 430000 Patentee after: Wuhan Minsheng New Technology Co.,Ltd. Address before: 315832 e2025, zone a, Room 401, building 1, No. 88, Meishan Qixing Road, Beilun District, Ningbo, Zhejiang Province Patentee before: Ningbo Huazhang enterprise management partnership (L.P.) |