Multi-chip stacking packaging structure and packaging method thereof
[ technical field ] A method for producing a semiconductor device
The invention belongs to the field of storage chip packaging, and relates to a multi-chip stacking packaging structure and a packaging method thereof.
[ background of the invention ]
With the development of consumer electronics, there is an increasing demand for high frequency, large capacity, multi-functionality, and high reliability memory devices. In the conventional multi-chip stack package, a plurality of bonding wires are usually used to electrically connect the chips through the substrate circuit, and the bonding wires are long and thin in the connection method, so that the electrical property cannot meet the expected requirement, and the electrical property loss is easily caused. Therefore, how to improve the package reliability and reduce the electrical loss is a major problem to be solved urgently.
[ summary of the invention ]
The present invention is directed to overcome the above-mentioned disadvantages of the prior art and to provide a multi-chip stacked package structure and a method for packaging the same.
In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:
the utility model provides a multi-chip piles up packaging structure, which comprises a base plate, chip and ladder plastic envelope unit, ladder plastic envelope unit includes the ladder plastic envelope body of plastic envelope on the base plate, ladder plastic envelope body up end is stair structure, ladder plastic envelope body's stair structure surface is equipped with the first plastic envelope surface line of being connected with base plate upper end wiring, a plurality of chips pile up in proper order on ladder plastic envelope body's stair structure, the wiring end and the first plastic envelope surface line welding of chip, ladder plastic envelope and a plurality of chips are connected with the base plate plastic envelope through the second plastic envelope body.
Furthermore, a welding pad is arranged between the wiring end of the chip and the surface line of the first plastic package body.
Furthermore, two adjacent chips are connected through an adhesive layer.
Furthermore, the height of the step plastic package is equal to the sum of the heights of a chip and an adhesive layer.
Furthermore, a solder ball for wiring is arranged at the lower end of the substrate; the solder balls of the substrate are connected to the wiring on the substrate via the internal circuit of the substrate.
A packaging method of a multi-chip stack packaging structure comprises the following steps:
step 1), plastically packaging the upper end of a substrate with wiring at the upper end to form a stepped plastic packaging structure;
step 2), a first plastic package surface line is attached to the step surface of the step plastic package structure to form a step conductive lead layer;
step 3), sequentially welding a plurality of chips on the stepped surface of the stepped plastic package structure to enable the wiring ends of the chips to be in surface line connection with the surface of the first plastic package structure;
and step 4) finally, plastically packaging the chip 5 and the stepped plastic packaging structure 3 on the substrate 1 through secondary plastic packaging to form a multi-chip stacking packaging structure.
Further, the stepped plastic package structure is formed on the substrate through plastic package through a special-shaped plastic package mold.
Further, the surface line of the first plastic package body forms a conducting circuit layer on the step surface of the step plastic package structure through spraying or line pasting.
Furthermore, a welding pad is arranged between the chip wiring end and the surface line of the first plastic package body.
Furthermore, when the plurality of chips are sequentially welded on the stepped plastic package structure, the sum of the thickness of the adhesive layer and the height of the chips is equal to the stepped height of the stepped plastic package.
Compared with the prior art, the invention has the following beneficial effects:
the invention relates to a multi-chip stacking packaging structure, which adopts a packaging unit formed by a plurality of chips stacked in a ladder way, wherein the lead ends of the chips stacked in the ladder way are positioned on the surface of a step, the lead ends of the chips are connected through chip wiring, the chips do not need routing, the packaging volume of the chips is reduced, the ladder plastic package and the chips are in plastic package connection with a substrate through a second plastic package body, and conducting circuits do not need to be connected through holes, so that the open circuit problem caused by insufficient copper plating of the through holes is reduced, the forming steps of the conducting circuits are simplified, and the punching cost is saved; the multi-chip is piled up and is placed perpendicularly, has reduced the chip because unsettled, the too big lobe of a leaf risk that probably produces of bearing, simultaneously, plays the effect of secondary protection with a plurality of encapsulation units and base plate plastic envelope through the second plastic envelope body, has improved product reliability.
According to the packaging method of the multi-chip stacking packaging structure, the ladder conductive structure is reserved through primary plastic packaging, the storage chips with proper quantity can be flexibly selected for welding and expanding capacity conveniently according to requirements in the later period, the multiple interfaces which are interconnected are formed on the surface of the circuit layer on the surface of the primary ladder plastic packaging, the front sides of the multiple chips are electrically connected with each interface of the rewiring circuit layer through welding, the electrical loss is reduced, the wire punching risk is avoided, and the stacking quantity of the chips and the thickness of the plastic packaging are flexible and adjustable.
[ description of the drawings ]
Fig. 1 is a schematic view of a stacked package structure according to the present invention.
Fig. 2 is a schematic view of a substrate.
Fig. 3 is a structural view of a step molding formed on the surface of a substrate.
Fig. 4 illustrates a conductive circuit formed on the surface of the step plastic package structure.
Fig. 5 shows the electrical connection of the multilayer chip to the conductive traces by soldering.
Fig. 6 shows that the secondary plastic package protects the chip to form a complete package.
Wherein: 1: a substrate; 2: tin balls; 3: a stepped plastic package body; 4: a first plastic package surface circuit; 5: a chip; 6: an adhesive layer; 7: a second plastic package body; 8: a pad; 9: and a substrate internal circuit.
[ detailed description ] embodiments
The invention is described in further detail below with reference to the accompanying drawings:
as shown in fig. 1 to 6, a multi-chip stacking and packaging structure, including base plate 1, chip 5 and ladder plastic packaging unit, ladder plastic packaging unit includes ladder plastic packaging body 3 of plastic packaging on base plate 1, 3 up end of ladder plastic packaging body is the stair structure, ladder plastic packaging body 3's stair structure surface is equipped with the first plastic packaging body surface line 4 with 1 upper end wiring connection of base plate, a plurality of chips 5 pile up in proper order on ladder plastic packaging body's stair structure, chip 5's wiring end and first plastic packaging body surface line 4 weld, ladder plastic packaging 3 and a plurality of chips 5 are connected with base plate 1 plastic packaging through second plastic packaging body 7.
The step surface of the chip 5 stacked in a stepped mode is communicated with the chips through the first plastic package surface line 4, the connection is stable, the connection space between the chips 5 is small, the chips 5 are not suspended, and the risk of chip cracking is avoided.
And a welding pad 8 is arranged between the wiring end of the chip 5 and the surface line 4 of the first plastic package. Two adjacent chips 5 are connected by an adhesive layer 6. The step height of the step plastic package 3 is equal to the sum of the heights of one chip 5 and one adhesive layer 6.
The lower end of the substrate 1 is provided with a solder ball 2 for wiring. The solder ball 2 of the substrate 1 is connected to the wiring on the substrate 1 via the substrate internal wiring 9.
A packaging method of a multi-chip stack packaging structure comprises the following steps:
step 1), plastically packaging the upper end of a substrate 1 with wiring at the upper end to form a stepped plastic packaging structure 3;
the stepped plastic package structure 3 is formed on the substrate 1 through plastic package through a special-shaped plastic package mold.
Step 2), a first plastic package surface line 4 is attached to the step surface of the step plastic package structure 3 to form a step conductive lead layer;
the first plastic package surface line 4 forms a conductive circuit layer on the step surface of the step plastic package structure 3 through spraying or line pasting.
Step 3), sequentially welding a plurality of chips 5 on the stepped surface of the stepped plastic package structure 3, so that the wiring ends of the chips 5 are connected with the surface line 4 of the first plastic package body; specifically, a welding pad 8 is arranged between the wiring end of the chip 5 and the surface line 4 of the first plastic package, so that the connection stability is ensured.
And step 4) finally, plastically packaging the chip 5 and the stepped plastic packaging structure 3 on the substrate 1 through secondary plastic packaging to form a multi-chip stacking packaging structure.
The surface line 4 of the first plastic package body is arranged by adopting a copper sheet, so that the heat dissipation performance is greatly improved.
This application is echelonment with a plurality of chips 5 and piles up in proper order at ladder plastic envelope structure 3, makes 4 wiring ends of chip be located the ladder upper surface, greatly reduced the electrical property loss in the transmission course.
The multi-chip is piled up and is placed, connects through adhesion coating 6 between two adjacent chips 5, and it is inseparable to bond, has reduced the chip because unsettled, the too big lobe of a leaf risk that probably produces of bearing, simultaneously, plays the effect of secondary protection with a plurality of encapsulation units and base plate plastic envelope through the second plastic-sealed body, has improved product reliability. The multiple modules are arranged in parallel on the substrate, so that the balance of the whole structure is better, and the packaging reliability of the product is further improved. The modular design can be flexibly used for the expansion of products, and the integration level of the product is improved. And the packaging of different modules is more beneficial to realizing the multi-functionalization of products.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.