CN111048479A - Multi-chip stacking packaging structure and packaging method thereof - Google Patents

Multi-chip stacking packaging structure and packaging method thereof Download PDF

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Publication number
CN111048479A
CN111048479A CN201911381418.0A CN201911381418A CN111048479A CN 111048479 A CN111048479 A CN 111048479A CN 201911381418 A CN201911381418 A CN 201911381418A CN 111048479 A CN111048479 A CN 111048479A
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plastic
chip
packaging
chips
ladder
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CN201911381418.0A
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CN111048479B (en
Inventor
杨巧
马晓建
董晨
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Huatian Technology Nanjing Co Ltd
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Huatian Technology Xian Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention discloses a multi-chip stacking packaging structure and a packaging method thereof.A packaging unit formed by a plurality of chips stacked in a ladder way is adopted, the lead ends of the chips stacked in the ladder way are positioned on the surface of a step, the lead ends of the chips are connected through chip wiring, the chips do not need routing, the packaging volume of the chips is reduced, the ladder plastic package and the chips are in plastic package connection with a substrate through a second plastic package body, via hole connection is not needed between conductive circuits, the open circuit problem caused by insufficient copper plating of the via holes is reduced, the forming steps of the conductive circuits are simplified, and the punching cost is saved; the multi-chip is piled up and is placed perpendicularly, has reduced the chip because unsettled, the too big lobe of a leaf risk that probably produces of bearing, simultaneously, plays the effect of secondary protection with a plurality of encapsulation units and base plate plastic envelope through the second plastic envelope body, has improved product reliability.

Description

Multi-chip stacking packaging structure and packaging method thereof
[ technical field ] A method for producing a semiconductor device
The invention belongs to the field of storage chip packaging, and relates to a multi-chip stacking packaging structure and a packaging method thereof.
[ background of the invention ]
With the development of consumer electronics, there is an increasing demand for high frequency, large capacity, multi-functionality, and high reliability memory devices. In the conventional multi-chip stack package, a plurality of bonding wires are usually used to electrically connect the chips through the substrate circuit, and the bonding wires are long and thin in the connection method, so that the electrical property cannot meet the expected requirement, and the electrical property loss is easily caused. Therefore, how to improve the package reliability and reduce the electrical loss is a major problem to be solved urgently.
[ summary of the invention ]
The present invention is directed to overcome the above-mentioned disadvantages of the prior art and to provide a multi-chip stacked package structure and a method for packaging the same.
In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:
the utility model provides a multi-chip piles up packaging structure, which comprises a base plate, chip and ladder plastic envelope unit, ladder plastic envelope unit includes the ladder plastic envelope body of plastic envelope on the base plate, ladder plastic envelope body up end is stair structure, ladder plastic envelope body's stair structure surface is equipped with the first plastic envelope surface line of being connected with base plate upper end wiring, a plurality of chips pile up in proper order on ladder plastic envelope body's stair structure, the wiring end and the first plastic envelope surface line welding of chip, ladder plastic envelope and a plurality of chips are connected with the base plate plastic envelope through the second plastic envelope body.
Furthermore, a welding pad is arranged between the wiring end of the chip and the surface line of the first plastic package body.
Furthermore, two adjacent chips are connected through an adhesive layer.
Furthermore, the height of the step plastic package is equal to the sum of the heights of a chip and an adhesive layer.
Furthermore, a solder ball for wiring is arranged at the lower end of the substrate; the solder balls of the substrate are connected to the wiring on the substrate via the internal circuit of the substrate.
A packaging method of a multi-chip stack packaging structure comprises the following steps:
step 1), plastically packaging the upper end of a substrate with wiring at the upper end to form a stepped plastic packaging structure;
step 2), a first plastic package surface line is attached to the step surface of the step plastic package structure to form a step conductive lead layer;
step 3), sequentially welding a plurality of chips on the stepped surface of the stepped plastic package structure to enable the wiring ends of the chips to be in surface line connection with the surface of the first plastic package structure;
and step 4) finally, plastically packaging the chip 5 and the stepped plastic packaging structure 3 on the substrate 1 through secondary plastic packaging to form a multi-chip stacking packaging structure.
Further, the stepped plastic package structure is formed on the substrate through plastic package through a special-shaped plastic package mold.
Further, the surface line of the first plastic package body forms a conducting circuit layer on the step surface of the step plastic package structure through spraying or line pasting.
Furthermore, a welding pad is arranged between the chip wiring end and the surface line of the first plastic package body.
Furthermore, when the plurality of chips are sequentially welded on the stepped plastic package structure, the sum of the thickness of the adhesive layer and the height of the chips is equal to the stepped height of the stepped plastic package.
Compared with the prior art, the invention has the following beneficial effects:
the invention relates to a multi-chip stacking packaging structure, which adopts a packaging unit formed by a plurality of chips stacked in a ladder way, wherein the lead ends of the chips stacked in the ladder way are positioned on the surface of a step, the lead ends of the chips are connected through chip wiring, the chips do not need routing, the packaging volume of the chips is reduced, the ladder plastic package and the chips are in plastic package connection with a substrate through a second plastic package body, and conducting circuits do not need to be connected through holes, so that the open circuit problem caused by insufficient copper plating of the through holes is reduced, the forming steps of the conducting circuits are simplified, and the punching cost is saved; the multi-chip is piled up and is placed perpendicularly, has reduced the chip because unsettled, the too big lobe of a leaf risk that probably produces of bearing, simultaneously, plays the effect of secondary protection with a plurality of encapsulation units and base plate plastic envelope through the second plastic envelope body, has improved product reliability.
According to the packaging method of the multi-chip stacking packaging structure, the ladder conductive structure is reserved through primary plastic packaging, the storage chips with proper quantity can be flexibly selected for welding and expanding capacity conveniently according to requirements in the later period, the multiple interfaces which are interconnected are formed on the surface of the circuit layer on the surface of the primary ladder plastic packaging, the front sides of the multiple chips are electrically connected with each interface of the rewiring circuit layer through welding, the electrical loss is reduced, the wire punching risk is avoided, and the stacking quantity of the chips and the thickness of the plastic packaging are flexible and adjustable.
[ description of the drawings ]
Fig. 1 is a schematic view of a stacked package structure according to the present invention.
Fig. 2 is a schematic view of a substrate.
Fig. 3 is a structural view of a step molding formed on the surface of a substrate.
Fig. 4 illustrates a conductive circuit formed on the surface of the step plastic package structure.
Fig. 5 shows the electrical connection of the multilayer chip to the conductive traces by soldering.
Fig. 6 shows that the secondary plastic package protects the chip to form a complete package.
Wherein: 1: a substrate; 2: tin balls; 3: a stepped plastic package body; 4: a first plastic package surface circuit; 5: a chip; 6: an adhesive layer; 7: a second plastic package body; 8: a pad; 9: and a substrate internal circuit.
[ detailed description ] embodiments
The invention is described in further detail below with reference to the accompanying drawings:
as shown in fig. 1 to 6, a multi-chip stacking and packaging structure, including base plate 1, chip 5 and ladder plastic packaging unit, ladder plastic packaging unit includes ladder plastic packaging body 3 of plastic packaging on base plate 1, 3 up end of ladder plastic packaging body is the stair structure, ladder plastic packaging body 3's stair structure surface is equipped with the first plastic packaging body surface line 4 with 1 upper end wiring connection of base plate, a plurality of chips 5 pile up in proper order on ladder plastic packaging body's stair structure, chip 5's wiring end and first plastic packaging body surface line 4 weld, ladder plastic packaging 3 and a plurality of chips 5 are connected with base plate 1 plastic packaging through second plastic packaging body 7.
The step surface of the chip 5 stacked in a stepped mode is communicated with the chips through the first plastic package surface line 4, the connection is stable, the connection space between the chips 5 is small, the chips 5 are not suspended, and the risk of chip cracking is avoided.
And a welding pad 8 is arranged between the wiring end of the chip 5 and the surface line 4 of the first plastic package. Two adjacent chips 5 are connected by an adhesive layer 6. The step height of the step plastic package 3 is equal to the sum of the heights of one chip 5 and one adhesive layer 6.
The lower end of the substrate 1 is provided with a solder ball 2 for wiring. The solder ball 2 of the substrate 1 is connected to the wiring on the substrate 1 via the substrate internal wiring 9.
A packaging method of a multi-chip stack packaging structure comprises the following steps:
step 1), plastically packaging the upper end of a substrate 1 with wiring at the upper end to form a stepped plastic packaging structure 3;
the stepped plastic package structure 3 is formed on the substrate 1 through plastic package through a special-shaped plastic package mold.
Step 2), a first plastic package surface line 4 is attached to the step surface of the step plastic package structure 3 to form a step conductive lead layer;
the first plastic package surface line 4 forms a conductive circuit layer on the step surface of the step plastic package structure 3 through spraying or line pasting.
Step 3), sequentially welding a plurality of chips 5 on the stepped surface of the stepped plastic package structure 3, so that the wiring ends of the chips 5 are connected with the surface line 4 of the first plastic package body; specifically, a welding pad 8 is arranged between the wiring end of the chip 5 and the surface line 4 of the first plastic package, so that the connection stability is ensured.
And step 4) finally, plastically packaging the chip 5 and the stepped plastic packaging structure 3 on the substrate 1 through secondary plastic packaging to form a multi-chip stacking packaging structure.
The surface line 4 of the first plastic package body is arranged by adopting a copper sheet, so that the heat dissipation performance is greatly improved.
This application is echelonment with a plurality of chips 5 and piles up in proper order at ladder plastic envelope structure 3, makes 4 wiring ends of chip be located the ladder upper surface, greatly reduced the electrical property loss in the transmission course.
The multi-chip is piled up and is placed, connects through adhesion coating 6 between two adjacent chips 5, and it is inseparable to bond, has reduced the chip because unsettled, the too big lobe of a leaf risk that probably produces of bearing, simultaneously, plays the effect of secondary protection with a plurality of encapsulation units and base plate plastic envelope through the second plastic-sealed body, has improved product reliability. The multiple modules are arranged in parallel on the substrate, so that the balance of the whole structure is better, and the packaging reliability of the product is further improved. The modular design can be flexibly used for the expansion of products, and the integration level of the product is improved. And the packaging of different modules is more beneficial to realizing the multi-functionalization of products.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (10)

1. The utility model provides a multi-chip piles up packaging structure, a serial communication port, including base plate (1), chip (5) and ladder plastic envelope unit, ladder plastic envelope unit includes ladder plastic envelope body (3) of plastic envelope on base plate (1), ladder plastic envelope body (3) up end is the stair structure, the stair structure surface of ladder plastic envelope body (3) is equipped with first plastic envelope surface line (4) of being connected with base plate (1) upper end wiring, a plurality of chips (5) pile up in proper order on the stair structure of ladder plastic envelope body (3), the wiring end and the first plastic envelope surface line (4) welding of chip (5), ladder plastic envelope (3) and a plurality of chips (5) are connected with base plate (1) plastic envelope through second plastic envelope body (7).
2. The multi-chip stacked package structure of claim 1, wherein a bonding pad (8) is disposed between the terminal of the chip (5) and the surface line (4) of the first plastic package.
3. The multi-chip stack package structure according to claim 1, wherein two adjacent chips (5) are connected by an adhesive layer (6).
4. The multi-chip stack package structure according to claim 1, wherein the step height of the step plastic package (3) is equal to the sum of the heights of one chip (5) and one adhesive layer (6).
5. The multi-chip stacked package structure according to claim 1, wherein the lower end of the substrate (1) is provided with solder balls (2) for wiring, and the solder balls (2) of the substrate (1) are connected to the wiring on the substrate (1) through the substrate internal circuit (9).
6. A packaging method of a multi-chip stack packaging structure is characterized by comprising the following steps:
step 1), plastically packaging the upper end of a substrate with wiring at the upper end to form a stepped plastic packaging structure;
step 2), a first plastic package surface line is attached to the step surface of the step plastic package structure to form a step conductive lead layer;
step 3), sequentially welding a plurality of chips on the stepped surface of the stepped plastic package structure to enable the wiring ends of the chips to be in surface line connection with the surface of the first plastic package structure;
and step 4) finally, plastically packaging the chip 5 and the stepped plastic packaging structure 3 on the substrate 1 through secondary plastic packaging to form a multi-chip stacking packaging structure.
7. The packaging method of the multi-chip stack packaging structure as claimed in claim 6, wherein the step plastic package structure is formed on the substrate by plastic package through a special-shaped plastic package mold.
8. The method of claim 6, wherein the first molding compound surface line is formed with a conductive trace layer on the step surface of the step molding compound by spraying or pasting.
9. The method of claim 6, wherein a bonding pad is disposed between the chip terminal and the surface line of the first plastic package.
10. The packaging method of claim 6, wherein the sum of the thickness of the adhesive layer and the height of the chips is equal to the step height of the step plastic package when the plurality of chips are sequentially welded on the step plastic package structure.
CN201911381418.0A 2019-12-27 2019-12-27 Multi-chip stacking packaging structure and packaging method thereof Active CN111048479B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113745171A (en) * 2021-08-31 2021-12-03 华天科技(南京)有限公司 Chip stacking and packaging structure with step cavity and manufacturing method thereof

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CN104576622A (en) * 2013-10-21 2015-04-29 标准科技股份有限公司 Packaging module with biased stacking element
CN104733447A (en) * 2013-12-18 2015-06-24 标准科技股份有限公司 Packaging module with stacked elements
KR20190131453A (en) * 2018-05-16 2019-11-26 주식회사 네패스 Package unit and multi-stack package

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US20130032954A1 (en) * 2006-12-09 2013-02-07 Stats Chippac Ltd. Stackable integrated circuit package system
JP2009027068A (en) * 2007-07-23 2009-02-05 Alps Electric Co Ltd Semiconductor device
US20110033978A1 (en) * 2008-06-30 2011-02-10 Hynix Semiconductor Inc. Stacked semiconductor package electrically connecting semiconductor chips using outer surfaces thereof and method for manufacturing the same
CN102194805A (en) * 2010-03-18 2011-09-21 海力士半导体有限公司 Semiconductor package with stacked chips and method for manufacturing the same
CN103081103A (en) * 2010-09-01 2013-05-01 甲骨文国际公司 Manufacturing fixture for a ramp-stack chip package
CN104425466A (en) * 2013-08-28 2015-03-18 标准科技股份有限公司 Packaging module with biased stack element
CN104576622A (en) * 2013-10-21 2015-04-29 标准科技股份有限公司 Packaging module with biased stacking element
CN104733447A (en) * 2013-12-18 2015-06-24 标准科技股份有限公司 Packaging module with stacked elements
CN104332462A (en) * 2014-09-16 2015-02-04 山东华芯半导体有限公司 Wafer-level package (WLP) unit with aslant stacked chips, and package method thereof
KR20190131453A (en) * 2018-05-16 2019-11-26 주식회사 네패스 Package unit and multi-stack package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113745171A (en) * 2021-08-31 2021-12-03 华天科技(南京)有限公司 Chip stacking and packaging structure with step cavity and manufacturing method thereof

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