CN110943080B - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN110943080B
CN110943080B CN201910609180.6A CN201910609180A CN110943080B CN 110943080 B CN110943080 B CN 110943080B CN 201910609180 A CN201910609180 A CN 201910609180A CN 110943080 B CN110943080 B CN 110943080B
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conductive layer
buried conductive
gate
isolation pattern
contact
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CN110943080A (zh
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金煐勋
梁在锡
李海王
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

一种半导体器件包括：有源区域，在衬底上沿第一方向延伸；掩埋导电层，在衬底上与有源区域相邻设置并沿第一方向延伸；栅电极，交叉有源区域并沿交叉第一方向的第二方向延伸；源/漏层，在栅电极的一侧设置在有源区域上；栅隔离图案，设置在掩埋导电层上以与栅电极的一端相邻设置，并沿第一方向延伸；以及接触插塞，设置在源/漏层上、电连接到掩埋导电层并与栅隔离图案接触。

Description

半导体器件
技术领域
示例实施方式涉及半导体器件。
背景技术
由于对半导体器件的高性能、高速度和多功能性的需求已经增加，半导体器件的集成度已增大。为了满足对半导体器件的高集成的要求，图案会需要精细的宽度或其间的精细的距离。而且，为了控制短沟道效应，已提出了包括包含具有三维结构的沟道的全包围栅(GAA)晶体管和鳍式场效应晶体管(FinFET)的半导体器件。
发明内容
至少一些示例实施方式涉及半导体器件，其具有包括掩埋电源轨(powerrail)的标准单元结构以增大其集成度。
根据一示例实施方式，一种半导体器件包括：有源区域，在衬底上沿第一方向延伸；掩埋导电层，在衬底上沿第一方向延伸，使得掩埋导电层与有源区域相邻；栅电极，沿交叉第一方向的第二方向延伸，使得栅电极交叉有源区域；源/漏层，在栅电极的一侧在有源区域上；栅隔离图案，在掩埋导电层上沿第一方向延伸，栅隔离图案与栅电极的一端相邻；以及接触插塞，在源/漏层上并延伸以电连接到掩埋导电层，接触插塞与栅隔离图案接触。
根据一示例实施方式，一种半导体器件包括：至少两个有源区域，包括第一有源区域和第二有源区域，所述至少两个有源区域的每个在衬底上沿第一方向延伸；至少两个栅电极，包括第一栅电极和第二栅电极，所述至少两个栅电极的每个沿交叉第一方向的第二方向延伸，使得所述至少两个栅电极在第二方向上彼此相邻；栅隔离图案，在第一栅电极和第二栅电极之间沿第一方向延伸；掩埋导电层，在栅隔离图案下方沿第一方向延伸；至少两个源/漏层，包括分别在第一有源区域和第二有源区域上的第一源/漏层和第二源/漏层；以及至少两个接触插塞，包括分别在第一源/漏层和第二源/漏层上的第一接触插塞和第二接触插塞，第一接触插塞和第二接触插塞中的至少一个与栅隔离图案接触，同时在第二方向上具有横向不对称的形状。
根据一示例实施方式，一种半导体器件包括：在衬底上的栅结构；在栅结构的一侧的源/漏层；相对于衬底低于源/漏层的掩埋导电层；在掩埋导电层上的栅隔离图案，栅隔离图案与栅结构接触；以及在源/漏层上的接触插塞，接触插塞与栅隔离图案接触，接触插塞延伸至掩埋导电层同时覆盖源/漏层的一端。
附图说明
本公开的以上及另外的方面、特征和优点将由以下结合附图的详细描述被更清楚地理解，附图中：
图1是示出根据本发明构思的一示例实施方式的半导体器件的俯视图；
图2和图3是半导体器件的沿图1的线I-I'和II-II'截取的剖视图；
图4至7是根据本发明构思的示例实施方式的半导体器件的剖视图；
图8是示出根据本发明构思的一示例实施方式的半导体器件的俯视图；
图9是半导体器件的沿图8的线I-I'截取的剖视图；
图10是示出根据本发明构思的一示例实施方式的半导体器件的俯视图；
图11是示出根据本发明构思的一示例实施方式的半导体器件的俯视图；以及
图12和图13是半导体器件的沿图11的线I-I'和II-II'截取的剖视图。
具体实施方式
在下文中，将参照附图描述本发明构思的示例实施方式。
图1是示出根据一示例实施方式的半导体器件的俯视图。图2和图3是半导体器件的沿图1的线I-I'和II-II'截取的剖视图。
参照图1，根据一示例实施方式的半导体器件可以包括提供在衬底上的逻辑标准单元SCL。每个逻辑标准单元SCL可以包括第一器件区域R1、第二器件区域R2、位于第一器件区域R1和第二器件区域R2之间的隔离区域SR、与第一器件区域R1相邻的第一电源轨区域PR1、以及与第二器件区域R2相邻的第二电源轨区域PR2。
n型晶体管TN可以设置在第一器件区域R1中，p型晶体管TP可以设置在第二器件区域R2中。n型晶体管TN和p型晶体管TP可以是鳍式场效应晶体管(FinFET)。
在第一器件区域R1中，p型有源区域AN可以沿第一方向(X方向)延伸，栅结构GSN可以沿第二方向(Y方向)延伸以交叉p型有源区域AN，n型源/漏层SD可以在栅结构GSN之间设置在p型有源区域AN上，并且接触插塞91可以设置在n型源/漏层SD上。
在第二器件区域R2中，n型有源区域AP可以沿第一方向(X方向)延伸，栅结构GSP可以沿第二方向(Y方向)延伸以交叉n型有源区域AP，p型源/漏层SG可以在栅结构GSP之间设置在n型有源区域AP上，并且接触插塞92可以设置在p型源/漏层SG上。
作为示例，两个p型有源区域AN在第一器件区域R1中被示出，两个n型有源区域AP在第二器件区域R2中被示出。p型有源区域AN和n型有源区域AP的数量可以改变。p型有源区域AN和n型有源区域AP可以是从衬底突出的有源鳍或鳍型有源区域。
n型晶体管TN可以包括p型有源区域AN、栅结构GSN和n型源/漏层SD，p型晶体管TP可以包括n型有源区域AP、栅结构GSP和p型源/漏层SG。
栅结构GSN和栅结构GSP可以在隔离区域SR中彼此接触。以与图1所示的方式不同的方式，在一个示例实施方式中，隔离区域SR中还可以包括局部地设置在栅结构GSN的一部分和栅结构GSP的一部分之间的栅隔离图案。
在第一电源轨区域PR1中，第一掩埋导电层12可以平行于p型有源区域AN沿第一方向(X方向)延伸设置，在第二电源轨区域PR2中，第二掩埋导电层13可以平行于n型有源区域AP沿第一方向(X方向)延伸设置。第一掩埋导电层12在第二方向(Y方向)上可以设置在p型有源区域AN之间，第二掩埋导电层13在第二方向(Y方向)上可以设置在n型有源区域AP之间。第一掩埋导电层12和第二掩埋导电层13可以提供电源电压或地电压。例如，第一掩埋导电层12可以提供电源电压，第二掩埋导电层13可以提供地电压。第一掩埋导电层12可以被称为第一掩埋电源轨，第二掩埋导电层13可以被称为第二掩埋电源轨。在第一电源轨区域PR1和第二电源轨区域PR2中，栅隔离图案80可以设置为重叠第一掩埋导电层12和第二掩埋导电层13。栅隔离图案80可以具有比第一掩埋导电层12和第二掩埋导电层13的每个的宽度小的宽度。
栅隔离图案80可以沿第一方向(X方向)连续地延伸。栅隔离图案80在第二方向(Y方向)上可以设置在栅结构GSN之间以及在栅结构GSP之间。栅结构GSN的一端可以与第一电源轨区域PR1中的栅隔离图案80接触，栅结构GSP的一端可以与第二电源轨区域PR2中的栅隔离图案80接触。
接触插塞91可以设置在n型源/漏层SD上，接触插塞92可以设置在p型源/漏层SG上。接触插塞91可以电连接到n型源/漏层SD，接触插塞92可以电连接到p型源/漏层SG。接触插塞91的一部分可以比n型源/漏层SD延伸得更远。接触插塞91的一部分可以延伸至第一电源轨区域PR1，以与栅隔离图案80接触并且与第一掩埋导电层12接触，从而电连接到第一掩埋导电层12。接触插塞92的一部分可以比p型源/漏层SG延伸得更远。接触插塞92的一部分可以延伸至第二电源轨区域PR2，以与栅隔离图案80接触并且与第二掩埋导电层13接触，从而电连接到第二掩埋导电层13。
第一掩埋导电层12和第二掩埋导电层13可以设置在栅隔离图案80下方。
栅隔离图案80可以包括与接触插塞91和92接触的第一部分、以及与栅结构GSN和GSP接触的第二部分。第一部分可以具有第一宽度W1，第二部分可以具有第二宽度W2。第一宽度W1和第二宽度W2可以相同。在一示例实施方式中，第一宽度W1可以大于第二宽度W2。在一示例实施方式中，第一宽度W1可以小于第二宽度W2。
参照图2和图3，半导体器件可以包括包含n型阱区域NW的衬底11、设置在n型阱区域NW上的n型下有源区域ARP、从n型下有源区域ARP突出的n型有源区域AP、设置在n型下有源区域ARP之间以及n型有源区域AP之间的器件隔离层15、围绕n型有源区域AP上部的栅结构GSP、设置在栅结构GSP之间的栅隔离图案80、设置在栅隔离图案80下方并且在n型有源区域AP之间的掩埋导电层13、设置在n型有源区域AP上的p型源/漏层SG、以及设置在p型源/漏层SG上的接触插塞92a和92b。栅结构GSP可以包括栅绝缘层GI和栅电极GP。在栅结构GSP上，可以设置栅盖层75。器件隔离层15可以包括设置在n型有源区域AP之间的第一隔离层15s、以及设置在n型下有源区域ARP之间的第二隔离层15d。
衬底11可以包括IV族半导体、III-V族化合物半导体或II-VI族化合物半导体。例如，IV族半导体可以包括硅、锗或硅锗。根据示例实施方式，衬底11可以是绝缘体上硅(SOI)衬底或绝缘体上锗(GOI)衬底。
n型阱区域NW、n型下有源区域ARP和n型有源区域AP可以包括n型掺杂剂。例如，当衬底11、n型下有源区域ARP和n型有源区域AP由IV族半导体形成时，n型掺杂剂可以是磷(P)或砷(As)。
n型有源区域AP可以沿第一方向(X方向)延伸，栅结构GSP可以围绕n型有源区域AP的从器件隔离层15向上突出的上部，并且可以沿交叉第一方向(X方向)的第二方向(Y方向)延伸。
栅隔离图案80可以设置于在第二方向(Y方向)上彼此相邻的栅结构GSP之间，并且可以沿第一方向(X方向)延伸。栅结构GSP的一端可以与栅隔离图案80接触。栅隔离图案80例如可以由硅氮化物、硅氮氧化物或其组合形成。
栅结构GSP可以包括栅绝缘层GI和栅电极GP，并且栅绝缘层GI可以设置在n型有源区域AP的上部和栅电极GP之间、在器件隔离层15和栅电极GP之间、以及在栅隔离图案80的侧壁和栅电极GP之间。界面绝缘层可以设置在n型有源区域AP和栅绝缘层GI之间。界面绝缘层可以包括硅氧化物。
栅绝缘层GI可以包括硅氧化物、硅氮化物、硅氮氧化物或高k材料。高k材料可以是指具有比硅氧化物(SiO2)膜的介电常数高的介电常数的电介质材料。高k材料例如可以是铝氧化物(Al2O3)、钽氧化物(Ta2O3)、钛氧化物(TiO2)、钇氧化物(Y2O3)、锆氧化物(ZrO2)、锆硅氧化物(ZrSixOy)、铪氧化物(HfO2)、铪硅氧化物(HfSixOy)、镧氧化物(La2O3)、镧铝氧化物(LaAlxOy)、镧铪氧化物(LaHfxOy)、铪铝氧化物(HfAlxOy)和镨氧化物(Pr2O3)中的一种。
栅电极GP可以通过堆叠在栅绝缘层GI上的多个层形成。所述多个层中的至少部分可以由彼此不同的材料形成。栅电极GP可以包括例如TiN、TaN、WN、WCN、TiAl、TiAlC、TiAlN、铝(Al)、钨(W)、铜(Cu)、钼(Mo)、掺杂多晶硅或其组合。
第二掩埋导电层13可以设置在栅隔离图案80下方并沿第一方向(X方向)延伸。第二掩埋导电层13在第二方向(Y方向)上可以具有比栅隔离图案80的宽度大的宽度。第二掩埋导电层13可以设置在n型有源区域AP之间，并且可以掩埋在器件隔离层15中。第二掩埋导电层13的下部可以插入到衬底11中。绝缘层14可以设置在第二掩埋导电层13和衬底11之间。绝缘层14可以在第二掩埋导电层13的侧壁上延伸。第二掩埋导电层13可以相对于衬底11的上表面具有倾斜的侧壁，并且可以具有这样的上部，该上部拥有比第二掩埋导电层13的下部的宽度大的宽度。第二掩埋导电层13可以包括例如TiN、TaN、WN、WCN、TiAl、TiAlC、TiAlN、铝(Al)、钨(W)、铜(Cu)、钼(Mo)、掺杂多晶硅或其组合。
p型源/漏层SG可以设置在n型有源区域AP的凹陷区域RCS上并沿第二方向(Y方向)延伸。p型源/漏层SG可以在设置于一个n型下有源区域ARP上的n型有源区域AP上一体地形成，并且可以具有倾斜的上表面。第二掩埋导电层13的上表面可以设置为低于n型有源区域AP的凹陷区域RCS的底部。例如，第二掩埋导电层13可以设置为低于p型源/漏层SG的下端。p型源/漏层SG可以是通过选择性外延生长从n型有源区域AP的凹陷区域RCS形成的包括p型掺杂剂的半导体层。
接触插塞92a和92b可以设置在p型源/漏层SG上并沿第二方向(Y方向)延伸。在接触插塞92a和92b中，例如，位于栅隔离图案80一侧的第一接触插塞92a可以比p型源/漏层SG延伸得更远。第一接触插塞92a的长度Wc可以大于p型源/漏层SG的长度Wsd。p型源/漏层SG的一端可以与栅隔离图案80间隔开，第一接触插塞92a的一端可以与栅隔离图案80接触。
第一接触插塞92a在沿第二方向(Y方向)截取的剖面处可以具有横向不对称的形状。第一接触插塞92a可以包括接触部分92v，接触部分92v延伸至第二掩埋导电层13同时覆盖p型源/漏层SG的一端。第一接触插塞92a可以通过接触部分92v电连接到第二掩埋导电层13。第二接触插塞92b在沿第二方向(Y方向)截取的剖面处可以具有横向对称的形状。第二接触插塞92b的下表面可以仅与p型源/漏层SG的上表面接触。
接触插塞92a和92b可以包括例如TiN、TaN、WN、WCN、TiAl、TiAlC、TiAlN、铝(Al)、钨(W)、铜(Cu)、钼(Mo)、掺杂多晶硅或其组合。
蚀刻停止层58可以设置在p型源/漏层SG的一部分的表面上，并且蚀刻停止层58可以延伸到器件隔离层15上。蚀刻停止层58可以覆盖第二掩埋导电层13的上表面的一部分。层间绝缘层60可以设置在蚀刻停止层58上。接触插塞92a和92b可以穿过层间绝缘层60并延伸至p型源/漏层SG。蚀刻停止层58可以包括硅氮化物层或硅氮氧化物层。层间绝缘层60可以包括硅氧化物层。
栅盖层75可以设置在栅结构GSP上。栅盖层75可以包括硅氧化物、硅氮化物和硅氮氧化物中的至少一种。
图4至7是示出根据示例实施方式的半导体器件的剖视图。图4和6是对应于图2的剖视图，图5和7是对应于图3的剖视图。因为图4至图7的示例实施方式与图1至图3的示例实施方式相似，所以将着重于不同之处进行说明。
参照图4和图5，与图2和图3不同，第二掩埋导电层13'可以具有插入到衬底11中的突出部分13p，并且突出部分13p可以具有比第二掩埋导电层13'的设置在衬底11上的下部的宽度小的宽度。
参照图6和图7，与图2和图3不同，第二掩埋导电层13”可以不插入到衬底11中，并且第二掩埋导电层13”的下表面可以设置为高于衬底11的上表面。在第二掩埋导电层13”的下表面和衬底11之间，可以存在器件隔离层15从而能够进行电绝缘。在衬底11和第二掩埋导电层13”之间，不需要设置绝缘层14。
图8是示出根据一示例实施方式的半导体器件的俯视图。图9是半导体器件的沿图8的线I-I'截取的剖视图。图8是对应于图1的俯视图，图9是对应于图2的剖视图。因为图8和图9的示例实施方式与图1至图3的示例实施方式相似，所以将着重于不同之处进行说明。
参照图8和图9，与图2不同，在栅隔离图案80的两侧沿着第二方向(Y方向)上的相同的线设置的第一接触插塞92a和第二接触插塞92b'可以在第二方向上比p型源/漏层SG延伸得更远。第一接触插塞92a和第二接触插塞92b'的每个的长度Wc可以大于每个p型源/漏层SG的长度Wsd。p型源/漏层SG的一端可以与栅隔离图案80间隔开，第一接触插塞92a的一端和第二接触插塞92b'的一端可以与栅隔离图案80接触。连接到第一接触插塞92a的p型源/漏层SG可以是第一源/漏层，连接到第二接触插塞92b'的p型源/漏层SG可以是第二源/漏层。
第一接触插塞92a和第二接触插塞92b'在沿第二方向(Y方向)截取的剖面处可以具有横向不对称的形状。第一接触插塞92a和第二接触插塞92b'可以每个包括接触部分92v，接触部分92v延伸至第二掩埋导电层13同时覆盖p型源/漏层SG的一端。第一接触插塞92a和第二接触插塞92b'可以通过接触部分92v电连接到第二掩埋导电层13。第一接触插塞92a的接触部分92v可以是第一接触部分，第二接触插塞92b'的接触部分92v可以是第二接触部分。
图10是示出根据一示例实施方式的半导体器件的俯视图。因为图10是对应于图1的俯视图并且与图1的示例实施方式相似，所以将着重于不同之处进行说明。
参照图10，栅隔离图案80'可以以比掩埋导电层12和13的每个的长度小的长度沿第一方向(X方向)延伸。栅隔离图案80'在第一电源轨区域PR1和第二电源轨区域PR2中可以排列成单个行。
栅结构GSN的一端可以与第一电源轨区域PR1中的栅隔离图案80'接触，栅结构GSP的一端可以与第二电源轨区域PR2中的栅隔离图案80'接触。
图11是示出根据一示例实施方式的半导体器件的俯视图。图12和图13是示出半导体器件的沿图11的线I-I'和II-II'截取的剖视图。因为图11至图13的示例实施方式与图1至图3的示例实施方式相似，所以将着重于不同之处进行说明。
参照图11，n型晶体管TN'可以设置在第一器件区域R1中，p型晶体管TP'可以设置在第二器件区域R2中。n型晶体管TN'和p型晶体管TP'可以是全包围栅(GAA)场效应晶体管。
在第一器件区域R1中，p型有源区域AN'可以沿第一方向(X方向)延伸，栅结构GSN'可以沿第二方向(Y方向)延伸以交叉p型有源区域AN'，n型源/漏层SD'可以在栅结构GSN'之间设置在p型有源区域AN'上，并且接触插塞91可以设置在n型源/漏层SD'上。p型沟道层可以设置在p型有源区域AN'上方，同时彼此间隔开且与p型有源区域AN'间隔开。栅结构GSN'可以围绕p型沟道层。
在第二器件区域R2中，n型有源区域AP'可以沿第一方向(X方向)延伸，栅结构GSP'可以沿第二方向(Y方向)延伸以交叉n型有源区域AP'，p型源/漏层SG'可以在栅结构GSP'之间设置在n型有源区域AP'上，并且接触插塞92可以设置在p型源/漏层SG'上。n型沟道层CP可以设置在n型有源区域AP'上方，同时彼此间隔开且与n型有源区域AP'间隔开。栅结构GSP'可以围绕n型沟道层CP。
参照图12和图13，半导体器件可以包括其中形成n型阱区域NW的衬底11、设置在n型阱区域NW上的n型下有源区域ARP、从n型下有源区域ARP突出的n型有源区域AP'、设置在n型下有源区域ARP之间以及n型有源区域AP'之间的器件隔离层15、设置在n型有源区域AP'上方同时彼此间隔开且与n型有源区域AP'间隔开的n型沟道层CP、围绕n型沟道层CP的栅结构GSP'、设置在栅结构GSP'之间的栅隔离图案80、设置在栅隔离图案80下方并且在n型有源区域AP'之间的掩埋导电层13、设置在n型有源区域AP'上的p型源/漏层SG'、以及设置在p型源/漏层SG'上的接触插塞92a和92b。
n型有源区域AP'可以沿第二方向(Y方向)延伸，并且n型沟道层CP可以以与n型有源区域AP'相同的长度沿第二方向(Y方向)延伸。
p型源/漏层SG'可以与n型沟道层CP接触。
栅结构GSP'可以沿第二方向(Y方向)延伸，同时围绕n型沟道层CP。
栅隔离图案80可以设置于在第二方向(Y方向)上彼此相邻的栅结构GSP'之间，并且可以沿第一方向(X方向)延伸。栅结构GSP'的一端可以与栅隔离图案80接触。
栅结构GSP'可以包括栅绝缘层GI'和栅电极GP'，并且栅绝缘层GI'可以设置在n型有源区域AP'的上部和栅电极GP'之间、在器件隔离层15和栅电极GP'之间、以及在栅隔离图案80的侧壁和栅电极GP'之间。此外，栅绝缘层GI'可以额外地设置在n型沟道层CP和栅电极GP'之间。界面绝缘层可以设置在n型有源区域AP'和栅绝缘层GI'之间、以及在n型沟道层CP和栅电极GP'之间。
接触插塞92a和92b可以设置在p型源/漏层SG'上，并且可以沿第二方向(Y方向)延伸。在接触插塞92a和92b中，例如，位于栅隔离图案80一侧的第一接触插塞92a可以比p型源/漏层SG'延伸得更远。第一接触插塞92a的长度Wc'可以大于每个p型源/漏层SG'的长度Wsd'。
栅盖层75可以设置在栅结构GSP'上。
尽管上面已说明了第二器件区域R2和第二电源轨区域PR2的剖面结构，第一器件区域R1和第一电源轨区域PR1也可以具有与之相似的剖面结构。
如上所述，根据示例实施方式，通过经由借助于栅隔离图案80、80'自对准的接触插塞92将源/漏层SG和掩埋导电层13、13'、13”电连接，可以获得具有源/漏层SG和掩埋导电层13、13'、13”之间改善的接触电阻特性的半导体器件。
虽然上面已显示并描述了示例实施方式，但是对本领域技术人员将明显的是，可以进行修改和变化而不脱离本发明构思的如由所附权利要求限定的范围。
本申请要求享有2018年9月21日向韩国知识产权局提交的韩国专利申请第10-2018-0113739号的优先权，其全部公开通过引用合并于此。

Claims (20)

1.一种半导体器件，包括：
有源区域，在衬底上沿第一方向延伸；
掩埋导电层，在所述衬底上沿所述第一方向延伸，使得所述掩埋导电层与所述有源区域相邻；
栅电极，沿交叉所述第一方向的第二方向延伸，使得所述栅电极交叉所述有源区域；
源/漏层，在所述栅电极的一侧在所述有源区域上；
栅隔离图案，在所述掩埋导电层上沿所述第一方向延伸，所述栅隔离图案与所述栅电极的一端相邻；以及
接触插塞，在所述源/漏层上并且延伸以电连接到所述掩埋导电层，所述接触插塞与所述栅隔离图案接触，
其中所述栅隔离图案具有彼此相反的第一侧壁和第二侧壁，
其中所述接触插塞与所述栅隔离图案的所述第一侧壁的第一部分接触，
其中所述栅电极的一端面对所述栅隔离图案的所述第一侧壁的第二部分，以及
其中所述栅隔离图案与所述掩埋导电层的至少一部分接触。
2.根据权利要求1所述的半导体器件，其中所述栅隔离图案沿着所述掩埋导电层连续地延伸。
3.根据权利要求1所述的半导体器件，其中所述栅隔离图案具有比所述掩埋导电层的长度小的长度。
4.根据权利要求1所述的半导体器件，其中所述栅隔离图案包括具有不同宽度的部分。
5.根据权利要求1所述的半导体器件，其中相比于所述源/漏层沿所述第二方向延伸，所述接触插塞沿所述第二方向延伸得更远。
6.根据权利要求1所述的半导体器件，其中所述接触插塞包括接触部分，所述接触部分覆盖所述源/漏层的一端并且延伸至所述掩埋导电层。
7.根据权利要求1所述的半导体器件，其中
所述有源区域包括凹陷区域，所述源/漏层在所述有源区域的所述凹陷区域上，以及
相对于所述衬底，所述掩埋导电层的上表面低于所述有源区域的所述凹陷区域的底部。
8.根据权利要求1所述的半导体器件，其中所述掩埋导电层的下部在所述衬底中。
9.根据权利要求1所述的半导体器件，其中
所述掩埋导电层包括上部和下部，相对于所述衬底，所述上部高于所述下部，以及
所述掩埋导电层具有倾斜的侧壁，使得所述掩埋导电层的所述上部的宽度大于所述掩埋导电层的所述下部的宽度。
10.根据权利要求1所述的半导体器件，其中
所述掩埋导电层包括突出部分和下部，所述下部在所述衬底上，所述突出部分突出到所述衬底中，以及
所述突出部分的宽度小于所述掩埋导电层的所述下部的宽度。
11.根据权利要求1所述的半导体器件，其中相对于所述衬底，所述掩埋导电层的下表面高于所述衬底的上表面。
12.根据权利要求1所述的半导体器件，还包括：
在所述掩埋导电层和所述衬底之间的绝缘层。
13.一种半导体器件，包括：
至少两个有源区域，包括第一有源区域和第二有源区域，所述至少两个有源区域的每个在衬底上沿第一方向延伸；
至少两个栅电极，包括第一栅电极和第二栅电极，所述至少两个栅电极的每个沿交叉所述第一方向的第二方向延伸，使得所述至少两个栅电极在所述第二方向上彼此相邻；
栅隔离图案，在所述第一栅电极和所述第二栅电极之间沿所述第一方向延伸；
掩埋导电层，在所述栅隔离图案下方沿所述第一方向延伸；
至少两个源/漏层，包括分别在所述第一有源区域和所述第二有源区域上的第一源/漏层和第二源/漏层；以及
至少两个接触插塞，包括分别在所述第一源/漏层和所述第二源/漏层上的第一接触插塞和第二接触插塞，所述第一接触插塞和所述第二接触插塞分别包括第一接触部分和第二接触部分，所述第一接触部分和所述第二接触部分每个延伸以电连接到所述掩埋导电层，使得每个延伸到所述掩埋导电层的所述第一接触部分和所述第二接触部分与所述栅隔离图案的侧壁接触，同时所述第一接触插塞和所述第二接触插塞在所述第二方向上具有横向不对称的形状，
其中所述栅隔离图案与所述掩埋导电层的至少一部分接触。
14.根据权利要求13所述的半导体器件，其中所述栅隔离图案沿着所述掩埋导电层在所述第一方向上延伸。
15.根据权利要求13所述的半导体器件，其中所述至少两个接触插塞中的至少一个比所述至少两个源/漏层中的至少一个沿所述第二方向延伸得更远。
16.根据权利要求13所述的半导体器件，其中所述第一接触部分覆盖所述第一源/漏层的一端，以及
所述第一接触插塞配置为经由所述栅隔离图案的所述侧壁在所述掩埋导电层上自对准。
17.根据权利要求16所述的半导体器件，其中所述第二接触部分延伸至所述掩埋导电层同时覆盖所述第二源/漏层的一端，以及
所述第二接触插塞配置为经由所述栅隔离图案的所述侧壁在所述掩埋导电层上自对准。
18.根据权利要求13所述的半导体器件，其中所述掩埋导电层的下部在所述衬底中。
19.根据权利要求13所述的半导体器件，其中相对于所述衬底，所述掩埋导电层的下表面高于所述衬底的上表面。
20.一种半导体器件，包括：
在衬底上的栅结构；
在所述栅结构的一侧的源/漏层；
相对于所述衬底低于所述源/漏层的掩埋导电层；
在所述掩埋导电层上的栅隔离图案，所述栅隔离图案与所述栅结构接触；以及
在所述源/漏层上的接触插塞，所述接触插塞与所述栅隔离图案接触，所述接触插塞延伸至所述掩埋导电层同时覆盖所述源/漏层的一端，
其中所述栅隔离图案具有彼此相反的第一侧壁和第二侧壁，
其中所述接触插塞与所述栅隔离图案的所述第一侧壁的第一部分接触，
其中所述栅结构的一端与所述栅隔离图案的所述第一侧壁的第二部分接触，以及
其中所述栅隔离图案与所述掩埋导电层的至少一部分接触。
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