CN110911492A - 电子器件和制造该电子器件的方法 - Google Patents

电子器件和制造该电子器件的方法 Download PDF

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CN110911492A
CN110911492A CN201910226482.5A CN201910226482A CN110911492A CN 110911492 A CN110911492 A CN 110911492A CN 201910226482 A CN201910226482 A CN 201910226482A CN 110911492 A CN110911492 A CN 110911492A
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layer
electronic device
substrate
carbon
channel element
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CN110911492B (zh
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许镇盛
李润姓
赵常玹
申建旭
申铉振
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

提供了一种电子器件和制造该电子器件的方法。一种电子器件可以包括：衬底；在衬底上的栅电极；在衬底和栅电极之间的铁电层；以及在衬底和铁电层之间的碳层。该碳层可以具有sp2键合结构。

Description

电子器件和制造该电子器件的方法
技术领域
本公开涉及电子器件和制造该电子器件的方法。
背景技术
一般的硅(Si)基电子器件的工作特性不能被容易地改善，并且这样的器件不能容易地按比例缩小。例如，在工作电压-电流特性方面，一般的Si基逻辑晶体管的亚阈值摆幅(SS)会被限制为约60mV/dec。因而，当逻辑晶体管的尺寸减小时，其工作电压不能容易地降低到约0.8V以下。因此，功率密度会增大并且逻辑晶体管不能容易地按比例缩小。
发明内容
提供了电子器件和制造该电子器件的方法。
额外的方面将部分地在下面的描述中阐述，并且部分地将从该描述明显，或者可以通过对所给出的实施方式的实践而掌握。
根据一实施方式的一方面，一种电子器件可以包括：衬底；在衬底上的栅电极；在衬底和栅电极之间的铁电层；以及在衬底和铁电层之间的碳层。碳层可以具有sp2键合结构。
在一些实施方式中，沟道元件可以包括沟道元件、源电极和漏电极。沟道元件可以在衬底中在与栅电极对应的位置处。源电极和漏电极可以被提供在沟道元件的两侧。
在一些实施方式中，碳层可以包括包含纳米尺寸的晶体的纳米晶体石墨烯。纳米晶体石墨烯可以包括具有约0.5nm至约100nm的尺寸的晶体。
在一些实施方式中，在纳米晶体石墨烯中，具有sp2键合结构的碳与全部碳的比率可以为约50％至约99％。纳米晶体石墨烯可以包含约1原子百分比(at％)至约20at％的氢。电子器件还可以包括在衬底和碳层之间的绝缘层。
在一些实施方式中，电子器件还可以包括在碳层和铁电层之间的绝缘层。
在一些实施方式中，栅电极可以包括导电金属或具有sp2键合结构的碳材料。
在一些实施方式中，铁电层可以包括包含硅(Si)、铝(Al)、铪(Hf)和锆(Zr)中的至少一种的氧化物。该氧化物还可以包括掺杂剂。碳层可以具有约0.4nm至约100nm的厚度。
根据另一实施方式的一方面，一种制造电子器件的方法可以包括：制备包括沟道元件的衬底；在沟道元件上沉积具有sp2键合结构的碳层；在碳层上沉积铁电层；在铁电层上沉积栅电极；以及通过退火工艺使铁电层结晶。
在一些实施方式中，制备衬底可以包括在沟道元件的两侧形成源电极和漏电极。
在一些实施方式中，该方法还可以包括在衬底和碳层之间产生绝缘层。
在一些实施方式中，该方法还可以包括在碳层和铁电层之间产生绝缘层。
在一些实施方式中，沉积碳层可以通过化学气相沉积(CVD)或原子层沉积(ALD)执行。
在一些实施方式中，碳层可以包括包含纳米尺寸的晶体的纳米晶体石墨烯。沉积碳层可以包括形成碳层使得碳层的厚度在约0.4nm至约100nm的范围内。
在一些实施方式中，沉积铁电层可以通过CVD或ALD执行。
根据另一实施方式的一方面，一种电子器件可以包括：沟道元件；连接到沟道元件的相对端的源电极和漏电极；在沟道元件上的栅电极；在沟道元件与栅电极之间的铁电层；以及在沟道元件与铁电层之间的碳层。栅电极可以与源电极、漏电极和沟道元件间隔开。碳层可以配置为限制金属或氧中的至少一种从铁电层扩散到沟道元件。
在一些实施方式中，该电子器件还可以包括在沟道元件上的绝缘层。该绝缘层可以在沟道元件与铁电层之间，或者该绝缘层可以在栅电极与铁电层之间。
在一些实施方式中，碳层可以包括包含纳米尺寸的晶体的纳米晶体石墨烯。
在一些实施方式中，沟道元件可以是沟道层或者是衬底的突出部分。
在一些实施方式中，铁电层可以包括包含硅(Si)、铝(Al)、铪(Hf)和锆(Zr)中的至少一种的氧化物。
附图说明
从以下结合附图对实施方式的描述，这些和/或其它的方面将变得明显并更容易理解，附图中：
图1是根据一示例实施方式的电子器件的剖视图；
图2是用于描述根据一示例实施方式的电子器件的亚阈值摆幅(SS)特性的改善的曲线图；
图3是根据另一示例实施方式的电子器件的剖视图；
图4是根据另一示例实施方式的电子器件的剖视图；
图5是根据另一示例实施方式的电子器件的剖视图；
图6A至图6F是用于描述根据一示例实施方式的制造电子器件的方法的剖视图；
图7A是形成在硅(Si)衬底上的晶体石墨烯(SLG)的扫描电子显微镜(SEM)图像；
图7B是形成在Si衬底上的纳米晶体石墨烯(ncG)和铪锆氧化物(HZO)的SEM图像；
图8A至图8D示出了根据一示例实施方式的制造电子器件的方法；以及
图9A至图9D示出了根据一示例实施方式的制造电子器件的方法。
具体实施方式
现在将详细参照实施方式，其示例在附图中示出，其中相同的附图标记始终表示相同的元件。在这方面，当前的实施方式可以具有不同的形式，并且不应被解释为限于在这里阐述的描述。因此，下面通过参照附图仅描述了实施方式以解释各方面。如这里使用的，诸如“……中的至少一个”的表述当在一列元件之后时，修饰整列元件而不修饰该列中的个别元件。
将理解，当一元件被称为“在”另一元件“上”时，它可以直接在所述另一元件上，或者也可以存在居间的元件。如这里所用的，单数形式“一”、“一个”和“该”旨在也包括复数形式，除非上下文另外清楚地指示。还将理解，术语“包含”、“包含……的”、“包括”和/或“包括……的”，当在这里使用时，表明所述特征、整数、步骤、操作、元件和/或部件的存在，但是不排除一个或更多个其它特征、整数、步骤、操作、元件、部件和/或其组的存在或添加。
在整个说明书中，“该”或类似的说明性表述可以指单数形式和复数形式两者。此外，除非方法的操作顺序被清楚地指出或与上下文矛盾，否则所述操作可以以适当可变的顺序执行，而不限于所描述的顺序。所有的示例或介绍示例的术语仅用于详细描述本公开而不限制本公开的范围，除非在权利要求书中限定。
在以下描述中，根据实施方式的电子器件是基于半导体的器件，并可以具有包括铁电体和栅电极的栅极堆叠结构。电子器件可以包括例如逻辑器件或存储器件。
图1是根据一示例实施方式的电子器件100的剖视图。
参照图1，电子器件100包括衬底110以及顺序地堆叠在衬底110上的碳层130、铁电层140和栅电极150。沟道元件115可以在对应于栅电极150的位置处被提供在衬底110中，例如，沟道元件115可以被提供在衬底110的突出部分中，并且源电极(S)121和漏电极(D)122可以被提供在沟道元件115的两侧。
源电极121可以电连接到沟道元件115的一侧，漏电极122可以电连接到沟道元件115的另一侧。源电极121和漏电极122可以通过将杂质注入到衬底110的不同区域中来形成，并且衬底110的在源电极121和漏电极122之间的区域可以被定义为沟道元件115。
衬底110可以是半导体衬底。例如，衬底110可以是硅(Si)衬底，或者可以是包括除了Si之外的材料(例如锗(Ge)、硅锗(SiGe)或III-Ⅴ族半导体)的衬底。在这种情况下，沟道元件115可以包括Si、Ge、SiGe或III-Ⅴ族半导体。衬底110的材料不限于上述示例，而是可以被各种各样地改变。如下面将描述的，沟道元件115可以不被提供为衬底110的一部分，而可以被提供为与衬底110区别开的材料层。
碳层130被提供在衬底110的沟道元件115的上表面上。碳层130可以包括具有sp2键合结构的碳。具有sp2键合结构的碳层130可以包括包含纳米尺寸的晶体的纳米晶体石墨烯。这里，纳米晶体石墨烯是指包括纳米尺寸的晶体的石墨烯。例如，纳米晶体石墨烯可以包括具有大于0nm且小于或等于约100nm的尺寸的晶体。
现在将比较正常晶体石墨烯、根据实施方式的纳米晶体石墨烯、和非晶碳层。
具有sp2键合结构的碳与全部碳的比率可以通过经由X射线光电子能谱(XPS)分析测量D参数来获得。具体地，在XPS分析中，碳的俄歇(Auger)谱的峰形状随着具有sp2键合结构的碳与全部碳的比率而变化。在通过对峰形状进行微分而获得的D参数光谱上的最高点和最低点之间的间隙用作D参数。因此，正常晶体石墨烯、纳米晶体石墨烯和非晶碳层可以通过测量碳的Auger谱上的D参数来识别。下面将描述的氢含量可以通过经由例如卢瑟福背散射光谱法(RBS)进行成分分析来获得。
正常晶体石墨烯也被称为本征石墨烯，可以包括具有大于例如约100nm的尺寸的晶体。正常晶体石墨烯在碳的Auger谱上的D参数可以为约23eV。在这种情况下，具有sp2键合结构的碳与全部碳的比率可以为几乎100％。正常晶体石墨烯可以几乎不含氢。此外，正常晶体石墨烯可以具有例如约2.1g/cc的密度并具有例如约100欧姆/平方(Ohm/sq)至约300Ohm/sq的薄层电阻。
纳米晶体石墨烯可以包括比正常晶体石墨烯的晶体小的晶体。具体地，例如，纳米晶体石墨烯可以包括具有约0.5nm至约100nm的尺寸的晶体。纳米晶体石墨烯在碳的Auger谱上的D参数可以为约18eV至约22.9eV。在这种情况下，具有sp2键合结构的碳与全部碳的比率可以为例如约50％至约99％。纳米晶体石墨烯可以包含例如约1原子百分比(at％)至约20at％的氢。纳米晶体石墨烯可以具有例如约1.6g/cc至约2.1g/cc的密度和大于例如约1000Ohm/sq的薄层电阻。
非晶碳层在碳的Auger谱上的D参数可以具有在金刚石的D参数(例如约13eV)与纳米晶体石墨烯的D参数之间的值。在这种情况下，具有sp2键合结构的碳与全部碳的比率可以为例如约30％至约50％。非晶碳层可以含有例如大于约20at％的氢。
具有sp2键合结构的碳层130可以是包括纳米晶体石墨烯的碳层。碳层130可以在衬底110的沟道元件115的上表面上。碳层130可以通过借助例如化学气相沉积(CVD)或原子层沉积(ALD)将纳米晶体石墨烯沉积在衬底110的沟道元件115的上表面上而形成。这里，碳层130可以包括例如约1层至约100层的纳米晶体石墨烯，但是不限于此。碳层130可以具有约0.4nm至约100nm的厚度。例如，碳层130可以具有约0.4nm至约10nm的厚度。然而，碳层130不限于此。
铁电层140可以被提供在具有sp2键合结构的碳层130的上表面上。铁电体可以在结晶材料结构的晶胞中具有非中心对称电荷分布，因此可以具有自发电偶极子，即，自发极化。铁电体可以在没有施加外部电场的情况下通过偶极子具有剩余极化。铁电体的极化方向可以通过外部电场以畴为单位转向。取决于外部电场，铁电体可以具有或可以不具有磁滞特性，并且取决于铁电体是否具有磁滞特性，电子器件100可以被实现为逻辑器件或存储器件。
如下面将描述的，铁电层140可以通过例如CVD或ALD在具有sp2键合结构的碳层130的上表面上沉积某种铁电材料作为非晶铁电层、然后经由退火工艺使非晶铁电层结晶而形成。
铁电层140可以包括包含例如Si、铝(Al)、铪(Hf)和锆(Zr)中的至少一种的氧化物。具体地，例如，铁电层140可以包括Hf基氧化物和Zr基氧化物中的至少一种。这里，Hf基氧化物可以包括例如HfO或HfZrO，Zr基氧化物可以包括例如ZrO。
在一些实施方式中，铁电层140还可以包括掺杂剂。掺杂剂可以包括例如Si、Al、Zr、钇(Y)、镧(La)、钆(Gd)、锶(Sr)和Hf中的至少一种，但是不限于此。当铁电层140包括掺杂剂时，掺杂剂可以在各处以相同的浓度掺杂或者在不同的区域中以不同的浓度掺杂。或者，铁电层140的不同区域可以以不同的掺杂剂掺杂。
栅电极150可以被提供在铁电层140的上表面上。这里，栅电极150可以位于沟道元件115的与衬底110相反的一侧。栅电极150可以包括导电金属。或者，栅电极150可以包括具有sp2键合结构的碳材料。这里，具有sp2键合结构的碳材料可以包括例如正常晶体石墨烯或纳米晶体石墨烯。
因为根据当前实施方式的电子器件100包括铁电层140，所以可以降低电子器件100的亚阈值摆幅(SS)。
图2是用于描述根据一示例实施方式的逻辑晶体管的SS特性的改善的曲线图。在图2中，曲线A表示一般的Si基逻辑晶体管的工作电压Vg-电流Id特性，曲线B表示根据一示例实施方式的逻辑晶体管的工作电压Vg-电流Id特性。
参照图2，一般的Si基逻辑晶体管的SS可以被限制为约60mV/dec。然而，根据一示例实施方式的逻辑晶体管使用铁电层，因此，可以通过由于铁电体中的畴变而发生的电压放大将SS降低到60mV/dec以下。
在根据当前实施方式的电子器件100中，由于具有sp2键合结构的碳层130可以被提供在铁电层140和沟道元件115之间，所以可以限制和/或防止在铁电层140中的金属或氧扩散到衬底110中。
例如，在包括铁电层和金属层的Si基电子器件中，由于铁电层中的金属或氧因退火工艺中的高温而扩散到Si衬底中，所以会发生电泄漏。此外，因为形成了不期望的Si氧化物层或硅化物，所以电子器件的特性会劣化。然而，在根据当前实施方式的电子器件100中，因为具有sp2键合结构的碳层130可以被提供在铁电层140和衬底110之间，所以具有sp2键合结构的碳层130可以限制和/或防止铁电层140中的金属或氧在高温退火工艺中扩散到衬底110中。因而，可以限制和/或防止电流泄漏，并且还可以限制和/或防止形成不期望的Si氧化物层或硅化物。此外，由于即使当具有sp2键合结构的碳层130可以具有约1nm的小厚度时扩散限制和/或防止效果也是可实现的，所以可以减小电子器件100的总厚度。因此，可以容易地按比例缩小电子器件100。
此外，在根据当前实施方式的电子器件100中，由于具有sp2键合结构的碳层130可以具有高电荷密度，所以可以在碳层130和沟道元件115之间形成等电势。因此，具有sp2键合结构的碳层130可以屏蔽由于铁电层140的多畴结构而引起的不均匀电势，因此，可以提高电子器件100的特性的均匀性。
图3是根据另一示例实施方式的电子器件200的剖视图。以下的描述集中在与前述实施方式的差异上。
参照图3，电子器件200包括衬底210以及顺序地堆叠在衬底210上的沟道层215、碳层230、铁电层240和栅电极250，其中碳层230可以具有sp2键合结构。源电极221和漏电极222可以被提供在沟道层215的两侧。
衬底210可以是半导体衬底。例如，衬底210可以是Si、Ge、SiGe或III-Ⅴ族半导体，但不限于此。沟道层215可以被提供在衬底210的上表面上。沟道层215可以不被提供为衬底210的一部分，而可以被提供为与衬底210区别开的材料层。沟道层215可以包括例如氧化物半导体、氮化物半导体、氮氧化物半导体、二维(2D)材料、量子点(QD)和有机半导体中的至少一种。这里，氧化物半导体可以包括例如InGaZnO，2D材料可以包括例如过渡金属二硫化物(TMD)或石墨烯，QD可以包括例如胶体QD或纳米晶体QD。当沟道层215包括石墨烯时，石墨烯可以被处理、加厚(例如，5个单层以上的石墨烯)和/或变窄(例如，小于10nm)从而使得沟道层215中的石墨烯的带隙大于0eV。然而，上述材料仅是示例，当前实施方式不限于此。
源电极221和漏电极222可以被提供在沟道层215的两侧。源电极221可以连接到沟道层215的一侧，漏电极222可以连接到沟道层215的另一侧。源电极221和漏电极222可以由导电材料诸如金属、金属化合物或导电聚合物制成。
以上已经描述了顺序地堆叠在沟道层215上的碳层230、铁电层240和栅电极250，因此这里将不提供其详细描述。
图4是根据另一示例实施方式的电子器件300的剖视图。以下的描述集中在与前述实施方式的差异上。
参照图4，电子器件300包括衬底310以及顺序地堆叠在衬底310上的绝缘层360、碳层330、铁电层340和栅电极350，其中碳层330可以具有sp2键合结构。沟道元件315可以在对应于栅电极350的位置处提供在衬底310中，并且源电极(S)321和漏电极(D)322可以被提供在沟道元件315的两侧。
源电极321可以电连接到沟道元件315的一侧，漏电极322可以电连接到沟道元件315的另一侧。源电极321和漏电极322可以通过将杂质注入到衬底310的不同区域中来形成，并且衬底310的在源电极321和漏电极322之间的区域可以被定义为沟道元件315。衬底310可以是半导体衬底。例如，衬底310可以是Si、Ge、SiGe或III-Ⅴ族半导体，但是不限于此。与此同时，沟道元件315可以不被提供为衬底310的一部分，而可以被提供为与衬底310区别开的材料层。
绝缘层360被提供在沟道元件315的上表面上。绝缘层360可以具有大于0nm且等于或小于例如约5nm的小厚度。然而，绝缘层360不限于此，而是可以具有大于约5nm的厚度。绝缘层360可以包括例如Si氧化物、Al氧化物、Hf氧化物、Zr氧化物或2D绝缘体诸如六方氮化硼(h-BN)。然而，绝缘层360的材料不限于此，而可以改变。绝缘层360可以用于抑制或防止电泄漏，并且还可以用于栅极堆叠结构中的电容匹配。
具有sp2键合结构的碳层330可以被提供在绝缘层360的上表面上。这里，具有sp2键合结构的碳层330可以包括包含纳米尺寸的晶体的纳米晶体石墨烯。这里，纳米晶体石墨烯可以包括比正常晶体石墨烯的晶体小的晶体。具体地，例如，纳米晶体石墨烯可以包括具有约0.5nm至约100nm的尺寸的晶体。具有sp2键合结构的碳与全部碳的比率可以为例如约50％至约99％。纳米晶体石墨烯可以含有例如约1at％至约20at％的氢。纳米晶体石墨烯可以具有例如约1.6g/cc至约2.1g/cc的密度和大于例如约1000Ohm/sq的薄层电阻。
具有sp2键合结构的碳层330可以具有约0.4nm至约100nm的厚度。例如，碳层330可以具有约0.4nm至约10nm的厚度。然而，碳层330不限于此。如上所述，具有sp2键合结构的碳层330可以限制和/或防止铁电层340中的金属或氧经过绝缘层360扩散到衬底310中。此外，因为即使当具有sp2键合结构的碳层330可以具有约1nm的小厚度时扩散限制和/或防止效果也是可实现的，所以可以减小电子器件300的总厚度。因此，可以容易地按比例缩小电子器件100。具有sp2键合结构的碳层330可以具有高电荷密度，因此可以提高电子器件300的特性的均匀性。
铁电层340可以被提供在具有sp2键合结构的碳层330的上表面上。铁电层340可以包括包含例如Si、Al、Hf和Zr中的至少一种的氧化物。具体地，例如，铁电层340可以包括Hf基氧化物和Zr基氧化物中的至少一种。这里，Hf基氧化物可以包括例如HfO或HfZrO，Zr基氧化物可以包括例如ZrO。
在一些实施方式中，铁电层340还可以包括掺杂剂。掺杂剂可以包括例如Si、Al、Zr、Y、La、Gd、Sr和Hf中的至少一种，但是不限于此。当铁电层340包括掺杂剂时，掺杂剂可以在各处以相同的浓度掺杂或者在不同的区域中以不同的浓度掺杂。或者，铁电层340的不同区域可以以不同的掺杂剂掺杂。
栅电极350可以被提供在铁电层340的上表面上。栅电极350可以包括导电金属。或者，栅电极350可以包括具有sp2键合结构的碳材料。在这里，具有sp2键合结构的碳材料可以包括例如正常晶体石墨烯或纳米晶体石墨烯。由于铁电层340，可以降低电子器件300的SS。
图5是根据另一示例实施方式的电子器件400的剖视图。以下的描述集中在与前述实施方式的差异上。
参照图5，电子器件400包括衬底410以及顺序地堆叠在衬底410上的碳层430、绝缘层460、铁电层440和栅电极450，其中碳层430具有sp2键合结构。沟道元件415可以在对应于栅电极450的位置处被提供在衬底410中，并且源电极(S)421和漏电极(D)422可以被提供在沟道元件415的两侧。
具有sp2键合结构的碳层430可以被提供在沟道元件415的上表面上。这里，具有sp2键合结构的碳层430可以包括包含纳米尺寸的晶体的纳米晶体石墨烯。具有sp2键合结构的碳层430可以具有约0.4nm至约100nm的厚度。绝缘层460可以被提供在具有sp2键合结构的碳层430的上表面上。绝缘层460可以具有等于或小于例如约5nm的小厚度。然而，绝缘层460不限于此。绝缘层460可以包括例如Si氧化物、Al氧化物、Hf氧化物、Zr氧化物或2D绝缘体诸如h-BN。
铁电层440可以被提供在绝缘层460的上表面上。铁电层440可以包括包含例如Si、Al、Hf和Zr中的至少一种的氧化物。铁电层440还可以包括掺杂剂。掺杂剂可以包括例如Si、Al、Zr、Y、La、Gd、Sr和Hf中的至少一种，但是不限于此。栅电极450可以被提供在铁电层440的上表面上。栅电极450可以包括导电金属或具有sp2键合结构的碳材料。
图6A至图6F是用于描述根据一示例实施方式的制造电子器件500的方法的剖视图。
参照图6A，可以制备包括沟道元件515、源电极(S)521和漏电极(D)522的衬底510。源电极521和漏电极522可以通过将杂质注入到衬底510的不同区域中形成，并且衬底510的在源电极521和漏电极522之间的区域可以被定义为沟道元件515。衬底510可以包括半导体(例如Si、Ge、SiGe或III-Ⅴ族半导体)。在这种情况下，沟道元件515还可以包括Si、Ge、SiGe或III-Ⅴ族半导体，像衬底510一样。衬底510的材料不限于上述示例，而可以各种各样地改变。形成源电极521和漏电极522的时机可以变化。例如，源电极521和漏电极522可以在可形成栅电极550(见图6D)之后形成在衬底510中，如将在下面描述的。
沟道元件515可以不形成为衬底510的一部分，而可以在衬底510的上表面上形成为与衬底510区别开的材料层。在这种情况下，沟道元件515可以包括各种材料。例如，沟道元件515可以包括例如氧化物半导体、氮化物半导体、氮氧化物半导体、2D材料、QD和有机半导体中的至少一种。氧化物半导体可以包括例如InGaZnO，2D材料可以包括例如TMD或石墨烯，QD可以包括例如胶体QD或纳米晶体QD。然而，上述材料仅是示例，当前实施方式不限于此。
参照图6B，可以在衬底510的沟道元件515的上表面上形成具有sp2键合结构的碳层530。这里，具有sp2键合结构的碳层530可以包括包含纳米尺寸的晶体的纳米晶体石墨烯。例如，纳米晶体石墨烯可以包括具有约0.5nm至约100nm的尺寸的晶体。在纳米晶体石墨烯中，具有sp2键合结构的碳与全部碳的比率可以为约50％至约99％，并且可以含有约1at％至约20at％的氢。纳米晶体石墨烯可以具有例如约1.6g/cc至约2.1g/cc的密度和大于例如约1000Ohm/sq的薄层电阻。
具有sp2键合结构的碳层530可以通过例如CVD或ALD在衬底510的沟道元件515的上表面上沉积纳米晶体石墨烯来形成。这里，具有sp2键合结构的碳层530可以包括例如约1层至约100层的纳米晶体石墨烯，但是不限于此。碳层130可以具有约0.4nm至约100nm的厚度，但是不限于此。
参照图6C，可以在具有sp2键合结构的碳层530的上表面上形成非晶铁电层540'。非晶铁电层540'可以通过借助例如CVD或ALD在具有sp2键合结构的碳层530的上表面上沉积某种铁电材料来形成。
非晶铁电层540'可以是具有高介电常数的薄膜。例如，非晶铁电层540'的介电常数可以等于或大于约10。因此，非晶铁电层540'可以用作高k电介质层。非晶铁电层540'可以包括包含例如Si、Al、Hf和Zr中的至少一种的氧化物。具体地，例如，非晶铁电层540'可以包括Hf基氧化物和Zr基氧化物中的至少一种。这里，Hf基氧化物可以包括例如HfO或HfZrO，Zr基氧化物可以包括例如ZrO。非晶铁电层540'还可以包括掺杂剂。这里，掺杂剂可以包括Si、Al、Zr、Y、La、Gd、Sr和Hf中的至少一种。当非晶铁电层540'包括掺杂剂时，掺杂剂可以在各处以相同的浓度掺杂或者在不同的区域中以不同的浓度掺杂。或者，非晶铁电层540'的不同区域可以以不同的掺杂剂掺杂。非晶铁电层540'可以在正形成非晶铁电层540'时被掺杂，或者在形成非晶铁电层540'之后在单独的工艺中被掺杂。
参照图6D，可以在非晶铁电层540'的上表面上形成栅电极550。栅电极550可以通过例如CVD、物理气相沉积(PVD)或ALD在非晶铁电层540'的上表面上沉积导电材料来形成。栅电极550可以包括导电金属。或者，栅电极550可以包括具有sp2键合结构的碳材料。这里，具有sp2键合结构的碳材料可以包括例如正常晶体石墨烯或纳米晶体石墨烯。
参照图6E，执行用于使非晶铁电层540'结晶的退火工艺。退火工艺可以在例如约400℃至约1000℃的温度进行。退火工艺可以在约1分钟内进行。然而，退火工艺的温度和时间不限于此，而可以被各种各样地改变。非晶铁电层540'可以通过退火工艺结晶。当非晶铁电层540'完全结晶时，可以如图6F所示地获得铁电层540，因此可以制造电子器件500。
制造电子器件500的上述方法还可以包括：在形成具有sp2键合结构的碳层530之前，在衬底510的沟道元件515的上表面上产生绝缘层(未示出)。在这种情况下，具有sp2键合结构的碳层530可以形成在该绝缘层的上表面上。绝缘层可以通过例如CVD或ALD在衬底510的沟道元件515的上表面上沉积某种绝缘材料来形成。绝缘层可以具有等于或小于例如约5nm的小厚度，但是不限于此。绝缘层可以包括例如Si氧化物、Al氧化物、Hf氧化物、Zr氧化物或2D绝缘体诸如h-BN，但是不限于此。
制造电子器件500的上述方法还可以包括：在形成具有sp2键合结构的碳层530之后且在形成非晶铁电层540'之前，在具有sp2键合结构的碳层530的上表面上产生绝缘层(未示出)。在这种情况下，非晶铁电层540'可以形成在该绝缘层的上表面上。
图7A是形成在Si衬底上的正常晶体石墨烯(SLG)的扫描电子显微镜(SEM)图像。在图7A中，SLG表示单层石墨烯。图7B是形成在Si衬底上的纳米晶体石墨烯(ncG)和铪锆氧化物(HZO)的SEM图像。
参照图7A，SiO2绝缘层可以形成在Si衬底的上表面上，并且SLG可以形成在SiO2绝缘层的上表面上。这里，示出了在SLG的上表面上没有形成诸如HZO的铁电层。
参照图7B，SiO2绝缘层可以形成在Si衬底的上表面上，并且ncG可以形成在SiO2绝缘层的上表面上。用作铁电层的HZO可以在ncG的上表面上形成至约3nm的厚度。因此，示出了ncG对形成在其上的铁电层提供高粘合力。
图8A至图8D示出根据一示例实施例的制造电子器件的方法。
参照图8A，沟道膜可以形成在衬底210上并且被图案化为沟道层215。然后，可以在沟道层215的端部上形成源电极221和漏电极222。
参照图8B，然后可以在沟道层215上形成碳层230。碳层230可以被图案化，如图8B所示，使得碳层230的侧部可以与源电极221和漏电极222间隔开。
参照图8C，可以在碳层230上形成非晶铁电层240'和栅电极250。
参照图8D，可以对非晶铁电层240'执行退火工艺。退火工艺可以将非晶铁电层240'结晶成在图3中示出的铁电层240。
图9A至图9D示出根据一示例实施例的制造电子器件的方法。
图9A至图9C类似于图6B至图6F，除了可以在形成碳层330之前形成绝缘层360之外。
参照图9A，可以在衬底310上形成绝缘层360，并且可以在绝缘层330上形成碳层330。绝缘层360可以直接形成在衬底310上。
参照图9B，可以在碳层330上形成非晶铁电层340'。
参照图9C，可以在非晶铁电层340'上形成栅电极350。
参照图9D，可以对非晶铁电层340'执行退火工艺。退火工艺可以使非晶铁电层340'结晶成图4中示出的铁电层340。根据前述实施方式，使用铁电层，可以实现能够通过由于铁电体中的畴变而发生的电压放大来降低SS的电子器件。此外，通过在铁电层和沟道元件之间提供具有sp2键合结构的碳层，可以限制和/或防止在退火工艺中铁电层中的金属或氧扩散到衬底中。因而，可以限制和/或防止电流泄漏，并且还可以限制和/或防止形成不期望的Si氧化物层或硅化物。此外，因为即使当具有sp2键合结构的碳层可以具有约1nm的小厚度时扩散限制和/或防止效果也是可实现的，所以可以减小电子器件的总厚度。因此，可以容易地按比例缩小电子器件。
因为具有sp2键合结构的碳层可以具有高电荷密度，所以可以在碳层和沟道元件之间形成等电势。因此，具有sp2键合结构的碳层可以由于铁电层的多畴结构而屏蔽不均匀的电势，因此可以提高电子器件的特性的均匀性。包括纳米晶体石墨烯的碳层可以为沉积在其上的铁电层提供高粘合力。
应当理解，这里描述的实施方式应当被认为仅是描述性的，而不是为了限制的目的。每个实施方式内的特征或方面的描述应当被认为可用于其它实施方式中的其它类似特征或方面。
尽管已经参照附图描述了一个或更多个实施方式，但是本领域普通技术人员将理解，可以在其中进行形式和细节上的各种改变，而没有脱离由以下的权利要求书限定的精神和范围。
本申请要求于2018年9月18日在韩国知识产权局提交的韩国专利申请第10-2018-0111596号的权益，其公开内容通过引用整体地结合于此。

Claims (25)

1.一种电子器件，包括：
衬底；
在所述衬底上的栅电极；
在所述衬底和所述栅电极之间的铁电层；以及
在所述衬底和所述铁电层之间的碳层，所述碳层具有sp2键合结构。
2.根据权利要求1所述的电子器件，其中
所述衬底包括在所述衬底中在与所述栅电极对应的位置处的沟道元件，以及
所述衬底还包括在所述沟道元件的两侧的源电极和漏电极。
3.根据权利要求1所述的电子器件，其中
所述碳层包括包含纳米尺寸的晶体的纳米晶体石墨烯。
4.根据权利要求3所述的电子器件，其中在所述纳米晶体石墨烯中的所述纳米尺寸的晶体具有0.5nm至100nm的尺寸。
5.根据权利要求3所述的电子器件，其中在所述纳米晶体石墨烯中，具有sp2键合结构的碳与全部碳的比率为50％至99％。
6.根据权利要求3所述的电子器件，其中所述纳米晶体石墨烯包含1原子百分比至20原子百分比的氢。
7.根据权利要求1所述的电子器件，还包括：
在所述衬底和所述碳层之间的绝缘层。
8.根据权利要求1所述的电子器件，还包括：
在所述碳层和所述铁电层之间的绝缘层。
9.根据权利要求1所述的电子器件，其中所述栅电极包括导电金属或具有sp2键合结构的碳材料。
10.根据权利要求1所述的电子器件，其中所述铁电层包括包含硅(Si)、铝(Al)、铪(Hf)和锆(Zr)中的至少一种的氧化物。
11.根据权利要求10所述的电子器件，其中所述氧化物还包含掺杂剂。
12.根据权利要求1所述的电子器件，其中所述碳层的厚度在从0.4nm至100nm的范围内。
13.一种制造电子器件的方法，所述方法包括：
制备包括沟道元件的衬底；
在所述沟道元件上沉积碳层，所述碳层具有sp2键合结构；
在所述碳层上沉积铁电层；
在所述铁电层上沉积栅电极；以及
通过退火工艺使所述铁电层结晶。
14.根据权利要求13所述的方法，其中制备所述衬底包括在所述沟道元件的两侧形成源电极和漏电极。
15.根据权利要求13所述的方法，还包括：
在所述衬底和所述碳层之间产生绝缘层。
16.根据权利要求13所述的方法，还包括：
在所述碳层和所述铁电层之间产生绝缘层。
17.根据权利要求13所述的方法，其中沉积所述碳层通过化学气相沉积或原子层沉积执行。
18.根据权利要求13所述的方法，其中所述碳层包括包含纳米尺寸的晶体的纳米晶体石墨烯。
19.根据权利要求13所述的方法，其中沉积所述碳层包括形成所述碳层使得所述碳层的厚度在0.4nm至100nm的范围内。
20.根据权利要求13所述的方法，其中沉积所述铁电层通过化学气相沉积或原子层沉积执行。
21.一种电子器件，包括：
沟道元件；
连接到所述沟道元件的相对端的源电极和漏电极；
在所述沟道元件上的栅电极，所述栅电极与所述源电极、所述漏电极和所述沟道元件间隔开；
在所述沟道元件与所述栅电极之间的铁电层；以及
在所述沟道元件与所述铁电层之间的碳层，
所述碳层配置为限制所述金属或氧中的至少一种从所述铁电层扩散到所述沟道元件。
22.根据权利要求21所述的电子器件，还包括：
在所述沟道元件上的绝缘层，其中
所述绝缘层在所述沟道元件与所述铁电层之间，或者
所述绝缘层在所述栅电极与所述铁电层之间。
23.根据权利要求21所述的电子器件，其中
所述碳层包括包含纳米尺寸的晶体的纳米晶体石墨烯。
24.根据权利要求21所述的电子器件，其中
所述沟道元件是沟道层或者是衬底的突出部分。
25.根据权利要求21所述的电子器件，其中所述铁电层包括包含硅(Si)、铝(Al)、铪(Hf)和锆(Zr)中的至少一种的氧化物。
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