CN110752167A - 芯片转移的方法及其芯片转移系统 - Google Patents

芯片转移的方法及其芯片转移系统 Download PDF

Info

Publication number
CN110752167A
CN110752167A CN201910100014.3A CN201910100014A CN110752167A CN 110752167 A CN110752167 A CN 110752167A CN 201910100014 A CN201910100014 A CN 201910100014A CN 110752167 A CN110752167 A CN 110752167A
Authority
CN
China
Prior art keywords
chip
chips
transparent substrate
target substrate
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910100014.3A
Other languages
English (en)
Other versions
CN110752167B (zh
Inventor
林怡君
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huafang Juliang Semiconductor Technology Co ltd
Original Assignee
Feichuan Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Feichuan Technology Co ltd filed Critical Feichuan Technology Co ltd
Publication of CN110752167A publication Critical patent/CN110752167A/zh
Application granted granted Critical
Publication of CN110752167B publication Critical patent/CN110752167B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H01L2221/68322—Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05551—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/13294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/132 - H01L2224/13291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H01L2224/29007—Layer connector smaller than the underlying bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32111—Disposition the layer connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32237—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81085—Bonding environment being a liquid, e.g. for fluidic self-assembly
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83053—Bonding environment
    • H01L2224/83085—Bonding environment being a liquid, e.g. for fluidic self-assembly
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8336—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/83365—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83868—Infrared [IR] curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83871—Visible light curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83874—Ultraviolet [UV] curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Die Bonding (AREA)
  • Mechanical Engineering (AREA)
  • Led Device Packages (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Wire Bonding (AREA)

Abstract

一种芯片转移的方法及其芯片转移系统。芯片转移的方法包括以下步骤：提供晶圆以生成多个芯片；将多个芯片转移到透明基板的表面，以借由光感应黏着层将多个芯片固定在透明基板的表面上；将透明基板与目标基板对位，其中目标基板具有落点处，至少一芯片的位置对应至落点处的位置；借由放射光束照射透明基板，使光感应黏着层让至少一芯片掉落，借此得以将至少一芯片转移到目标基板的落点处上；以及固定至少一芯片于落点处。

Description

芯片转移的方法及其芯片转移系统
技术领域
本发明关于一种芯片转移的方法及其芯片转移系统，特别是一种利用光感式进行转移的芯片转移的方法及其芯片转移系统。
背景技术
随着科技的进步，电子芯片已经的被大量地使用于各式电子装置上。而于先前技术中已经揭示了几种将电子芯片设置于基板上的方法，例如表面黏着技术(SMT)、晶圆转移(Wafer-to-Wafer Transfer)技术、静电转移(Electrostatic Transfer)技术、弹性印模(Elastomer stamp)微转印(μTP)技术、流体组装(Fluidic Assembly)等技术。
表面黏着技术为芯片需先经逐一封装为SMD(surface mount device)组件后，制作成卷带才完成组件阶段。卷带放入表面贴焊机(SMT)运用真空吸头逐一将SMD打在电路基板上，再经回焊炉固定于基板。但此种方式只能一次转移一个芯片，且能对应的芯片尺寸或电路基板形式有限。晶圆转移技术为将芯片的原生基板与目标基板贴合，再将原生基板剥离后使芯片转移到目标基板上。但此种方式的原生基板与目标基板尺寸必须相同，原生基板与目标基板上芯片设置的间距必须一致，芯片也无法选择性移转。静电转移技术为例用静电方式拾取、移转、放置芯片于目标基板上。但此种静电方式易造成芯片损坏，且移转时为硬碰硬接触，易损伤芯片，也受限于静电极的尺寸。弹性印模微转印技术以具微黏性的PDMS为拾取头(stamp)，微调拾取头的速度及施力，破坏组件的弱结构而达成拾取的动作。移转至目标基板后，利用芯片两面分别与拾取头及目标基板上固着层的附着性差异而达成贴附的动作。但此种方式原生芯片须额外制作，且虽可以一次移转多个芯片，但无法作直接选择要移转的芯片。并且破坏组件时容易造成屑粒的产生。流体组装技术将芯片悬浮于液体中，运用滚筒在基板上的滚动使流体带动芯片，同时可利用上部矩阵状的喷嘴释出流体或气体，促进具悬浮芯片的流体扰动，使芯片进而落入基板上的对应井当中。但此种方式芯片外型须作特殊设计，且流体的控制不确定性高，完成的时间亦难以预测。
因此，有必要发明一种新的芯片转移的方法及其芯片转移系统，以解决先前技术的缺失。
发明内容
本发明的主要目的在于提供一种芯片转移的方法，其具有利用光感式进行转移的效果。
本发明的另一主要目的在于提供一种用于上述方法的芯片转移系统。
为达成上述的目的，本发明的芯片转移的方法包括以下步骤：提供晶圆以生成多个芯片；将多个芯片转移到透明基板的表面，以借由光感应黏着层将多个芯片固定在透明基板的表面上；将透明基板与目标基板对位，其中目标基板具有落点处，至少一芯片的位置对应至落点处的位置；借由放射光束照射透明基板，使光感应黏着层让至少一芯片掉落，借此得以将至少一芯片转移到目标基板的落点处上；以及固定至少一芯片于落点处。
本发明的芯片转移系统适用于转移多个芯片。芯片转移系统包括透明基板、目标基板及光束射出模块。透明基板具有一表面，表面设置光感应黏着层，其中于晶圆生成多个芯片后，多个芯片移转到表面，以借由光感应黏着层固定多个芯片。目标基板具有落点处，其中透明基板与目标基板对位时，至少一芯片的位置对应至落点处的位置。光束射出模块用以射出放射光束，放射光束照射至透明基板，使透明基板上的光感应黏着层让至少一芯片掉落，借此得以将至少一芯片转移于目标基板的落点处上。
附图说明
图1为本发明的芯片转移系统的侧视示意图。
图2A-2C为本发明的芯片转移系统的转移顺序的示意图。
图3为本发明的芯片转移的方法的步骤流程图。
其中附图标记为：
芯片转移系统1
晶圆10
芯片11
透明基板20
表面20a
光感应黏着层21
目标基板30
落点处31
黏着层311
光束射出模块40
放射光束B
具体实施方式
为能让贵审查委员能更了解本发明的技术内容，特举较佳具体实施例说明如下。
以下请先参考图1为本发明的芯片转移系统的侧视示意图及图2A-2C为本发明的芯片转移系统的转移顺序的示意图。
本发明的芯片转移系统1适用于转移多个芯片11，多个芯片11由一晶圆10所制成，由于利用晶圆10生成芯片11的技术已经被本发明所属技术领域中具通常知识者所熟悉，故在此不再赘述其原理。该芯片转移系统1包括透明基板20、目标基板30及光束射出模块40。该透明基板20具有一表面20a，该表面20a设置一光感应黏着层(Photosensitive AdhesiveLayer)21。该光感应黏着层21借由一具黏性的高分子胶体构成，在吸收特定波长范围的能量后会产生相变而失去黏着力或分解气化。于晶圆10生成该多个芯片11后，该多个芯片11借由晶圆转移(Wafer-to-Wafer Transfer)技术以移转到该表面20a上，并借由该光感应黏着层(Photosensitive Adhesive)21固定该多个芯片11，使多个芯片11不易掉落，即如图2A到图2B所示。
目标基板30具有一落点处31，其中该透明基板20与该目标基板30对位时，表面20a上至少有一个芯片11的位置对应至该落点处31的位置。该目标基板30的该落点处31设置一对应井或一黏着层，以方便设置芯片11。于本发明的图1中，落点处31为黏着层311再加上对应井的结构，但本发明并不限于此。
光束射出模块40可射出一放射光束B。放射光束B的波长配合于光感应黏着层21的特性。因此当该放射光束B照射至该透明基板20，会使得该透明基板20上的该光感应黏着层21产生相变或分解。放射光束B可自由设定扫瞄范围，以透过单点对焦或扫描的方式选择性地对单一芯片11或多个芯片11作转置，放射光束B也可弹性调整以对应大小不同尺寸的芯片11，兼顾高效率与选择性的需求。如此一来，就可以让特定的单一芯片11或多个芯片11掉落，借此得以将芯片11转移于该目标基板30的该落点处31上，最后再以黏胶固定芯片11于落点处31。举例来说，芯片11的电极朝上时，可用绝缘胶材经过光(通常为UV，但不以此为限)或热固定。而芯片11的电极朝下时，即覆晶(Flip chip)，可用焊料类，如锡膏、球栅数组封装(Ball Grid Array，BGA)或异方性导电胶(ACF)，再经热或光固着于目标基板30，并使芯片11与目标基板30的电极导通，但本发明并不限定芯片11的固定方式。就如图2C所示，芯片11已经完全转移到目标基板30。
并需注意的是，该目标基板30上不同落点处31的间距为该透明基板20上相邻芯片11的间距的M倍，其中M为正整数，但本发明并不限定M的大小。如此一来，芯片转移系统1可在透明基板20到位后以逐点选择性地将欲转置的芯片11一次巨量而快速地进行转置到目标基板30。透明基板20可再移动至下一区域，持续转置芯片11直到目标基板30上的落点处31都已转置完成芯片11。若有多个目标基板30，则可分区同步或同区依序将多个透明基板20的各芯片11巨量而高速地转置于目标基板30上。例如用于制造LED显示器时，可将多个透明基板20分别乘载的红色、蓝色及绿色的LED芯片，再大量且高速地转置到目标基板30，以制成LED显示器的面板。
接着请参考图3为本发明的芯片转移的方法的步骤流程图。此处需注意的是，以下虽以上述芯片转移系统1为例说明本发明的芯片转移的方法，但本发明的芯片转移的方法并不以使用在上述相同结构的芯片转移系统1为限。
首先进行步骤301：提供一晶圆以生成多个芯片。
首先利用晶圆10制成多个芯片11。
接着进行步骤302：将该多个芯片转移到一透明基板的一表面，以借由一光感应黏着层将该多个芯片固定在该透明基板的该表面上。
接着该多个芯片11借由晶圆转移技术以移转到透明基板20的该表面20a上，并借由透明基板20的该光感应黏着层21固定该多个芯片11，如图2A到2B所示。
再进行步骤303：将该透明基板与一目标基板对位，其中该目标基板具有一落点处，至少一芯片的位置对应至该落点处的位置。
让该透明基板20与该目标基板30对位，使得透明基板20的表面20a上至少有一个芯片11的位置对应至该落点处31的位置。
接着执行步骤304：借由一放射光束照射该透明基板，使该光感应黏着层让该至少一芯片掉落，借此得以将该至少一芯片转移到该目标基板的该落点处上。
当该放射光束B照射至该透明基板20，会使得该透明基板20上的该光感应黏着层21产生相变或分解。如此一来，就可以让芯片11掉落，借此得以将芯片11转移于该目标基板30的该落点处31上。
最后执行步骤305：固定该芯片于该落点处。
最后以黏胶固定芯片11于落点处31，但本发明并不限定黏胶的材质或固定的方法。
此处需注意的是，本发明的芯片转移的方法并不以上述的步骤次序为限，只要能达成本发明的目的，上述的步骤次序亦可加以改变。
如此一来，借由本发明的芯片转移系统1及芯片转移的方法可以完全在室温下制造，且目标基板30无尺寸、材料的限制。本发明的芯片转移的方法用于群组式的巨量移转时，可提高效率，缩短工艺时间。用于单点或小区域的高选择性移转时也可用于修复不良区域，提高转置良率。
需注意的是，上述实施方式仅例示本发明的较佳实施例，为避免赘述，并未详加记载所有可能的变化组合。然而，本领域的通常知识者应可理解，上述各模块或组件未必皆为必要。且为实施本发明，亦可能包含其他较细节的现有模块或组件。各模块或组件皆可能视需求加以省略或修改，且任两模块间未必不存在其他模块或组件。只要不脱离本发明基本架构者，皆应为本专利所主张之权利范围，而应以专利申请范围为准。

Claims (8)

1.一种芯片转移的方法，其特征在于，包括以下步骤：
提供一晶圆以生成多个芯片；
将该多个芯片转移到一透明基板的一表面，以借由一光感应黏着层将该多个芯片固定在该透明基板的该表面上；
将该透明基板与一目标基板对位，其中该目标基板具有一落点处，至少一芯片的位置对应至该落点处的位置；
借由一放射光束照射该透明基板，使该光感应黏着层让该至少一芯片掉落，借此得以将该至少一芯片转移到该目标基板的该落点处上；以及
固定该至少一芯片于该落点处。
2.如权利要求1所述的芯片转移的方法，其特征在于，更包括以下步骤：借由一具黏性的高分子胶体构成该光感应黏着层。
3.如权利要求1所述的芯片转移的方法，其特征在于，更包括以下步骤：设置一对应井或一黏着层于该目标基板的该落点处。
4.如权利要求1所述的芯片转移的方法，其特征在于，该目标基板上不同落点处的间距为该透明基板上相邻芯片的间距的M倍，其中M为正整数。
5.一种芯片转移系统，适用于转移多个芯片，其特征在于，该芯片转移系统包括：
一透明基板，具有一表面，该表面设置一光感应黏着层，其中于一晶圆生成该多个芯片后，该多个芯片移转到该表面，以借由该光感应黏着层固定该多个芯片；
一目标基板，具有一落点处，其中该透明基板与该目标基板对位时，至少一芯片的位置对应至该落点处的位置；以及
一光束射出模块，用以射出一放射光束，该放射光束照射至该透明基板，使该透明基板上的该光感应黏着层让该至少一芯片掉落，借此得以将该至少一芯片转移于该目标基板的该落点处上。
6.如权利要求5所述的芯片转移系统，其特征在于，该光感应黏着层借由一具黏性的高分子胶体构成。
7.如权利要求5所述的芯片转移系统，其特征在于，该目标基板的该落点处设置一对应井或一黏着层。
8.如权利要求5所述的芯片转移系统，其特征在于，该目标基板上不同落点处的间距为该透明基板上相邻芯片的间距的M倍，其中M为正整数。
CN201910100014.3A 2018-07-23 2019-01-31 芯片转移的方法及其芯片转移系统 Active CN110752167B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW107125365A TW202008558A (zh) 2018-07-23 2018-07-23 晶片轉移之方法及其晶片轉移系統
TW107125365 2018-07-23

Publications (2)

Publication Number Publication Date
CN110752167A true CN110752167A (zh) 2020-02-04
CN110752167B CN110752167B (zh) 2022-11-08

Family

ID=69161984

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201910100014.3A Active CN110752167B (zh) 2018-07-23 2019-01-31 芯片转移的方法及其芯片转移系统
CN201910099977.6A Pending CN110753487A (zh) 2018-07-23 2019-01-31 芯片转移的方法及其芯片转移系统

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201910099977.6A Pending CN110753487A (zh) 2018-07-23 2019-01-31 芯片转移的方法及其芯片转移系统

Country Status (3)

Country Link
US (2) US20200023479A1 (zh)
CN (2) CN110752167B (zh)
TW (1) TW202008558A (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111564393A (zh) * 2020-05-21 2020-08-21 厦门乾照半导体科技有限公司 一种led芯片的转移方法
CN112967972A (zh) * 2020-06-03 2021-06-15 重庆康佳光电技术研究院有限公司 一种微型发光二极管巨量转移装置及方法
CN114074429A (zh) * 2020-08-12 2022-02-22 重庆康佳光电技术研究院有限公司 弱化结构的制造方法及制造系统
CN115172192A (zh) * 2022-09-09 2022-10-11 之江实验室 一种多芯粒晶圆级集成的混合键合方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111933775B (zh) * 2020-07-24 2022-09-23 深圳市隆利科技股份有限公司 界面限位组装制备led显示器的方法
TWI744181B (zh) * 2021-01-28 2021-10-21 台灣愛司帝科技股份有限公司 晶片移轉模組以及晶片移轉與固晶裝置與方法
TWI811625B (zh) * 2021-01-29 2023-08-11 台灣愛司帝科技股份有限公司 晶片移轉方法、晶片移轉裝置以及影像顯示器
CN113314453A (zh) * 2021-05-20 2021-08-27 湘潭大学 一种Micro-LED的转移方法和装置
TWI766699B (zh) * 2021-05-25 2022-06-01 台灣愛司帝科技股份有限公司 轉移電子元件之方法
CN113594308A (zh) * 2021-08-02 2021-11-02 錼创显示科技股份有限公司 巨量转移设备
TWI787933B (zh) * 2021-08-02 2022-12-21 錼創顯示科技股份有限公司 巨量轉移設備
CN114122203B (zh) * 2021-11-19 2023-03-14 东莞市中麒光电技术有限公司 一种利用液体表面张力实现芯片转移的方法

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001177294A (ja) * 1999-12-20 2001-06-29 Nec Ibaraki Ltd チップ部品搭載装置および方法
US20100071206A1 (en) * 2008-09-24 2010-03-25 Kerr Roger S Low cost die release wafer
US20100109024A1 (en) * 2008-11-04 2010-05-06 Canon Kabushiki Kaisha Transfer method of functional region, led array, led printer head, and led printer
CN105493297A (zh) * 2015-05-21 2016-04-13 歌尔声学股份有限公司 微发光二极管的转移方法、制造方法、装置和电子设备
WO2017107097A1 (en) * 2015-12-23 2017-06-29 Goertek.Inc Micro-led transfer method and manufacturing method
WO2017124332A1 (en) * 2016-01-20 2017-07-27 Goertek.Inc Micro-led transfer method and manufacturing method
US20170263811A1 (en) * 2015-08-18 2017-09-14 Goertek.Inc Repairing method, manufacturing method, device and electronic apparatus of micro-led
US20170358623A1 (en) * 2016-06-10 2017-12-14 Manivannan Thothadri Maskless parallel pick-and-place transfer of micro-devices
US20180053751A1 (en) * 2015-10-20 2018-02-22 Goertek, Inc. Transferring method, manufacturing method, device and electronic apparatus of micro-led
CN107889540A (zh) * 2015-05-21 2018-04-06 歌尔股份有限公司 微发光二极管的转移方法、制造方法、装置和电子设备
WO2018124664A1 (ko) * 2016-12-26 2018-07-05 주식회사 엘지화학 마이크로 전기 소자의 전사 방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU1575329A1 (ru) * 1988-05-17 1990-06-30 Особое конструкторско-технологическое бюро "Орион" при Новочеркасском политехническом институте им.Серго Орджоникидзе Резонатор дл изготовлени катодных полуэлементов тепловых источников тока
JP5007127B2 (ja) * 2004-12-28 2012-08-22 光正 小柳 自己組織化機能を用いた集積回路装置の製造方法及び製造装置
WO2007105535A1 (ja) * 2006-03-14 2007-09-20 Matsushita Electric Industrial Co., Ltd. 電子部品実装構造体およびその製造方法
JP2008103493A (ja) * 2006-10-18 2008-05-01 Lintec Corp チップのピックアップ方法及びピックアップ装置
TWI366677B (en) * 2007-12-28 2012-06-21 Ind Tech Res Inst Electrowetting display devices and fabrication methods thereof
KR20100087932A (ko) * 2009-01-29 2010-08-06 삼성전기주식회사 자기 조립 단분자막을 이용한 다이 어태치 방법 및 자기 조립 단분자막을 이용하여 다이가 어태치된 패키지 기판
JP2011138902A (ja) * 2009-12-28 2011-07-14 Tokyo Electron Ltd 実装方法及び実装装置
CN103165541B (zh) * 2011-12-12 2016-05-04 中芯国际集成电路制造(北京)有限公司 芯片与晶片的接合方法以及三维集成半导体器件

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001177294A (ja) * 1999-12-20 2001-06-29 Nec Ibaraki Ltd チップ部品搭載装置および方法
US20100071206A1 (en) * 2008-09-24 2010-03-25 Kerr Roger S Low cost die release wafer
US20100109024A1 (en) * 2008-11-04 2010-05-06 Canon Kabushiki Kaisha Transfer method of functional region, led array, led printer head, and led printer
CN105493297A (zh) * 2015-05-21 2016-04-13 歌尔声学股份有限公司 微发光二极管的转移方法、制造方法、装置和电子设备
CN107889540A (zh) * 2015-05-21 2018-04-06 歌尔股份有限公司 微发光二极管的转移方法、制造方法、装置和电子设备
US20170263811A1 (en) * 2015-08-18 2017-09-14 Goertek.Inc Repairing method, manufacturing method, device and electronic apparatus of micro-led
US20180053751A1 (en) * 2015-10-20 2018-02-22 Goertek, Inc. Transferring method, manufacturing method, device and electronic apparatus of micro-led
WO2017107097A1 (en) * 2015-12-23 2017-06-29 Goertek.Inc Micro-led transfer method and manufacturing method
WO2017124332A1 (en) * 2016-01-20 2017-07-27 Goertek.Inc Micro-led transfer method and manufacturing method
US20170358623A1 (en) * 2016-06-10 2017-12-14 Manivannan Thothadri Maskless parallel pick-and-place transfer of micro-devices
WO2018124664A1 (ko) * 2016-12-26 2018-07-05 주식회사 엘지화학 마이크로 전기 소자의 전사 방법

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111564393A (zh) * 2020-05-21 2020-08-21 厦门乾照半导体科技有限公司 一种led芯片的转移方法
CN111564393B (zh) * 2020-05-21 2022-10-18 厦门乾照半导体科技有限公司 一种led芯片的转移方法
CN112967972A (zh) * 2020-06-03 2021-06-15 重庆康佳光电技术研究院有限公司 一种微型发光二极管巨量转移装置及方法
CN114074429A (zh) * 2020-08-12 2022-02-22 重庆康佳光电技术研究院有限公司 弱化结构的制造方法及制造系统
CN114074429B (zh) * 2020-08-12 2024-01-12 重庆康佳光电技术研究院有限公司 弱化结构的制造方法及制造系统
CN115172192A (zh) * 2022-09-09 2022-10-11 之江实验室 一种多芯粒晶圆级集成的混合键合方法

Also Published As

Publication number Publication date
US20200023479A1 (en) 2020-01-23
CN110752167B (zh) 2022-11-08
TW202008558A (zh) 2020-02-16
CN110753487A (zh) 2020-02-04
US20200027757A1 (en) 2020-01-23

Similar Documents

Publication Publication Date Title
CN110752167B (zh) 芯片转移的方法及其芯片转移系统
JP6533838B2 (ja) マイクロ発光ダイオードの搬送方法、製造方法、装置及び電子機器
CN107251237B (zh) 微发光二极管的修复方法、制造方法、装置和电子设备
CN112908897B (zh) 基于无掩膜光刻的MicroLED芯片粘附式阵列转移方法
CN110634840B (zh) 检测基板及其制备方法、检测装置和检测方法
CN108538877B (zh) Micro LED显示面板的制作方法
US9049797B2 (en) Electrically bonded arrays of transfer printed active components
US20230215851A1 (en) Driving backplane, transfer method for light-emitting diode chip, display apparatus
TW200424985A (en) Circuit board, mounting structure of ball grid array, electro-optic device and electronic apparatus
CN111199907A (zh) 微发光器件的转移方法及转移设备
CN109461752A (zh) 具微半导体结构的目标基板
KR102218988B1 (ko) Led칩 전사용 감광성 전사 수지, 그 감광성 전사 수지를 이용한 led칩 전사 방법 및 이를 이용한 디스플레이 장치의 제조 방법
CN111902952A (zh) 发光二极管的巨量转移方法、以及显示背板组件
JP2019140400A (ja) マイクロ発光ダイオードの事前排除方法、製造方法、装置及び電子機器
JP2020145243A (ja) チップ転写板ならびにチップ転写方法、画像表示装置の製造方法および半導体装置の製造方法
CN111133498A (zh) 一种显示面板及其制作方法、显示装置
CN114220828A (zh) Micro-LED芯片的巨量转移方法和巨量转移载体
TWM618106U (zh) 晶片轉移系統
CN111477651A (zh) 一种基于液晶光闸掩膜的巨量转移方法及转移装置
US10524359B2 (en) Method and system for manufacturing a workpiece using a polymer layer
US20230073010A1 (en) Method for mass transfer, led display device, and display apparatus
US11955453B2 (en) Electronic device
KR102626606B1 (ko) 디스플레이 장치의 제조 방법 및 디스플레이 장치
CN117334619A (zh) Micro LED暂态转移基板及Micro LED的转移方法
TW202337300A (zh) 修補設備

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20220104

Address after: Floor 3, building 19, building 8, No. 498, GuoShouJing Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai

Applicant after: Shanghai Huafang Juliang Semiconductor Technology Co.,Ltd.

Address before: 3 / F, 13 / F, No.141, Section 1, Keelung Road, Xinyi District, Taipei, Taiwan, China

Applicant before: Feichuan Technology Co.,Ltd.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant