CN110730988B - 半导体模块 - Google Patents

半导体模块 Download PDF

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CN110730988B
CN110730988B CN201780091511.0A CN201780091511A CN110730988B CN 110730988 B CN110730988 B CN 110730988B CN 201780091511 A CN201780091511 A CN 201780091511A CN 110730988 B CN110730988 B CN 110730988B
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processing unit
interposer
semiconductor module
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CN110730988A (zh
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梶谷一彦
安达隆郎
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Ultramemory Inc
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Abstract

本发明提供一种半导体模块，通过能够扩大存储带宽并且减少耗电从而能够提高数据传输效率。半导体模块(1)具有中介层(10)和处理部(20)，所述处理部(20)载置在所述中介层(10)并与所述中介层(10)电连接，所述处理部具有在沿所述中介层(10)的板面的第一方向(F1)上排列设置的多个处理部主体(21)，所述处理部主体(21)具有多个子部(22)，所述子部(22)具有一个运算部(23)和一个存储部(24)，所述运算部(23)包含至少一个核(25)，所述存储部(24)由层叠型RAM模块构成，并排列设置在运算部(23)的第一方向(F1)上，多个所述子部(22)排列设置在与第一方向(F1)交叉的第二方向(F2)上。

Description

半导体模块
技术领域
本发明涉及半导体模块。
背景技术
以往，作为存储装置，已知有DRAM(DynamicRandom Access Memory：动态随机存取存储器)等易失性存储器。对于DRAM，要求对应于运算装置(以下称为MPU)的高性能化、数据量的增大能够承受的大容量化。因此，一直在追求通过存储器(存储单元阵列、存储芯片)的微细化以及单元的平面增设而得到的大容量化。另一方面，因为由微细化导致的对噪声的脆弱性、晶片(die)面积的增加等，这种大容量化达到了极限。
因此，最近提出了层叠多个平面的存储器来进行三维化(3D化)从而实现大容量化的技术(例如，参照专利文献1～4)。
现有技术文献
专利文献
专利文献1：日本特表2016-502287号公报；
专利文献2：日本特表2015-507372号公报；
专利文献3：日本特表2015-502664号公报；
专利文献4：日本特表2011-512598号公报。
发明内容
发明要解决的问题
然而，因为MPU的高性能化、数据量的增大，在要求大容量化的同时也要求提高MPU与DRAM之间的通信速度。通过提高存储带宽(存储频带宽度)，能够提高MPU与DRAM之间的通信速度，但因为通信速度的提高，数据传输功率(耗电)也增大。例如，如果将在DRAM的读出放大器与处理器的处理元件(processing element)之间传输1比特的数据所需要的能量设为1pJ，则在128TB/s的存储带宽下，数据传输功率达到1024W。
因此，如果通过能够扩大存储带宽并且减少耗电从而能够提高数据传输效率，则非常有用。
本发明的目的在于提供一种半导体模块，通过能够扩大存储带宽并且减少耗电，从而能够提高数据传输效率。
用于解决问题的方案
本发明涉及一种半导体模块，其特征在于，具有：中介层；以及处理部，所述处理部载置在所述中介层并与所述中介层电连接，所述处理部具有在沿所述中介层的板面的第一方向上排列设置的多个处理部主体，所述处理部主体具有多个子部，所述子部具有一个运算部和一个存储部，所述运算部包含至少一个核，所述存储部排列设置在运算部的第一方向上，并由层叠型RAM模块构成，多个所述子部排列设置在与第一方向交叉的第二方向上。
此外，优选所述处理部还具有路由器部，所述路由器部排列设置在所述处理部主体的第二方向上，对多个所述处理部主体之间的数据通信进行中继。
此外，优选所述中介层具有连接多个所述路由器部的通信线。
此外，优选在所述运算部的与排列设置的所述存储部邻接的一端部具有第一接口部，在所述存储部的与排列设置的所述运算部邻接的一端部具有第二接口部。
发明效果
根据本发明，能够提供一种半导体模块，通过能够扩大存储带宽并且减少耗电，从而能够提高数据传输效率。
附图说明
图1为表示本发明的一实施方式的半导体模块的概略俯视图。
图2为图1的A-A线剖视图。
图3为表示一实施方式的半导体模块的第一处理部的概略俯视图。
图4为表示一实施方式的半导体模块的第一处理部、第二处理部以及路由器部的概略俯视图。
图5为表示一实施方式的半导体模块的信号线的长度的概略图。
具体实施方式
以下，参照附图来对本发明的一实施方式的半导体模块进行说明。
本实施方式的半导体模块1是例如在中介层(interposer)上配置了运算装置(以下称为MPU)和层叠型DRAM的SIP(system in a package：系统级封装)。半导体模块1配置在另一中介层或封装基板上，使用微凸块(micro bump)进行电连接。半导体模块1是从另一中介层或封装基板获得电源并且能够在与另一中介层或封装基板之间收发数据的装置。
如图1和图2所示，该半导体模块1具有中介层10和处理部20。
中介层10形成为板状，使用凸块M1将该中介层的一侧的表面与另一中介层或封装基板进行电连接。在中介层10的另一侧的表面具有将后述的多个路由器部30之间进行连接的通信线12。通信线12在沿中介层10的板面的第一方向F1上配置。此外，中介层10具有对后述的运算部23和后述的存储部24进行连接的布线部26。对于布线部26的详情，在后面叙述。
处理部20载置在中介层10，并且与中介层10电连接。如图1～图3所示，处理部20具有多个处理部主体21和路由器部30。
处理部主体21形成为正视时的矩形。处理部主体21具有：运算部组C，其排列设置有多个后述的运算部23；以及存储部组D，其排列设置有多个后述的存储部24。
运算部组C形成为正视时的矩形，并构成为沿着中介层10的板面在与第一方向F1交叉的第二方向F2上排列设置多个后述的运算部23。即，运算部组C形成为正视时在第二方向F2上较长的长方形。
存储部组D形成为正视时的矩形，并构成为在第二方向F2上排列设置多个后述的存储部24。即，存储部组D形成为正视时在第二方向F2上较长的长方形。存储部组D在第一方向F1上与运算部组C排列设置。在此，如图3和图4所示，构成存储部组D的存储部24与构成运算部组C的运算部23在第一方向F1上一一对应地配置。一一对应的运算部23和存储部24的组合构成一个子部22。
以上的处理部主体21在本实施方式中设置16个(多个)。如图1所示，16个处理部主体21是将沿第一方向F1配置的8个处理部主体21设为一列，并在第二方向F2上配置2行而形成的。此外，处理部主体21是将在第一方向上排列设置的两个作为一组来配置的。一组处理部主体21沿第一方向F1按照存储部组D、运算部组C、运算部组C以及存储部组D的顺序配置。
如图3和图4所示，子部22形成为正视时的矩形。在本实施方式中，子部22在一个处理部主体21中在第二方向F2上配置64个(多个)。子部22具有一个运算部和一个存储部。
运算部23形成为正视时的矩形，并配置在中介层10上。运算部23使用ACF(各向异性导电膜)、混合键合(Hybrid Bonding)或微凸块等与中介层10连接。运算部23包含至少一个核25。
在本实施方式中，如图4所示，运算部23包含四个核25，各个核25沿第一方向F1排列设置。运算部23构成为能够与邻接的子部22的运算部23进行通信。此外，运算部23与另一子部22的运算部23在第二方向F2上邻接地配置。在本实施方式中，运算部23构成为四个核25各自能够与其他核25进行通信。此外，如图5所示，在运算部23的与后述的排列设置的存储部24邻接的一端部配置第一接口部27。第一接口部27构成为能够与后述的存储部24进行数据通信。如图5所示，运算部23例如形成为在第一方向F1上的长度L1为1mm。
存储部24由层叠型RAM模块构成，形成为正视时的矩形。在本实施方式中，存储部24由层叠型DRAM模块构成。存储部24配置在中介层10上。存储部24使用ACF(各向异性导电膜)、混合键合(Hybrid Bonding)或微凸块等与中介层10连接。存储部24排列设置在运算部23的第一方向F1(沿图3的纸面，左右侧中的一方)上。此外，存储部24与另一子部22的存储部24在第二方向F2上邻接地配置。如图5所示，在存储部24的与排列设置的运算部23邻接的一端部配置第二接口部28。第二接口部28构成为能够与运算部23进行数据通信。如图5所示，存储部24形成为例如第一方向F1上的长度L4为1mm，整体的厚度L3为0.1mm，且为八层。存储部24的容量为各层64Mb，在整体上由64MB构成。一个子部22具有由布线部26、第一接口部27以及第二接口部28构成的一信道量的接口。
根据以上的子部22，处理部主体21的整体由256个核25(256PE(ProcessingElement：处理元件)/核)构成，成为64信道结构(64MB/信道)。此外，各个信道以宽度256b、通信速度4Gbps来构成，由此成为128GB/s的存储带宽，作为64信道整体，以8TB/s的存储带宽来构成。此外，处理部主体21构成为存储部24的容量为4GB。模块整体由16个处理部主体21构成，因此模块整体以4096个核25、1024信道、128TB/s的存储带宽以及存储部24的容量为64GB来构成。
此外，如图3所示，在多个子部22中，运算部23和存储部24各自在第一方向F1上按照相同的顺序配置。即，多个子部22的运算部23沿第二方向F2配置，并且多个子部22的存储部24沿第二方向F2配置。此外，如图3所示，一组处理部主体21以运算部23在第一方向F1上邻接的方式配置。由此，如图3所示，一组处理部主体21在第一方向F1上按照存储部组D、运算部组C、运算部组C以及存储部组D的顺序配置。
路由器部30对多个处理部主体21之间的数据通信进行中继。路由器部30通过中介层10的通信线12与其他路由器部30连接。路由器部30排列设置在处理部主体21的第二方向F2上。具体而言，路由器部30排列设置在处理部主体21的运算部23的第二方向F2。在本实施方式中，如图4所示，路由器部30按每一组处理部主体21来设置一个，该路由器部30配置于在第二方向F2上排列的一组处理部主体21之间。路由器部30能够进行处理部主体21的数据通信，由此将运算部23构成为一个运算处理装置。
接下来，对布线部26进行说明。
布线部26为在中介层10上构成的布线，在中介层10上层状地配置。布线部26在第一方向F1上对子部22的一个运算部23的一端部和一个存储部24的一端部进行电连接。此外，布线部26在第二方向F2上与排列设置的子部22各自的位置对应地配置了多个。在本实施方式中，布线部26由两个2μm间距的铜焊盘(未图示)和1μm间距的铜布线或铝布线(未图示)构成。铜焊盘在一个子部22中分别与一个运算部23的一个端部和一个存储部24的一个端部连接，铜布线或铝布线的两端部分别连接于两个铜焊盘。铜布线或铝布线在第一方向F1上以例如0.2mm的长度L2来形成。
以上的半导体模块1如下进行工作。
如图5所示，在一个子部22中，运算部23和存储部24通过布线部26以128GB/s的存储带宽来连接。在一个子部22中，从布线部26的第一方向F1的一端到配置于最远位置的核25的距离L1为1mm。此外，布线部26的沿第一方向F1的长度L2为0.2mm。此外，存储部24的厚度方向的最大长度L3为0.1mm。而且，从第二接口部28起沿第一方向F1到最远位置的存储块的距离L4为1mm。因此，在一个子部22中，最大布线长度为2.3mm。
如果在图1所示的半导体模块1中，将峰时的存储带宽设为128TB/s，将经由最大布线长度为2.3mm的布线在DRAM的读出放大器与处理器的处理单元之间传输1比特的数据所需的能量设为0.1pJ/b，则一组处理部主体21的峰时的数据传输功率为6.55W。即，半导体模块1的峰时的数据传输功率为105W。
根据如上所述的一实施方式的半导体模块1，获得以下的效果。
(1)将半导体模块1构成为包含中介层10和处理部20，所述处理部20具有在沿中介层10的板面的第一方向F1上排列设置的多个处理部主体21，所述处理部20载置在中介层10并与中介层10电连接。此外，将处理部主体21构成为包含多个子部22，所述子部22由一个运算部23和一个存储部24，所述运算部23包含至少一个核25，所述存储部24由层叠型RAM模块构成，并排列设置在运算部23的第一方向F1上。而且，将多个子部22排列设置在与第一方向F1交叉的第二方向F2上。由此，能够将运算部23的核25与存储部24靠近地配置，因而能够缩短两者的连接距离。由此，能够扩大存储带宽，削减数据通信所需的功率，因而能够提高数据传输效率。
(2)将处理部20构成为还包含路由器部30，所述路由器部30排列设置在处理部主体21的第二方向F2上，并对多个处理部主体21之间的数据通信进行中继。由此，在处理部主体21彼此之间能够进行数据通信，因而能够提高使用了多个子部22的运算效率。
(3)将中介层10构成为包含连接多个路由器部30的通信线12。在中介层10形成了通信线12，因此，无需另外设置布线就能够将路由器部30彼此进行连接，能够将两者容易地连接。
(4)将运算部23构成为在该运算部的与排列设置的存储部24邻接的一端部包含第一接口部27，将存储部24构成为在该存储部的与排列设置的运算部23邻接的一端部包含第二接口部28。因为将第一接口部27和第二接口部28靠近地配置，因而能够进一步缩短连接运算部23和存储部24的信号线的长度。
以上，对本发明的半导体模块的优选的一实施方式进行了说明，但本发明不限于上述实施方式，能够适当变更。
例如，在上述实施方式中，能够如以下表1那样形成存储部24的层叠方向电源连接端子与存储部24的层叠方向信号连接端子的组合。
[表1]
RAM部层叠方向电源端子 RAM部层叠方向信号线
1 TSV+Hybrid Bonding TSV+Hybrid Bonding
2 ACF ACF
3 无凸块TSV TSV+Hybrid Bonding
4 无凸块TSV ACF
此外，在上述实施方式中，由以在第一方向F1上为8行、在第二方向F2上为两列的方式共计16个的处理部主体21构成了处理部20的结构，但第一方向F1和第二方向F2上的数量不限于此。在第一方向F1上配置多个处理部主体21，并在第二方向F2上配置一个处理部主体21的情况下，路由器部30在每一组处理部主体21，与运算部23的列邻接地配置。此外，在第二方向F2上配置三个以上处理部主体21的情况下，路由器部30可以在第二方向F2上在各个处理部主体21之间与两个运算部组C邻接地配置。此外，在第一方向F1上，不配置一组而是配置单个处理部主体21的情况下，路由器部30与单个处理部主体21的运算部组C邻接地配置。此外，处理部主体21内的运算部23与路由器部30可以通过NoC(NetworkonChip：片上网络)进行连接。路由器部30的配置位置可以酌情变更，也可以配置多个。
此外，在上述实施方式中，运算部23、存储部24以及布线部26的规模、信道数量、通信速度、核25的数量以及层叠数量等为一个例子，不限于此。
此外，在上述实施方式中，第二方向F2设为相对于第一方向F1正交的方向，但不限于此。即，第二方向F2可以为沿中介层10的板面相对于第一方向F1大致正交的方向，也可以为相对于第一方向F1倾斜的方向。
此外，在上述实施方式中，使构成子部22的一个运算部23与一个存储部24接触地配置，但不限于此。一个运算部23与一个存储部24也可以空开规定的间隔来配置。此外，在第一方向F1上，子部22可以接触地配置，也可以空开规定的间隔来配置。
此外，运算装置不限定于MPU，可以广泛应用于所有逻辑芯片，存储器不限定于DRAM，可以广泛应用于包含非易失性RAM(例如MRAM、ReRAM、FeRAM等)的所有RAM(RandomAccess Memory：随机存取存储器)。
附图标记说明
1：半导体模块
10：中介层
20：处理部
21：处理部主体
22：子部
23：运算部
24：存储部
25：核
27：第一接口部
28：第二接口部
F1：第一方向
F2：第二方向

Claims (4)

1.一种半导体模块，其特征在于，具有：
中介层；以及
处理部，其载置在所述中介层并与所述中介层进行电连接，所述处理部具有在沿所述中介层的板面的第一方向上排列设置的多个处理部主体，
所述处理部主体具有多个子部，所述子部具有一个运算部和一个存储部，所述运算部包含至少一个核，所述存储部由层叠型RAM模块构成并排列设置在所述运算部的第一方向上，
多个所述子部排列设置在与第一方向交叉的第二方向上，
所述处理部主体是将在所述第一方向上排列设置的两个作为一组来配置的，一组处理部主体沿所述第一方向按照所述存储部、所述运算部、所述运算部以及所述存储部的顺序配置。
2.根据权利要求1所述的半导体模块，其特征在于，
所述处理部还具有路由器部，所述路由器部排列设置在所述第一方向上，对多个所述处理部主体之间的数据通信进行中继，
所述路由器部按每一组处理部主体来设置一个。
3.根据权利要求2所述的半导体模块，其特征在于，
所述中介层具有连接多个所述路由器部的通信线。
4.根据权利要求1至3中任一项所述的半导体模块，其特征在于，
在所述运算部的与排列设置的所述存储部邻接的一端部具有第一接口部，
在所述存储部的与排列设置的所述运算部邻接的一端部具有第二接口部。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1311898A (zh) * 1998-06-02 2001-09-05 薄膜电子有限公司 可调节的集成数据处理设备
CN1734436A (zh) * 2004-08-10 2006-02-15 松下电器产业株式会社 多重处理器
JP2007206849A (ja) * 2006-01-31 2007-08-16 Renesas Technology Corp 並列演算処理装置
JP2015535101A (ja) * 2012-10-11 2015-12-07 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ 高信頼性メモリコントローラ

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2561261B2 (ja) * 1987-02-18 1996-12-04 株式会社日立製作所 バッファ記憶アクセス方法
JP2006127460A (ja) * 2004-06-09 2006-05-18 Renesas Technology Corp 半導体装置、半導体信号処理装置、およびクロスバースイッチ
JP4989899B2 (ja) * 2006-01-27 2012-08-01 ルネサスエレクトロニクス株式会社 半導体演算処理装置
JP5003097B2 (ja) * 2006-10-25 2012-08-15 ソニー株式会社 半導体チップ
US9229887B2 (en) * 2008-02-19 2016-01-05 Micron Technology, Inc. Memory device with network on chip methods, apparatus, and systems
JP2010039625A (ja) * 2008-08-01 2010-02-18 Renesas Technology Corp 並列演算装置
US8493089B2 (en) * 2011-04-06 2013-07-23 International Business Machines Corporation Programmable logic circuit using three-dimensional stacking techniques
US8704364B2 (en) * 2012-02-08 2014-04-22 Xilinx, Inc. Reducing stress in multi-die integrated circuit structures
CN104471708B (zh) * 2012-02-08 2017-05-24 吉林克斯公司 具有多个插入件的堆叠裸片组件
US8704384B2 (en) * 2012-02-17 2014-04-22 Xilinx, Inc. Stacked die assembly
US9024657B2 (en) * 2012-10-11 2015-05-05 Easic Corporation Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1311898A (zh) * 1998-06-02 2001-09-05 薄膜电子有限公司 可调节的集成数据处理设备
CN1734436A (zh) * 2004-08-10 2006-02-15 松下电器产业株式会社 多重处理器
JP2007206849A (ja) * 2006-01-31 2007-08-16 Renesas Technology Corp 並列演算処理装置
JP2015535101A (ja) * 2012-10-11 2015-12-07 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ 高信頼性メモリコントローラ

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