CN110716359A - 阵列基板及其制造方法与对准精度检测方法 - Google Patents

阵列基板及其制造方法与对准精度检测方法 Download PDF

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CN110716359A
CN110716359A CN201910971862.1A CN201910971862A CN110716359A CN 110716359 A CN110716359 A CN 110716359A CN 201910971862 A CN201910971862 A CN 201910971862A CN 110716359 A CN110716359 A CN 110716359A
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color resistance
substrate
display area
resistance unit
array substrate
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游景文
黄俊灵
黄费慧
江华
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US16/759,357 priority patent/US11320708B2/en
Priority to PCT/CN2019/121906 priority patent/WO2021072930A1/zh
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Abstract

本揭示公开一种阵列基板及其制造方法与对准精度检测方法，其将一虚拟色阻单元设置于一阵列基板的显示区的周边上，且将所述虚拟色阻单元设计成其一侧边或中心点与邻近信号线相距一预设距离。因此，仅需测量所述虚拟色阻单元的所述侧边或中心点与邻近信号线的距离，并比较所测量到的距离与所述预设距离，即可推估所述显示区内数个色阻单元的对准精度，而无需在所述阵列基板的非显示区内设置数个检测单元，从而能进一步减少非显示区的面积，以实现超窄边框的显示面板设计。

Description

阵列基板及其制造方法与对准精度检测方法
技术领域
本揭示涉及薄膜晶体管液晶显示器(thin-film transistor liquid-crystaldisplay，TFT-LCD)技术领域，特别是涉及一种COA(Color Filter On Array)阵列基板及其制造方法与对准精度检测方法。
背景技术
在现有技术中，为了检测COA阵列基板中色阻层的对准精度，一般会在COA阵列基板的非显示区设置数个检测单元来检测色阻层中各色阻单元的位置是否与预设位置相符。现今窄边框的液晶显示面板因具有高的屏占比而受到用户青睐，因此如何实现超窄边框设计成为企业研发的重点。然而，随着科技的发展，COA阵列基板在非显示区的走线设计愈来愈复杂，因此若仍欲在COA阵列基板的非显示区设置额外的检测单元，将会使得一显示面板的边框窄化受到限制。
请参阅图1及图2。图1是现有技术中设有检测单元20的COA阵列基板10的示意图。图2是现有技术中检测单元20的示意图。在现有技术中，一般会在COA阵列基板10的非显示区14设置数个检测单元20，用以检测显示区12内一色阻层(未图示)的对准精度。典型的检测单元20包含一金属外框22及一设置在金属外框22内的色阻块24。所述色阻块24是与所述色阻层同时制成。所述金属外框22通常与栅极同时制成。通过测量色阻块24的每一侧边及与其邻近且平行的金属外框22的侧边的距离，并比较所测量到的距离与原设计的距离，来推估所述色阻层的对准精度。然而，在非显示区14设置额外的检测单元20，将会使得非显示区14的窄化受到限制。因此，有需要研发一种新的阵列基板及其制造方法与对准精度检测方法来解决上述技术问题。
发明内容
为了解决上述技术问题，本揭示公开一种阵列基板的制造方法，其包含：提供一基板，其中所述基板包含一显示区及围绕所述显示区的一非显示区；形成数个薄膜晶体管及数个信号线于该基板的显示区上，其中每一薄膜晶体管包含一栅电极层、一绝缘层、一有源层及一源漏极层，所述数个信号线与所述数个薄膜晶体管的栅电极层以同材料同时制成且互相电连接；以及形成数个色阻单元于所述显示区内的所述数个薄膜晶体管及所述基板上，并同时以与所述数个色阻单元相同的材料形成一虚拟色阻单元于所述基板的显示区的周边上，其中所述虚拟色阻单元的一侧边或一中心点设计成与所述数个信号线中的一者相距一预设距离。
本揭示还公开一种通过上述方法制造的阵列基板，其包含一基板、数个薄膜晶体管、数个信号线、数个色阻单元及一虚拟色阻单元。所述基板包含一显示区及围绕所述显示区的一非显示区。所述数个薄膜晶体管设置于该基板的显示区上。每一薄膜晶体管包含一栅电极层、一绝缘层、一有源层及一源漏极层。所述数个信号线设置于该基板的显示区上。所述数个信号线与所述数个薄膜晶体管的栅电极层同材料、同层且互相电连接。所述数个色阻单元设置于所述显示区内的薄膜晶体管及基板上。所述虚拟色阻单元设置于所述基板显示区的周边。所述虚拟色阻与所述数个色阻单元同材料且同层。所述虚拟色阻单元的一侧边或一中心点设计成与所述数个信号线中的一者相距一预设距离。
本揭示还公开一种色阻层对准精度检测方法，其包含：提供通过上述方法所制造的阵列基板；测量所述虚拟色阻单元的所述侧边或所述中心点相对于被设置成与所述侧边或所述中心点相距所述预设距离的所述信号线的距离；及比较所测量到的距离与所述预设距离。
在一实施例中，所述虚拟色阻单元被形成于所述基板的显示区的一边角或一侧边。
在一实施例中，所述虚拟色阻单元被构形成三角形、四角形、六角形、八角形、圆形、L字型、T字型、十字形或其组合。
在一实施例中，所述虚拟色阻单元被构形成四角形，每一侧边设计成与一邻近且互相平行的信号线相距所述预设距离。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中设有检测单元的COA阵列基板的示意图。
图2是现有技术中检测单元的示意图。
图3是本揭示实施例中设有虚拟色阻单元的COA阵列基板的示意图。
图4是图3的X区域的放大图。
图5是沿图3线B-B’的剖面图。
图6至图10是以图5为例的本揭示实施例的阵列基板制造方法的流程示意图。
具体实施方式
请参阅图3至图10。图3是本揭示实施例中设有虚拟色阻单元130的COA阵列基板100的示意图。图4是图3的X区域的放大图。图5是沿图3线B-B’的剖面图。图6至图10是以图5为例的本揭示实施例的阵列基板制造方法的流程示意图。本揭示实施例提供了一种阵列基板的制造方法，其包含步骤S1-S3。
步骤S1：提供一基板101，其中所述基板101包含一显示区110及围绕所述显示区110的一非显示区120。所述基板101可为一硬性基板，诸如玻璃基板，但不限于此。
步骤S2：形成数个薄膜晶体管150及数个信号线140于该基板101的显示区110上，其中每一薄膜晶体管150包含一栅电极层151、一绝缘层152、一有源层153及一源漏极层154，所述数个信号线140与所述数个薄膜晶体管150的栅电极层151以同材料同时制成且互相电连接。
步骤S3：形成数个色阻单元124于所述显示区110内的所述数个薄膜晶体管150及所述基板101上，并同时以与所述数个色阻单元相同的材料形成一虚拟色阻单元130于所述基板的显示区110的周边。所述虚拟色阻单元130的一侧边或一中心点设计成与所述数个信号线140中的一者相距一预设距离。所述数个色阻单元124可分别为红色、蓝色及绿色的光阻块。红色、蓝色及绿色的光阻块在显示区110内可为三角形配置、正方形配置、线形配置或马赛克形配置。所述数个色阻单元124可使用染色法、蚀刻法、印刷法、干膜法或电着法制成，但不限于此。所述虚拟色阻单元130可为红色、蓝色或绿色的光阻块。具体而言，所述虚拟色阻单元130与所述数个色阻单元124中的红色、蓝色或绿色的光阻块以同材料同时制成。
在一实施例中，所述虚拟色阻单元130是设置于所述基板的显示区110的一边角或一侧边。在一实施例中，所述虚拟色阻单元130的数量可为二个，分别设置在显示区110的两斜对角、同一侧边的两边角、两相对侧边，或是相邻的两侧边上。在一实施例中，所述虚拟色阻单元130的数量可为四个，分别设置在显示区110的四个边角或四个侧边上。然而，所述虚拟色阻单元130的数量和设置位置不限于此。
在一实施例中，所述虚拟色阻单元130可设计成三角形、四角形、六角形、八角形、圆形、L字型、T字型、十字形或其它适合的形状。较佳地，所述虚拟色阻单元130为一四角形且具有第一侧边131、第二侧边132、第三侧边133及第四侧边134。所述数个信号线140包含分别邻近且平行于第一侧边131、第二侧边132、第三侧边133及第四侧边134的第一信号线141、第二信号线142、第三信号线143及第四信号线144。将所述虚拟色阻单元130设置成：第一侧边131与第一信号线141相距一预设距离a、第二侧边132与第二信号线142相距一预设距离b、第三侧边133与第三信号线143相距一预设距离c，且第四侧边134与第四信号线144相距一预设距离d。所述预设距离a、b、c及d可相等、不相等或部分相等。
在一实施例中，步骤S2还包含：形成数个驱动电路160于所述基板101的非显示区120上。所述数个驱动电路160是与所述数个薄膜晶体管150的栅电极层151及所述数个信号线140以同材料同时制成。所述数个驱动电路160电连接于所述数个信号线140与一公共电压产生电路(图未示)。所述公共电压产生电路用于产生一公共电压。所述公共电压透过所述数个驱动电路160产生驱动信号至所述数个薄膜晶体管150的栅电极层151，来控制所述数个薄膜晶体管150的开关。
在一实施例中，所述数个薄膜晶体管150的绝缘层152延伸覆盖所述数个信号线140及所述数个驱动电路160。
在一实施例中，所述方法在步骤S2之后，还包含步骤S21：形成一保护层155，覆盖所述数个薄膜晶体管150。所述保护层155由一绝缘材料制成。所述保护层155可由诸如环氧树脂、压克力树脂、聚亚酰胺树脂及聚乙烯醇树脂等高分子绝缘材料所制成，但不限于此。
在一实施例中，所述方法在步骤S3之后，还包含步骤S32：形成一平坦层(overcoat)170，覆盖所述数个色阻单元124及所述虚拟色阻单元130。
在一实施例中，所述方法在步骤S3与S32之间，还包含步骤S31：形成一遮光层(即黑色矩阵(black matrix，BM)，图未示)。所述遮光层是用于遮蔽所述数个色阻单元124以外的区域，以(1)防止一薄膜晶体管液晶显示器的背光源漏光，进而提高所述显示器的对比度(2)防止背光源透过所述数个色阻单元124中相邻的红色、蓝色及绿色光阻块所产生的三原色光发生混色，以提高所述显示器的色纯度，(3)防止光造成TFT误动作及工作参数发生变化。所述遮光层可由黑色树脂、单层铬(Cr)或双层铬(Cr)/氧化铬(CrOx)组成。
在一实施例中，所述方法在步骤S32之后，还包含步骤S33：形成数个柱状的光学间隙子(photo spacer，图未示)于显示区内的所述平坦层上，以避免所述显示器的盒厚(cellgap)因压力而改变。所述数个光学间隙子具有相同的高度，以保持盒厚的均一性。
本揭示实施例还提供藉由上述方法所制成的一种阵列基板100。所述阵列基板100包含一基板101、数个薄膜晶体管150、数个信号线140、数个色阻单元124及一虚拟色阻单元130。所述基板101包含一显示区110及围绕所述显示区110的一非显示区120。所述基板100可为一硬性基板，诸如玻璃基板，但不限于此。所述数个薄膜晶体管150设置于该基板101的显示区110上。每一薄膜晶体管150包含一栅电极层151、一绝缘层152、一有源层153及一源漏极层154。所述数个信号线140设置于所述基板101的显示区110上，与所述数个薄膜晶体管150的栅电极层151同材料、同层且互相电连接。所述数个色阻单元124设置于所述显示区110内的薄膜晶体管150及基板101上。所述数个色阻单元124可分别为红色、蓝色及绿色的光阻块。红色、蓝色及绿色的光阻块在显示区110内可为三角形配置、正方形配置、线形配置或马赛克形配置。所述数个色阻单元124可使用染色法、蚀刻法、印刷法、干膜法或电着法制成，但不限于此。所述虚拟色阻单元130设置于所述基板101的显示区110的周边。所述虚拟色阻130与所述数个色阻单元124同材料且同层。所述虚拟色阻单元130的一侧边或一中心点设计成与所述数个信号线140中的一者相距一预设距离。所述虚拟色阻单元130可为红色、蓝色或绿色的光阻块。具体而言，所述虚拟色阻单元130与所述数个色阻单元124中的红色、蓝色或绿色的光阻块同材料且同层。
在一实施例中，所述虚拟色阻单元130是设置于所述基板的显示区110的一边角或一侧边。在一实施例中，所述虚拟色阻单元130的数量可为二个，分别设置在显示区110的两斜对角、同一侧边的两边角、两相对侧边，或是相邻的两侧边上。在一实施例中，所述虚拟色阻单元130的数量可为四个，分别设置在显示区110的四个边角或四个侧边上。然而，所述虚拟色阻单元130的数量和设置位置不限于此。
在一实施例中，所述虚拟色阻单元130可设计成三角形、四角形、六角形、八角形、圆形、L字型、T字型、十字形或其它适合的形状。较佳地，所述虚拟色阻单元130为一四角形且具有第一侧边131、第二侧边132、第三侧边133及第四侧边134。所述数个信号线140包含分别邻近且平行于第一侧边131、第二侧边132、第三侧边133及第四侧边134的第一信号线141、第二信号线142、第三信号线143及第四信号线144。将所述虚拟色阻单元130设置成：第一侧边131与第一信号线141相距一预设距离a、第二侧边132与第二信号线142相距一预设距离b、第三侧边133与第三信号线143相距一预设距离c，且第四侧边134与第四信号线144相距一预设距离d。所述预设距离a、b、c及d可相等、不相等或部分相等。
在一实施例中，所述阵列基板100还包含数个驱动电路160，设置于所述基板100的非显示区120上。所述数个驱动电路160是与所述数个薄膜晶体管150的栅电极层151及所述数个信号线140同材料且同层。所述数个驱动电路160电连接于所述数个信号线140与一公共电压产生电路(图未示)。所述公共电压产生电路用于产生一公共电压。所述公共电压透过所述数个驱动电路160产生驱动信号至所述数个薄膜晶体管150的栅电极层151，来控制所述数个薄膜晶体管150的开关。
在一实施例中，所述数个薄膜晶体管150的绝缘层152延伸覆盖所述数个信号线140及所述数个驱动电路160。
在一实施例中，所述阵列基板100还包含一保护层155，覆盖所述数个薄膜晶体管150。所述保护层155由一绝缘材料制成。所述保护层155可由诸如环氧树脂、压克力树脂、聚亚酰胺树脂及聚乙烯醇树脂等高分子绝缘材料所制成，但不限于此。
在一实施例中，所述阵列基板100还包含一平坦层(overcoat)170，覆盖所述数个色阻单元124及所述虚拟色阻单元130。
在一实施例中，所述阵列基板100还包含一遮光层，用于遮蔽所述数个色阻单元124以外的区域，以(1)防止一薄膜晶体管液晶显示器的背光源漏光，进而提高所述显示器的对比度(2)防止背光源透过所述数个色阻单元124中相邻的红色、蓝色及绿色光阻块所产生的三原色光发生混色，以提高所述显示器的色纯度，(3)防止光造成TFT误动作及工作参数发生变化。所述遮光层可以为黑色矩阵(black matrix，BM)层。所述遮光层可由黑色树脂、单层铬(Cr)或双层铬(Cr)/氧化铬(CrOx)组成。
在一实施例中，所述阵列基板100还包含数个柱状的光学间隙子(photo spacer，图未示)，设置于显示区内的所述平坦层上，以避免所述显示器的盒厚(cell gap)因压力而改变。所述数个光学间隙子具有相同的高度，以保持盒厚的均一性。
本揭示实施例还提供一种对准精度检测方法，其包含步骤S51-S53。
步骤S51：通过上述本揭示实施例的方法制造一阵列基板100，或提供上述本揭示实施例的阵列基板100。
步骤S52：测量所述虚拟色阻单元130的所述侧边或所述中心点相对于被设置成与所述侧边或所述中心点相距所述预设距离的所述信号线140的距离。
步骤S53：比较所测量到的距离与所述预设距离。
在一实施例中，所述虚拟色阻单元130为一四角形且具有第一侧边131、第二侧边132、第三侧边133及第四侧边134。所述数个信号线140包含分别邻近且平行于第一侧边131、第二侧边132、第三侧边133及第四侧边134的第一信号线141、第二信号线142、第三信号线143及第四信号线144。将所述虚拟色阻单元130设置成：第一侧边131与第一信号线141相距一预设距离a、第二侧边132与第二信号线142相距一预设距离b、第三侧边133与第三信号线143相距一预设距离c，且第四侧边134与第四信号线144相距一预设距离d。所述预设距离a、b、c及d可相等、不相等或部分相等。在此实施例中，步骤S52为：测量所述虚拟色阻单元130的测量所述虚拟色阻单元130的第一侧边131与第一信号线141的距离、第二侧边132与第二信号线142的距离、第三侧边133与第三信号线143的距离，及第四侧边134与第四信号线144的距离，且步骤S53为：将所测量到的第一侧边131与第一信号线141的距离、第二侧边132与第二信号线142的距离、第三侧边133与第三信号线143的距离，及第四侧边134与第四信号线144的距离，分别与所述预设距离a、b、c及d比较，用以推估所述数个色阻单元124的对准精度。
本揭示实施例所提供的阵列基板及其制造方法与对准精度检测方法，是将一虚拟色阻单元设置于所述基板的显示区的周边，及将所述虚拟色阻单元设计成各侧边与邻近的信号线相距不同、相同或部分相同的预设距离。因此，仅需测量所述虚拟色阻单元的各侧边和与其邻近的信号线的距离，并比较所测量到的距离与所述预设距离，即可推估所述数个色阻单元的对准精度。本揭示实施例所提供的阵列基板及其制造方法与对准精度检测方法无需在所述阵列基板的非显示区内设置数个检测单元，从而能进一步减少非显示区的面积，以实现超窄边框的显示面板设计。藉此，解决了先前技术在COA阵列基板非显示区设置数个检测单元而限制一显示面板的边框窄化的问题。
虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (10)

1.一种阵列基板的制造方法，其特征在于：其包含：
提供一基板，其中所述基板包含一显示区及围绕所述显示区的一非显示区；
形成数个薄膜晶体管及数个信号线于该基板的显示区上，其中每一薄膜晶体管包含一栅电极层、一绝缘层、一有源层及一源漏极层，所述数个信号线与所述数个薄膜晶体管的栅电极层以同材料同时制成且互相电连接；及
形成数个色阻单元于所述显示区内的所述数个薄膜晶体管及所述基板上，并同时以与所述数个色阻单元相同的材料形成一虚拟色阻单元于所述基板的显示区的周边上，其中所述虚拟色阻单元的一侧边或一中心点设计成与所述数个信号线中的一者相距一预设距离。
2.根据权利要求1所述的阵列基板的制造方法，其特征在于：所述虚拟色阻单元被形成于所述基板的显示区的一边角或一侧边。
3.根据权利要求1所述的阵列基板的制造方法，其特征在于：所述虚拟色阻单元被构形成三角形、四角形、六角形、八角形、圆形、L字型、T字型、十字形或其组合。
4.根据权利要求3所述的阵列基板的制造方法，其特征在于：所述虚拟色阻单元被构形成四角形，每一侧边设计成与一邻近且互相平行的信号线相距所述预设距离。
5.一种阵列基板，其特征在于：其包含：
一基板，包含一显示区及围绕所述显示区的一非显示区；
数个薄膜晶体管，设置于该基板的显示区上，其中每一薄膜晶体管包含一栅电极层、一绝缘层、一有源层及一源漏极层；
数个信号线，设置于该基板的显示区上，与所述数个薄膜晶体管的栅电极层同材料、同层且互相电连接；
数个色阻单元，设置于所述显示区内的薄膜晶体管及基板上；及
一虚拟色阻单元，设置于所述基板显示区的周边，其中所述虚拟色阻与所述数个色阻单元同材料且同层，且所述虚拟色阻单元的一侧边或一中心点设计成与所述数个信号线中的一者相距一预设距离。
6.根据权利要求5所述的阵列基板，其特征在于：所述虚拟色阻单元设置于所述基板的显示区的一边角或一侧边。
7.根据权利要求5所述的阵列基板，其特征在于：所述虚拟色阻单元为一四角形，每一侧边设计成与一邻近且互相平行的信号线相距所述预设距离。
8.一种色阻层对准精度检测方法，其特征在于：其包含：
通过权利要求1所述的方法制造一阵列基板，或提供权利要求5所述的阵列基板；
测量所述虚拟色阻单元的所述侧边或所述中心点相对于被设置成与所述侧边或所述中心点相距所述预设距离的所述信号线的距离；及
比较所测量到的距离与所述预设距离。
9.根据权利要求8所述的色阻层对准精度检测方法，其特征在于：所述虚拟色阻单元设置于所述基板的显示区的一边角或一侧边。
10.根据权利要求8所述的色阻层对准精度检测方法，其特征在于：所述虚拟色阻单元为一四角形，每一侧边设计成与一邻近且互相平行的信号线相距所述预设距离。
CN201910971862.1A 2019-10-14 2019-10-14 阵列基板及其制造方法与对准精度检测方法 Pending CN110716359A (zh)

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