CN110676310A - 高压垂直功率部件 - Google Patents

高压垂直功率部件 Download PDF

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CN110676310A
CN110676310A CN201911099089.0A CN201911099089A CN110676310A CN 110676310 A CN110676310 A CN 110676310A CN 201911099089 A CN201911099089 A CN 201911099089A CN 110676310 A CN110676310 A CN 110676310A
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CN110676310B (zh
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S·梅纳德
G·戈蒂埃
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Italian Semiconductor (tour) Co
STMicroelectronics Tours SAS
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Abstract

本公开的实施例涉及高压垂直功率部件。一种垂直功率部件，包括第一导电类型的硅衬底，在衬底的下表面上有第二导电类型的阱。第一阱在部件外围处与绝缘多孔硅圆环接界。多孔硅环的上表面仅与第一导电类型的衬底接触。绝缘多孔硅圆环向下穿入衬底中至大于阱的厚度的深度。

Description

高压垂直功率部件
本申请是申请日为2014年10月16日、申请号为201410553425.5、发明名称为“高压垂直功率部件”的发明专利申请的分案申请。
优先权要求
本申请要求2013年10月17日提交的法国专利申请No.1360094的优先权，该申请的内容在此通过引用在法律允许的最大范围内被并入本文。
技术领域
本公开内容涉及一种能够耐受高电压(高于500V)的垂直半导体功率部件，并且更具体而言涉及该部件的外围的结构。
背景技术
图1至图4显示了具有垂直结构的三端双向可控硅型(triac-type)高电压功率部件的截面图。这些不同示意图中的三端双向可控硅的区别在于它们的外围。
总体而言，附图显示由轻掺杂的N型衬底1(N-)形成的三端双向可控硅。衬底1的上表面和下表面包含P型掺杂层或阱3和阱4。上部层3包含重掺杂的N型区域5(N+)，并且下部层4在俯视图中与由区域5占据的区域基本上互补的区域中包含重掺杂的N型区域6(N+)。主要电极A1和A2分别被设置在衬底1的上表面和下表面上。根据这些情形，电极A2在衬底1的下表面的全部或者部分上扩展。该结构还包含在其上表面侧上的其上有栅极电极的栅极区域(未示出)。
图1显示了台面技术的三端双向可控硅。P型层3和4分别分布在轻掺杂衬底1(N-)的整个上表面和整个下表面之上扩展。环形沟槽被形成在三端双向可控硅的上表面的外围处，并且比层3更深地穿入衬底1。类似地，沟槽也被形成在三端双向可控硅的下表面的外围处，并且比层4更深地穿入衬底1。这些沟槽被填充有钝化玻璃9，从而形成玻璃钝化层。P型层3和4与衬底1之间的PN结浮现于玻璃层9上。主电极A1和A2被分别设置在三端双向可控硅的上表面和下表面上。
图2显示了平坦技术的三端双向可控硅。在轻掺杂N型硅衬底1(N-)中分别在衬底1的上表面侧和下表面侧上形成P型阱3和阱4。三端双向可控硅的上部外围和下部外围因此对应于衬底1。在阱3和阱4上分别设置主电极A1和A2。绝缘层11被设置在三端双向可控硅的上表面和下表面的未被电极A1和A2覆盖的部分上。在衬底1中在三端双向可控硅的上表面的外围和下表面的外围处分别形成重掺杂N型沟道停止环13和14(N+)。
图3显示了“平面阱”技术的三端双向可控硅。图3中的部件与图2中的部件的区别在于：图3中的部件由P型扩散壁15所包围。三端双向可控硅的下表面完全被主电极A2覆盖，并且P型层4在衬底1的整个下表面之上延伸直至壁15。P型阱3在三端双向可控硅的上表面上延伸且在扩散壁15前停止。沟道停止环13被设置在衬底1中在阱3和壁15之间。环形电极17可以覆盖沟道停止环13。
图4显示了“平面阱”技术的三端双向可控硅的变体，诸如关于2012年5月30日提交的法国专利申请No.1254987(通过引用并入)的图2描述的那样。图4所示的三端双向可控硅与图3所示的三端双向可控硅的不同之处在于：在其下表面侧上，包围部件的扩散外围壁15的下部部分已变为形成绝缘环19的绝缘的多孔硅。多孔硅绝缘环19比层4的厚度更深地向下穿入到衬底1中。
图1至图4中的每个三端双向可控硅都有各种优势和不利之处。
实际中，在图1所示的台面结构中，刻蚀沟槽的步骤、使用钝化玻璃9填充沟槽的步骤以及切割钝化玻璃9的步骤难于实施。
在图2所示的平坦结构中，不利之处在于部件组装步骤。实际上，如果电极A2期望被焊接至平板，则侧向焊料浸锡(wicking)可以将电极A2电连接至衬底1，从而使对应的PN结短路。因此需要将部件组装在焊盘上，这使得组装更为复杂。
在图3所示的“平坦阱”结构中，壁15将N-型衬底1与三端双向可控硅组件上三端双向可控硅的侧向表面上的可能的焊料浸锡隔离。然而，图3和图4的结构需要通过从衬底1上表面和下表面扩散掺杂剂元素形成侧向壁15。不利之处在于该步骤时间长，对于厚度为200至300微米的衬底和硼掺杂而言通常约为250小时。此外，需要在三端双向可控硅外围提供额外的空间来形成侧向的壁15，侧向壁15跨约为衬底1的厚度的宽度延伸。
防护距离(即，部件边缘和部件的有用部分的边缘之间的必要距离)取决于所涉及的外围类型。例如，对于大约为800V的击穿电压而言：
-图1的结构的防护距离e1大约为300微米，
-图2的结构的防护距离e2大约为200微米，
-图3和图4的结构的防护距离e3大约为400微米。
发明内容
期望能够有一种垂直功率部件，其具有可以积累现有结构的优势同时避免其不利之处的外围。更具体地，期望形成一种结构，其：
-能够避免部件的组件上的侧向焊料浸锡导致的短路；
-能够具有最小的可能防护距离；以及
-制造简单。
因此，一个实施例提供一种垂直功率部件，其包括第一导电类型的硅衬底；在衬底的下表面的侧部上的第二导电类型的第一阱，该阱在部件外围处与第一绝缘多孔硅环接界，该绝缘环的上表面只与第一导电类型的衬底接触；第一绝缘环比第一阱的厚度更深地向下穿入衬底中。
根据一个实施例，该部件进一步包括：在衬底的上表面侧上的第二导电类型的第二阱，该阱在部件外围处与第二绝缘多孔硅环接界，该绝缘环的下表面只与第一导电类型的衬底接触；第二绝缘环比第二阱的厚度更深地向下穿入至衬底中。
根据一个实施例，多孔硅被氧化。
根据一个实施例，第一导电类型为N型。
根据一个实施例，该部件形成三端双向可控硅。
另一实施例提供一种制造垂直功率部件的方法，该方法包括如下步骤：在N型掺杂衬底中分别在衬底的下表面和上表面上形成第一P型掺杂的阱和第二P型掺杂的阱；将衬底下表面陷入第一电解液浴中，以及在衬底的上表面和电解液浴之间循环第一电流以在衬底下表面侧上形成多孔硅。
根据一个实施例，该方法还包括如下步骤：将衬底上表面陷入第二电解液浴，以及在衬底的下表面和电解液浴之间循环第二电流以在衬底的上表面侧上形成多孔硅。
根据一个实施例，该方法还包括退火步骤来氧化多孔硅。
根据一个实施例，该方法还包括分别在第一阱和第二阱中形成第一N型掺杂区域和第二N型掺杂区域。
根据一个实施例，该方法还包括在第二阱中制作N型掺杂的栅极。
根据一个实施例，该方法还包括在衬底的上表面侧上形成沟道停止环。
附图说明
上述特性和优势以及其他的特性和优势将在下文具体实施例的非限制性描述中结合所附附图进行详细描述，其中：
之前描述的图1示意性显示了“台面”技术的三端双向可控硅的截面图。
之前描述的图2示意性显示了“平坦”技术的三端双向可控硅的截面图。
之前描述的图3和图4示意性显示了“平面阱”技术的两个三端双向可控硅的截面图。
图5示意性显示了三端双向可控硅的实施例的截面图。
图6A至图6C是示出制造图5的三端双向可控硅的方法的简化截面图。
图7是三端双向可控硅的备选实施例的简化截面图。
为了清楚起见，相同部件在各种示意图中以相同的附图标记指示，以及此外如半导体部件的表示中常用的那样，各个附图并不按比例绘制。
具体实施方式
图5显示了一种垂直三端双向可控硅型功率部件的实施例。该三端双向可控硅包括轻掺杂的N型硅衬底1(N-)。P型掺杂的阱3和阱4被分别设置在衬底1的上表面侧和下表面侧上。阱3包含重掺杂的N型区域5(N+)。类似地，阱4在平面图中在与由区域5占据的区域互补的区域中包含重掺杂N型区域6(N+)。主电极A1和A2分别被设置在阱3和阱4上。绝缘层11在阱3和阱4外边缘处被设置在该结构的上表面和下表面上。在衬底1中在衬底的上表面侧上在三端双向可控硅外围处形成重掺杂的N型沟道停止环13(N+)。在三端双向可控硅的上表面侧上形成其上有栅极电极的栅极区域。
在下表面侧上，阱4与在三端双向可控硅外围处形成的绝缘多孔硅环19侧向接界。环19比阱4的厚度更深地向下穿入至衬底中。
环19构成了N-型衬底1和P型阱4之间PN结的一个结末端。
在三端双向可控硅的下表面的外围处存在的绝缘环19有利于避免三端双向可控硅侧表面上的焊料浸锡，以例如当三端双向可控硅的电极A2经由焊膏组装到平板上时将衬底1电连接至电极A2。
图6A至图6C是在制造关于图5描述的三端双向可控硅型垂直功率部件的方法的一个实施例的相继步骤处获得的简化截面示意图。
图6A显示了在完成如下步骤后的轻掺杂N型硅衬底1(N-)的一部分：
-在衬底1中分别在部件的上表面侧和下表面侧上形成两个P型掺杂阱3和阱4；
-分别在阱3和阱4中形成重掺杂N型区域5和6(N+)；
-在部件的上表面的外围处形成重掺杂N型沟道停止环13(N+)。
作为示例，衬底1的厚度在从200到300微米的范围中，例如250微米。衬底1中的掺杂剂浓度可以在从1014到1015at./cm3的范围中，比如5*1014at./cm3。
可以通过传统注入步骤和/或扩散步骤制作阱3和阱4，例如，对衬底1中进行硼掺杂。阱3和阱4的掺杂剂元素浓度可以在从1018到1019at./cm3范围中，例如5*1018at./cm3。阱3和阱4可以具有在从10到50微米的范围中的厚度。例如，对于大约为600V的三端双向可控硅击穿电压而言，阱3和阱4的厚度可以约为20微米。
可以通过传统注入步骤和/或扩散步骤形成区域5和区域6以及沟道停止环13。区域5和6以及沟道停止环13中的掺杂剂元素浓度可以大于1019at./cm3，例如1020at./cm3。区域5和6以及沟道停止环13可以具有从5到20微米的范围中的厚度，例如约为10微米。
图6B显示在形成多孔硅绝缘环19之后的三端双向可控硅。可以在如下步骤期间形成多孔硅绝缘环19：
-将衬底下表面浸入包括例如氢氟酸和/或乙酸的混合物的电解液浴中，其中负电极浸入电解液浴中；
-在衬底的上表面布置正电极或者将衬底的上表面浸入包括例如氢氟酸和/或乙酸的混合物的电解液浴中，其中正电极浸入电解液浴中；
-在正电极和负电极之间施加电压以在衬底1中有空穴电流，空穴电流从N型衬底1和P型阱3之间的导电PN结并一路流至衬底的裸露的下表面。
该最后步骤持续的时间长到足以使多孔硅环19形成为期望厚度。
还可以例如通过在1000摄氏度在氧气氛围中执行额外的多孔硅氧化步骤达多个小时。这步骤可以加强多孔硅的绝缘特性。
在P型阱4的外围处形成绝缘环19。绝缘环19比阱4更深地穿入衬底1。具体而言，绝缘环的厚度选择为大于阱4的厚度，以避免在三端双向可控硅的组装期间侧向焊料浸锡导致的不利之处。例如，绝缘环的厚度可以在从20至80微米的范围中，例如对于具有20微米厚度的阱4而言，绝缘环的厚度为40微米。
应该注意，不在如图4描述的扩散侧壁15中形成绝缘环19。扩散侧壁15的缺乏使得能够去掉形成扩散壁所必须的长扩散步骤。此外，侧壁的缺乏使得能够抑制形成侧壁所必须的外围空间，因此与图3和图4中的三端双向可控硅相比，减小三端双向可控硅表面积。
在图5的三端双向可控硅中，三端双向可控硅的有源部分和三端双向可控硅的外围之间的防护距离e4等于关于图2所示的“平坦”型三端双向可控硅的防护距离。需要注意，如前面关于图1至图4所示，平坦型结构的防护距离小于台面和平坦阱型结构的防护距离。
图6C所示在如下步骤之后的三端双向可控硅：
-形成绝缘层11，例如，至少在三端双向可控硅上表面上，在阱3和阱4的外围处由玻璃制成。在三端双向可控硅的上表面侧上，层11与N-型衬底1接触且在沟道停止环和阱3之上部分延伸；
-在阱3上形成电极A1，并且在阱4上形成电极A2；
-切割具有在其中形成的三端双向可控硅的硅衬底1以获得单独的部件；以及
-在支撑体上组装三端双向可控硅。
在切割衬底1的步骤中，图1所示填充了绝缘玻璃的沟槽的取消避免了切割玻璃时出现的不利因素。
可以使用焊膏22执行在支撑物20上组装三端双向可控硅组的步骤。应该注意，多孔硅绝缘环19使得能够将衬底1与焊膏22的侧向焊料浸锡24隔离。应该注意，在前面描述的方法中，仅四个掩模步骤对于制造三端双向可控硅是必须的，即：
-用于形成阱3和阱4的步骤的一个掩膜板；
-用于形成区域5和区域6的步骤的一个掩膜板；
-用于形成绝缘层11的步骤的一个掩膜板；以及
-用于形成电极A1和电极A2的步骤的一个掩膜板。
因此，关于图6A至图6C描述的制造方法易于实施。
图7示出了垂直三端双向可控硅型功率部件的备选实施例。图7的晶闸管包括与图5所示的相同的元件，不同之处在于P型阱3与多孔硅绝缘环26侧向接界。绝缘环26向下穿入衬底中至比阱3的厚度更大的深度，从而绝缘环26的下表面仅与N-型衬底1接触。例如，绝缘环26的厚度可以在从20到80微米的范围中，例如对于具有20微米厚度的阱3而言为40微米。
绝缘环26形成了P型阱3和N-型衬底1之间PN结的结端。可以在关于图6B描述的步骤期间通过反转流过晶闸管的电流的方向来形成绝缘环26，其中三端双向可控硅的下表面与包括例如氟酸和乙酸的混合物的电解液浴接触。
图7显示了位于附图的右手侧的在阱3中形成的重掺杂N型栅极区域28(N+)。三端双向可控硅的栅极区域28未在其它示意图中显示。栅极电极G覆盖了阱3的一部分和区域28。
已经描述了具体实施例。本领域技术人员会想到各种替换、修改和改进。具体而言，已经在垂直功率部件为三端双向可控硅的情况中描述了本发明。应该理解，类似结构可以应用于任何其它已知类型的垂直双向功率部件，诸如双向肖特基二极管。本发明也可以适用于任何其它类型的垂直双向功率部件。此外，本发明不限于关于图6A至图6C描述的用于形成部件的制造方法的示例。本领域技术人员有能力通过使用用于形成各种层、区和/或阱的任何其它已知方法来形成所提供的结构。
虽然在上述实施例中已经描述了具有相同厚度和相同掺杂水平的防护环13以及区域5和区域6，但是本领域技术人员能够根据期望的三端双向可控硅的特性来适配形成三端双向可控硅的不同区域和/或层的厚度和掺杂水平。具体而言，已经描述具有N型衬底的实施例，但是通过反转各个层、区域和阱的导电类型，本发明也适用于P型衬底。
此外，一般适配用于形成三端双向可控硅的各种方法和修改可以例如在此应用以提供发射极短路空穴及其特定栅极配置。
这些替换、修改和改进旨在为本公开内容的一部分，并且旨在位于本发明的精神和范围内。因此，上述描述只是举例而非旨在限制。本发明仅根据下面的权利要求书及其等同范围进行限制。

Claims (31)

1.一种垂直功率部件，包括：
第一导电类型的硅衬底；
第二导电类型的第一阱，在所述硅衬底的下表面上，所述第二导电类型与所述第一导电类型相反；
在所述硅衬底中的第一绝缘多孔硅环，在所述垂直功率部件的外围边界处，所述第一绝缘多孔硅环与所述第一阱和所述硅衬底之间的第一PN结接触；
其中所述第一绝缘多孔硅环穿入所述硅衬底中至大于所述第一阱的厚度的深度。
2.根据权利要求1所述的垂直功率部件，还包括：
所述第二导电类型的第二阱，在所述硅衬底的、与所述下表面相对的上表面上；
在所述硅衬底中的第二绝缘多孔硅环，在所述部件的所述外围边界处，所述第二绝缘多孔硅环与所述第二阱和所述硅衬底之间的第二PN结接触；
其中所述第二绝缘多孔硅环穿入所述硅衬底中至大于所述第二阱的厚度的深度。
3.根据权利要求2所述的垂直功率部件，其中所述第二绝缘多孔硅环的下表面仅与所述硅衬底接触。
4.根据权利要求2所述的垂直功率部件，其中所述第二绝缘多孔硅环的侧表面在所述第二PN结处与所述硅衬底和所述第二阱两者接触。
5.根据权利要求1所述的垂直功率部件，其中所述第一绝缘多孔硅环被氧化。
6.根据权利要求1所述的垂直功率部件，其中所述第一导电类型为N型，并且所述第二导电类型为P型。
7.根据权利要求1所述的垂直功率部件，形成三端双向可控硅。
8.根据权利要求1所述的垂直功率部件，其中所述第一绝缘多孔硅环的侧表面在所述第一PN结处与所述硅衬底和所述第一阱两者接触。
9.根据权利要求1所述的垂直功率部件，其中所述第一绝缘多孔硅环的上表面仅与所述硅衬底接触。
10.一种垂直功率部件，包括：
硅衬底，由第一导电类型掺杂，并且具有上表面和与所述上表面相对的下表面；
第一阱，在所述硅衬底的所述下表面中，所述第一阱由第二导电类型掺杂，所述第二导电类型与所述第一导电类型相反；
第二阱，在所述硅衬底的所述上表面中，所述第二阱由所述第二导电类型掺杂；
所述第一导电类型的第一重掺杂区域，在所述第一阱中；
所述第一导电类型的第二重掺杂区域，在所述第二阱中；
环区域，由所述第一导电类型重掺杂，所述环区域围绕所述第二阱，但是与所述第二阱间隔开；以及
多孔硅绝缘环，围绕PN结并且与所述PN结接触，所述PN结存在于所述第一阱与所述硅衬底接触处；
其中所述部件不具有所述第二导电类型的周围扩散外围壁。
11.根据权利要求10所述的垂直功率部件，其中所述多孔硅绝缘环的厚度比所述第一阱的厚度厚。
12.根据权利要求10所述的垂直功率部件，还包括：
在所述下表面上的第一电极，与所述第一阱和所述第一重掺杂区域接触；以及
在所述上表面上的第二电极，与所述第二阱和所述第二重掺杂区域接触。
13.一种垂直功率部件，包括：
硅衬底，由第一导电类型掺杂，并且具有上表面和与所述上表面相对的下表面；
第一阱，在所述衬底的所述下表面中，所述第一阱由第二导电类型掺杂，所述第二导电类型与所述第一导电类型相反；
第二阱，在所述衬底的所述上表面中，所述第二阱由所述第二导电类型掺杂；
第一绝缘多孔硅环，围绕所述第一阱并且与第一PN结接触，所述第一PN结存在于所述硅衬底与所述第一阱彼此接触处；以及
第二绝缘多孔硅环，围绕所述第二阱并且与第二PN结接触，所述第二PN结由所述硅衬底与所述第二阱彼此接触形成。
14.根据权利要求13所述的垂直功率部件，还包括栅极电极，所述栅极电极与所述衬底的所述上表面上的所述第二阱接触，所述栅极电极与所述第二电极绝缘。
15.根据权利要求14所述的垂直功率部件，还包括所述第一导电类型的重掺杂区域，所述重掺杂区域在所述第二阱中，并且与所述栅极电极接触。
16.根据权利要求13所述的垂直功率部件，还包括：
所述第一导电类型的第一重掺杂区域，在所述第一阱中，并且与所述第一电极接触；以及
所述第一导电类型的第二重掺杂区域，在所述第二阱中，并且与所述第二电极接触。
17.一种方法，包括如下步骤：
在N型掺杂衬底中、在所述衬底的下表面上形成第一P型掺杂阱，
将所述衬底的所述下表面浸入第一电解液浴中，以及
在所述衬底的上表面和所述第一电解液浴之间循环第一电流，以使得在所述衬底的所述下表面上围绕所述第一P型掺杂阱形成第一多孔硅环，所述第一多孔硅环与由所述N型掺杂衬底和所述第一P型掺杂阱形成的PN结接触。
18.根据权利要求17所述的方法，还包括：在所述衬底的所述上表面中形成第一P型掺杂环，所述第一P型掺杂环与所述第一多孔硅环接触。
19.根据权利要求18所述的方法，还包括：在所述衬底的所述上表面上形成第二P型掺杂阱，所述第二P型掺杂阱由所述第一P型掺杂环围绕。
20.根据权利要求19所述的方法，还包括：在所述衬底的所述上表面上形成沟道停止环，其中所述沟道停止环被定位在所述第二P型掺杂阱和所述第一P型掺杂环之间。
21.根据权利要求18所述的方法，还包括：在所述衬底的所述上表面上形成第二P型掺杂阱。
22.根据权利要求21所述的方法，还包括：在所述衬底的所述上表面上形成沟道停止环，其中所述沟道停止环被定位为围绕所述第二P型掺杂阱。
23.根据权利要求17所述的方法，还包括：
在所述N型掺杂衬底中、在所述衬底的所述上表面上形成第二P型掺杂阱，
将所述衬底的所述上表面浸入第二电解液浴中，以及
在所述衬底的所述下表面和所述第二电解液浴之间循环第一电流，以使得在所述衬底的所述上表面上围绕所述第二P型掺杂阱形成第二多孔硅环，所述第二多孔硅环与由所述N型掺杂衬底和所述第二P型掺杂阱形成的PN结接触。
24.根据权利要求23所述的方法，还包括：执行退火以氧化所述第二多孔硅环。
25.根据权利要求23所述的方法，还包括：在所述第二P型掺杂阱中形成第二N型掺杂区域。
26.根据权利要求23所述的方法，还包括：在所述衬底的所述上表面上形成沟道停止环，其中所述沟道停止环被定位在所述第二P型掺杂阱和所述第二多孔硅环之间。
27.根据权利要求17所述的方法，还包括：执行退火以氧化所述第一多孔硅环。
28.根据权利要求17所述的方法，还包括：在所述第一P型掺杂阱中形成第一N型掺杂区域。
29.一种方法，包括如下步骤：
形成N型掺杂衬底，所述N型掺杂衬底具有第一表面、与所述第一表面相对的第二表面、以及外围侧壁表面，所述外围侧壁表面在所述第一表面和所述第二表面之间延伸；
在所述衬底的所述第一表面上形成P型掺杂阱；
将所述衬底的所述第一表面置于电解液浴中；以及
在所述衬底的所述第二表面和所述电解液浴之间循环电流，以在所述衬底的拐角处形成多孔硅环，所述衬底的所述第一表面在所述拐角处接触所述外围侧壁表面。
30.根据权利要求29所述的方法，还包括：执行退火以氧化所述多孔硅环。
31.根据权利要求29所述的方法，还包括：在所述P型掺杂阱中形成N型掺杂区域。
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