CN110581209A - 半导体器件和方法 - Google Patents
半导体器件和方法 Download PDFInfo
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- CN110581209A CN110581209A CN201910035366.5A CN201910035366A CN110581209A CN 110581209 A CN110581209 A CN 110581209A CN 201910035366 A CN201910035366 A CN 201910035366A CN 110581209 A CN110581209 A CN 110581209A
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- light emitting
- emitting diode
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- photosensitive
- layer
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Classifications
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- H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
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Abstract
在一个实施例中,一种方法包括:将发光二极管连接到衬底;用光敏密封剂密封发光二极管;穿过邻近发光二极管的光敏密封剂形成第一开口;以及在第一开口中形成导电通孔。本发明的实施例还涉及半导体器件和方法。
Description
技术领域
本发明的实施例涉及半导体器件和方法。
背景技术
由于各种电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度的不断提高,半导体工业经历了快速增长。在大多数情况下,集成密度的提高来自最小部件尺寸的反复减小,这允许将更多组件集成到给定区中。近年来,光学部件已经在越来越多的应用中与半导体器件集成,特别是由于对电话、笔记本电脑和其他便携式设备中的相机的需求不断增长。
发明内容
本发明的实施例提供了一种形成半导体器件的方法,包括:将发光二极管连接到衬底;用光敏密封剂密封所述发光二极管;穿过邻近所述发光二极管的所述光敏密封剂形成第一开口;以及在所述第一开口中形成导电通孔。
本发明的另一实施例提供了一种形成半导体器件的方法,包括:将第一结构连接到互连件,所述第一结构包括从载体衬底延伸的发光二极管,所述发光二极管的第一端子连接到所述互连件;去除所述载体衬底以暴露所述发光二极管;用光敏密封剂密封所述发光二极管;在密封所述发光二极管之后,形成延伸穿过所述光敏密封剂以接触所述互连件的第一导电通孔;以及形成将所述发光二极管的第二端子连接到所述第一导电通孔的导线。
本发明的又一实施例提供了一种半导体器件,包括:互连件;发光二极管,连接到所述互连件;光敏密封剂,围绕所述发光二极管;第一导电通孔,延伸穿过所述光敏密封剂,所述第一导电通孔电连接到所述互连件,所述第一导电通孔包括位于晶种层上的导电材料,所述晶种层设置在所述导电材料和所述互连件之间,所述晶种层还设置在所述导电材料和所述光敏密封剂之间;以及导线,将所述发光二极管连接到所述第一导电通孔。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该强调,根据工业中的标准实践,各个部件未按比例绘制并且仅用于说明的目的。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1至图18示出了根据一些实施例的用于形成激光器件的工艺的各种截面图。
图19示出了根据一些实施例的激光器件的操作。
图20至图22示出了根据一些其他实施例的用于形成激光器件的工艺的各种截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征不同的实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然这些仅是实例而不旨在限制。例如,元件的尺寸不限于所公开的范围或值,但可能依赖于工艺条件和/或器件所需的性能。此外,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。为了简单和清楚的目的,各个部件可以以不同的比例任意地绘制。
此外,为了便于描述,本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语,以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外,空间关系术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位),并且在本文中使用的空间关系描述符可以同样地作相应地解释。
根据一些实施例,导电通孔形成在多个发光二极管之间。顶部结构附接到底部结构。底部结构可以包括例如互连结构,并且包括形成在互连结构上的导电连接件。顶部结构包括衬底,衬底上形成有多个发光二极管,例如以栅格图案。顶部结构的相应发光二极管连接到底部结构的相应导电连接件。通过例如蚀刻工艺去除顶部结构的载体。在发光二极管周围和上面形成光敏密封剂,例如低温聚酰亚胺(LTPI)。通过蚀刻工艺在光敏密封剂中形成开口,暴露下面的底部结构的连接焊盘。利用蚀刻工艺代替通过显影光敏密封剂来形成开口,可以允许形成具有更细间距的开口。然后在开口中形成导电通孔,连接到下面的底部结构的连接焊盘。然后可以形成将导电通孔连接到发光二极管的导线。通过在附接发光二极管之后形成导电通孔,可以减小导电通孔坍塌的可能性,并且导电通孔可以形成为具有更高纵横比的更细的间距。
图1至图3示出了根据一些实施例的用于形成第一结构100的工艺的各种截面图。第一结构100包括载体衬底102,载体衬底102上形成有多个发光二极管104(参见图3)。
在图1中,提供了载体衬底102。载体衬底102可以是半导体衬底,例如体半导体、绝缘体上半导体(SOI)衬底等,其可以是掺杂的(例如,用p型或n型掺杂剂)或未掺杂的。载体衬底102可以是晶圆,例如硅晶圆。通常,SOI衬底是在绝缘层上形成的半导体材料层。绝缘体层可以是例如掩埋氧化物(BOX)层、氧化硅层等。绝缘层设置在衬底上,通常是硅或玻璃衬底。也可以使用其他衬底,例如多层或梯度衬底。在一些实施例中,载体衬底102的半导体材料可包括硅;锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或它们的组合。在特定实施例中,载体衬底102是GaAs衬底。
此外,在载体衬底102上形成第一反射结构106。第一反射结构106包括多层材料,例如电介质或半导体材料。这些层可以是掺杂的或未掺杂的。这些层可以通过合适的沉积工艺沉积,例如化学气相沉积(CVD),或者可以通过合适的外延工艺生长。第一反射结构106可以是分布式布拉格反射器,其使用具有不同折射率的材料的交替层来反射光。在一些实施例中,第一反射结构106包括载体衬底102的材料(例如,GaAs)的交替的掺杂层和未掺杂层,其中掺杂层具有与未掺杂层不同的折射率。掺杂剂可以是允许掺杂层具有与未掺杂层不同的折射率的任何掺杂剂。在一些实施例中,掺杂剂是诸如C的p型掺杂剂。在一些实施例中,第一反射结构106的掺杂层的掺杂剂浓度在约1E-17原子/cm3至约1E-18原子/cm3的范围内。因此,第一反射结构106可以在所得到的发光二极管104(参见图3)中形成p型反射区。第一反射结构106可以具有任何宽度。在一些实施例中,第一反射结构106具有14μm的宽度。
此外,在第一反射结构106上形成发射半导体区108。发射半导体区108还包括载体衬底102的材料(例如,GaAs)的掺杂层。发射半导体结108具有p型区和n型区,并且包括在操作期间以单个谐振频率发出激光的P-N结。p型区可以掺杂有p型掺杂剂,例如硼、铝、镓、铟等。n型区可以掺杂有n型掺杂剂,例如磷、砷等。在一些实施例中,p型区形成在n型区上方。发射半导体区108的n型区可以连接到第一反射结构106,使得光朝向第一反射结构106发射。
此外,在发射半导体区108上形成第二反射结构110。发射半导体区108的p型区可以连接到第二反射结构110。第二反射结构110包括多层材料,例如介电或半导电材料。这些层可以是掺杂的或未掺杂的。这些层可以通过合适的沉积工艺沉积,例如化学气相沉积(CVD),或者可以通过合适的外延工艺生长。第二反射结构110可以是分布式布拉格反射器,其使用具有不同折射率的材料的交替层来反射光。在一些实施例中,第二反射结构110包括载体衬底102的材料(例如,GaAs)的交替的掺杂和未掺杂层,其中掺杂层具有与未掺杂层不同的折射率。掺杂剂可以是允许掺杂层具有与未掺杂层不同的折射率的任何掺杂剂。在一些实施例中,掺杂剂是n型掺杂剂,例如Si。在一些实施例中,第二反射结构110的掺杂层的掺杂剂浓度范围为约1E-17原子/cm3至约1E-18原子/cm3。因此,第二反射结构110可以在所得到的发光二极管104中形成n型反射区(参见图3)。第二反射结构110的掺杂剂可以是与第一反射结构106的掺杂剂不同的掺杂剂。第二反射结构110可以具有任何宽度。在一些实施例中,第二反射结构110具有13μm的宽度。
反射结构106和110形成谐振腔,以帮助增强来自发射半导体区108的光的强度。反射结构106和110具有不同的反射率,例如反射结构106和110的折射率是不同的。在一些实施例中,第一反射结构106形成为具有比第二反射结构110低的反射率,以允许从发射半导体区108发射激光束。通过调整反射结构106和110的总高度和总掺杂量,反射结构106和110的折射率可以变化。例如,第一反射结构106的高度H1可以小于第二反射结构110的高度H2。在一些实施例中,高度H1在约2μm至约4μm的范围内(例如约3μm),并且高度H2在约5μm至约7μm的范围内(例如约6μm)。
在图2中,接触焊盘112形成在第二反射结构110上。接触焊盘112物理地和电连接到第二反射结构110,第二反射结构110本身物理地和电连接到发射半导体区108。因此,接触焊盘112连接到所得发光二极管104(见图3)的n型侧。作为形成接触焊盘112的示例,在第二反射结构110上形成晶种层。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上的铜层。可以使用例如物理气相沉积(PVD)等形成晶种层。然后在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成,并且可以暴露于光以进行图案化。光刻胶的图案对应于接触焊盘112。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过镀形成,例如电镀或化学镀等。导电材料可包括金属,如铜、钛、钨、铝等。然后,去除光刻胶和其上未形成导电材料的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶,例如使用氧等离子体等。一旦去除光刻胶,就去除晶种层的暴露部分,例如通过使用可接受的蚀刻工艺,例如通过湿或干蚀刻。晶种层的剩余部分和导电材料形成接触焊盘112。
此外,在接触焊盘112和第二反射结构110上形成钝化层114。钝化层114在后续处理期间保护第二反射结构110。钝化层114可以由无机材料形成,其可以是诸如氮化硅的氮化物、诸如氧化硅的氧化物等,并且可以通过诸如CVD等的沉积工艺形成。钝化层114也可以由聚合物形成,该聚合物可以是诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的光敏材料,并且可以通过旋涂等形成。
此外,在钝化层114的开口上形成凸块下金属(UBM)116。作为形成UBM 116的示例,钝化层114被图案化为具有暴露接触焊盘112的开口。图案化可以通过可接受的工艺进行,例如在钝化层114是光敏材料时通过将钝化层114暴露于光,或者通过使用例如各向异性蚀刻的蚀刻。如果钝化层114是光敏材料,则可以在曝光之后显影钝化层114。在钝化层114上方和开口中形成晶种层。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上的铜层。可以使用例如PVD等形成晶种层。然后在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成,并且可以暴露于光以进行图案化。光刻胶的图案对应于UBM 116。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过镀形成,例如电镀或化学镀等。导电材料可包括金属,如铜、钛、钨、铝等。然后,去除光刻胶和其上未形成导电材料的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶,例如使用氧等离子体等。一旦去除光刻胶,就去除晶种层的暴露部分,例如通过使用可接受的蚀刻工艺,例如通过湿或干蚀刻。晶种层的剩余部分和导电材料形成UBM116。
在图3中,形成延伸到载体衬底102中的凹槽120。凹槽120延伸穿过钝化层114、第二反射结构110、发射半导体区108和第一反射结构106,位于凹槽120之间的这些部件的剩余部分形成发光二极管104。可以通过使用例如各向异性蚀刻的可接受的蚀刻工艺来形成凹槽120。
发光二极管104以间距P1间隔开,间距P1由凹槽120的宽度确定。在一些实施例中,间距P1在约4μm至约7μm的范围内。此外,发光二极管104形成为锥形。第一反射结构106的下部具有下部宽度W1,第二反射结构110的上部具有上部宽度W2。在一些实施例中,下部宽度W1在约13μm至约15μm的范围内(例如约14μm),并且上部宽度W2在12μm至约14μm的范围内。
此外,不透明部分108B形成在发光二极管104的发射半导体区108中。在顶视图中,不透明部分108B在发射半导体区108的透明部分108A的周边延伸。不透明部分108B基本上阻挡或吸收来自发射半导体区108的光,使得光不在横向方向上(例如,在平行于载体衬底102的主表面的方向上)从发光二极管104发射。不透明部分108B包括发射半导体区108的氧化材料,并且可以通过氧化工艺形成,例如快速热氧化(RTO)工艺、化学氧化工艺、在含氧环境中实施的快速热退火(RTA)等。发射半导体区108的剩余透明部分108A可以在氧化期间被例如光刻胶掩蔽。
此外,保护间隔件124形成在发光二极管104的侧面上。保护间隔件124可以由诸如氮化硅、氧化硅、SiCN、它们的组合等的介电材料形成。保护间隔件124可以通过共形沉积以及然后进行各向异性蚀刻来形成。
图4示出了根据一些实施例的第二结构200的截面图。第二结构200可以是诸如集成电路、中介层等的器件。第二结构200包括半导体衬底202,其中诸如晶体管、二极管、电容器、电阻器等的器件形成在半导体衬底202中和/或上。这些器件可以通过互连结构204互连以形成集成电路,例如,互连结构204由半导体衬底上的一个或多个介电层中的金属化图案形成。互连结构204包括焊盘204A和204B,它们可以分别用于耦合到发光二极管104和外部连接。互连结构204还包括对准标记204C。在互连结构204上方形成钝化层206以保护该结构。钝化层206可以由一种或多种合适的介电材料制成,例如氧化硅、氮化硅、低k电介质(例如碳掺杂的氧化物)、极低k电介质(例如多孔碳掺杂的二氧化硅)、聚合物(例如聚酰亚胺)、阻焊剂、聚苯并恶唑(PBO)、苯并环丁烯(BCB)、模塑料等或它们的组合。图案化钝化层206,其中开口208暴露对准标记204C。暴露的对准标记204C用于在后续处理期间的精确定位。第二结构200还包括接触焊盘210,例如铝或铜焊盘或柱,其上形成外部连接。接触焊盘210位于可被称为第二结构200的相应有源侧的位置上,并且可通过例如光刻、蚀刻和镀工艺形成为延伸穿过钝化层206。
图5至图18示出了根据一些实施例的用于形成激光器件300的工艺的各种截面图。激光器件300可以在进一步处理中封装以形成例如图像传感器、光纤网络设备等。得到的器件可以是集成电路器件的一部分,例如片上系统(SoC)。
在图5中,第一结构100连接到第二结构200。第一结构100的发光二极管104连接到第二结构200的接触焊盘210。可以形成导电连接件302,导电连接件302连接发光二极管104的接触焊盘112与相应的接触焊盘210。导电连接件302可以由导电材料形成,例如焊料、铜、铝、金、镍、银、钯、锡等或者它们的组合。在一些实施例中,导电连接件302是焊料连接。在一些实施例中,通过首先通过诸如蒸发、电镀、印刷、焊料转移、球放置等常用方法在UBM 116或接触焊盘210上形成焊料层而形成导电连接件302。一旦在UBM 116或接触焊盘210上形成焊料层,接触焊盘210和UBM 116物理接触,并且可以实施回流以将材料成形为期望的凸块形状。在附接发光二极管104之后,发光二极管104、接触焊盘210和导电连接件302具有组合高度H3。在一些实施例中,组合高度H3在约13μm至约15μm的范围内(例如约14μm)。
当第一结构100连接到第二结构200时,发光二极管104的第二反射结构110(例如,n型侧或阴极)面向第二结构200,并且发光二极管104的第一反射结构106(例如,p型侧或阳极)面向第一结构100。如上所述,第一反射结构106具有比第二反射结构110低的反射率。因此,来自发射半导体区108的产生的激光束由第二反射结构110反射。一些反射激光束由第一反射结构106进一步反射,并且一些反射激光束透射通过第一反射结构106。
在图6中,去除载体衬底102,留下发光二极管104。可以通过蚀刻工艺去除载体衬底102,例如对载体衬底102的材料(例如,GaAs)具有选择性的干蚀刻。在去除之后,发光二极管104保留在激光器件300的发光区300A中。激光器件300还包括连接区300B和对准区300C。如进一步讨论的,在区300A、300B和300C中的每一个中形成导电通孔。
在图7中,在发光二极管104和钝化层206上形成钝化层304。钝化层304还沿着接触焊盘210和导电连接件302的侧面以及在开口208中延伸。层304可以包括氧化硅、氮化硅等,并且可以通过诸如化学气相沉积(CVD)的沉积工艺形成。在一些实施例中,钝化层304由氧化物(例如氧化硅)形成。钝化层304形成至厚度T1。在一些实施例中,厚度T1在约0.05μm至约0.1μm的范围内。
此外,在钝化层304上形成光敏密封剂306。光敏密封剂可以由例如LTPI形成,并且可以通过诸如旋涂的涂覆工艺形成。LTPI可以允许比氧化物更好的间隙填充,并且可以帮助避免空隙的形成。光敏密封剂306形成为厚度T2,厚度T2大于钝化层304的厚度T1。在一些实施例中,厚度T2在约14μm至约16μm的范围内。光敏密封剂306围绕并且掩埋发光二极管104。光敏密封剂306在发光二极管104上的部分具有厚度T3。在一些实施例中,厚度T3在约2μm至约3μm的范围内。
在图8中,实施平坦化工艺以平坦化和薄化光敏密封剂306。特别地,减少了发光二极管104上的光敏密封剂306的量。平坦化工艺可以是例如研磨工艺、化学机械抛光(CMP)工艺等。在平坦化和薄化之后,在发光二极管104上方的光敏密封剂306的部分具有减小的厚度T4,厚度T4小于厚度T3。在一些实施例中,减小的厚度T4在约1μm至约2μm的范围内(例如约1μm)。
此外,在对准标记204C上方的对准区300C中形成开口308。开口308可以通过光刻工艺形成。例如,光敏密封剂306可以暴露于光以进行图案化,并且显影以形成开口308。在一些实施例中,开口308暴露对准标记204C上方的钝化层304的部分。在一些实施例中,开口308延伸穿过钝化层304以暴露对准标记204C。
在图9中,在光敏密封剂306上形成掩模层312。掩模层312可以由金属或含金属材料形成,例如Ti、Cu、TiW、TaN、TiN及其组合,或其多层,并且可以称为硬掩模层。掩模层312可以通过诸如物理气相沉积(PVD)、CVD等的沉积工艺形成。掩模层312还可以延伸到开口308中。
此外,在掩模层312上形成光刻胶314。光刻胶314可以是单层光刻胶、三层光刻胶等,并且直接形成在(例如,接触)掩模层上。光刻胶314可以通过旋涂等形成,并且可以暴露于光以进行图案化。在一些实施例中,光刻胶314包括底部抗反射涂层(BARC)或吸收层,使得仅光刻胶314暴露于光,并且光敏密封剂306不暴露于光或显影。图案化形成穿过光刻胶314的开口以暴露掩模层312。
在图10中,通过将光刻胶314的图案转移到掩模层312,然后将掩模层312的图案转移到光敏密封剂306来图案化光敏密封剂306。可以使用图案化的光刻胶314作为蚀刻掩模,通过可接受的蚀刻工艺图案化掩模层312,例如通过湿蚀刻、干蚀刻或它们的组合。然后使用图案化的掩模层312作为蚀刻掩模,可以通过可接受的蚀刻工艺图案化光敏密封剂306,例如干蚀刻。在一些实施例中,干蚀刻是等离子体蚀刻,其可以用诸如O2中的CF4气体的蚀刻剂来实施。图案化形成穿过光敏密封剂306的开口316A和316B,以分别暴露互连结构204的焊盘204A和204B。开口316A和316B可具有不同的尺寸。开口316A具有上部宽度W3和下部宽度W4。在一些实施例中,上部宽度W3在约3μm至约5μm的范围内(例如约3μm),并且下部宽度W4在约2μm至约4μm的范围内。开口316B具有上部宽度W5和下部宽度W6。上部宽度W5大于上部宽度W3,下部宽度W6大于下部宽度W4。在一些实施例中,上部宽度W5在约70μm至约90μm的范围内,下部宽度W6在约50μm至约70μm的范围内(例如约50μm)。一旦完成光敏密封剂306的图案化,可以通过例如蚀刻工艺、灰化工艺、其组合等去除掩模层312和光刻胶314的剩余部分。
尽管光敏密封剂306本身是光敏的,但是仍然使用光刻胶314和掩模层312通过光刻和蚀刻工艺对其进行图案化。利用光刻和蚀刻工艺形成开口316A和316B可以允许开口316A和316B比通过曝光和显影图案化光敏密封剂306形成的开口(例如开口308)更小并且具有更细的间距。
在图11中,晶种层324形成在光敏密封剂306上方和开口308、316A和316B中。在一些实施例中,晶种层324是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层324包括钛层和钛层上的铜层。可以使用例如PVD等形成晶种层324。
在图12中,导电材料326形成在晶种层324上和开口308、316A和316B中。导电材料326可包括金属,例如铜、钛、钨、铝等。导电材料326可以通过镀形成,例如电镀或化学镀等。
在图13中,实施平坦化工艺以平坦化导电材料326和光敏密封剂306。平坦化工艺可以是例如研磨工艺、CMP工艺等。导电材料326和晶种层324的剩余部分分别在开口308、316A和316B中形成导电通孔328A、328B和328C。导电通孔328A、328B分别物理地和电连接到焊盘204A和204B。可选地,导电通孔328C可以连接到对准标记204C。在对准标记204C未被开口308暴露的实施例中,导电通孔328C可以是电隔离的非功能性通孔,其用于工艺对准。
在图14中,在光敏密封剂306和导电通孔328A、328B和328C上形成光刻胶334。光刻胶334可以是单层光刻胶、三层光刻胶等,可以通过旋涂等形成,并且可以暴露于光以进行图案化。在一些实施例中,光刻胶334包括底部抗反射涂层(BARC)或吸收层,使得仅光刻胶334暴露于光,并且光敏密封剂306不暴露于光或显影。图案化形成穿过光刻胶334的开口,以暴露光敏密封剂306的部分。
在图15中,通过将光刻胶334的图案转移到光敏密封剂306,然后将光敏密封剂306的图案转移到钝化层304来图案化钝化层304。可以通过可接受的蚀刻工艺图案化光敏密封剂306,例如使用光刻胶334作为蚀刻掩模的干蚀刻。在一些实施例中,干蚀刻是等离子体氧化物蚀刻。然后可以通过可接受的蚀刻工艺图案化钝化层304,例如使用光敏密封剂306作为蚀刻掩模的湿蚀刻。图案化形成穿过钝化层304的开口336以暴露发光二极管104的第一反射结构106。可以通过可接受的灰化或剥离工艺(例如使用氧等离子体等)去除光刻胶334。利用光刻和蚀刻工艺形成开口336可以允许开口336比通过光曝光和显影图案化光敏密封剂306而形成的开口(例如开口308)更小并且具有更细的间距。
在图16中,导线338形成在开口336中,从而形成用于发光二极管104的第一反射结构106的接触件。在光敏密封剂306上和开口336中形成晶种层。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上的铜层。可以使用例如PVD等形成晶种层。然后在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成,并且可以暴露于光以进行图案化。光刻胶的图案对应于导线338。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过镀形成,例如电镀或化学镀等。导电材料可包括金属,如铜、钛、钨、铝等。然后,去除光刻胶和其上未形成导电材料的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶,例如使用氧等离子体等。一旦去除光刻胶,就去除晶种层的暴露部分,例如通过使用可接受的蚀刻工艺,例如通过湿或干蚀刻。晶种层的剩余部分和导电材料形成导线338。
除了作为第一反射结构106的接触件之外,导线338还将发光二极管104连接到导电通孔328A。在形成之后,互连结构204通过导电连接件302电连接到第二反射结构110,并且互连结构204通过导线338和导电通孔328A电连接到第一反射结构106。
此外,测试焊盘340形成在导电通孔328B上。测试焊盘340可以用于激光器件300的后续测试。在一些实施例中,可以在制造激光器件300的工艺的中间阶段实施测试,并且可以仅使用已知的良好器件(KGD)来进行进一步处理。测试焊盘340通过导电通孔328B电连接到互连结构204。
在图17中,在导线338、测试焊盘340和光敏密封剂306上形成钝化层342。钝化层342可以包括氧化硅、氮化硅等,并且可以通过诸如CVD的沉积工艺形成。在一些实施例中,钝化层342由氮化物(诸如氮化硅)形成。
在图18中,图案化钝化层342,钝化层342的剩余部分覆盖导线338。因此可以暴露导电通孔328B和328C。可以在导电通孔328B上形成外部连接。在形成外部连接之前,可以(或可以不)去除测试焊盘340。例如,可以在器件测试之后并且在形成外部连接之前去除测试焊盘340。在一些实施例中,到导电通孔328B的外部连接是引线接合连接。在一些实施例中,外部连接未形成到导电通孔328C,并且导电通孔328C在最终激光器件300中保持电隔离。
图19示出了根据一些实施例的激光器件300的操作。激光器件300可以用作深度传感器400的激光束源。激光器件300可以脉冲产生激光束,并且可以在被目标404反射之后由检测器402接收。可以测量激光束的往返时间并且用于计算深度传感器400和目标404之间的距离。检测器402可以是例如CMOS图像传感器,例如光电二极管。在一些实施例中,检测器402形成在与激光器件300相同的衬底上。例如,检测器402可以形成在第二结构200的半导体衬底202中(参见图4)。
图20至图22示出了根据一些其他实施例的用于形成第一结构100的工艺的各种截面图。在该实施例中,掩模层312不与光刻胶314一起去除,而是在形成导电材料326之后被去除。在图20中,晶种层324直接形成在掩模层312上方和开口308、316A和316B中。在图21中,导电材料326形成在晶种层324上和开口308、316A和316B中。在图22中,实施平坦化工艺以平坦化导电材料326和光敏密封剂306。通过平坦化工艺去除覆盖光敏密封剂306的晶种层324和掩模层312的部分。所得导电通孔328C通过掩模层312电隔离。
实施例可以实现优点。通过在附接发光二极管104之后形成导电通孔328A、328B和328C,可以减小塌陷的导电通孔的可能性。此外,通过光刻和蚀刻而不是曝光和显影来在光敏密封剂306中形成开口316A,导电通孔328A可以形成为具有更高纵横比的更细的间距,这在导电通孔328A形成在发光二极管104之间时是重要的。特别地,导电通孔328A可以具有高达4.2的纵横比。
在一个实施例中,一种方法包括:将发光二极管连接到衬底;用光敏密封剂密封发光二极管;通过邻近发光二极管的光敏密封剂形成第一开口;以及在第一开口中形成导电通孔。
在该方法的一些实施例中,在第一开口中形成导电通孔包括:在光敏密封剂上形成掩模层;在掩模层上形成光刻胶;用对应于第一开口的第一图案图案化光刻胶;通过第一蚀刻工艺将第一图案从光刻胶转移到掩模层;通过第二蚀刻工艺将第一图案从掩模层转移到光敏密封剂。在该方法的一些实施例中,第一蚀刻工艺是湿蚀刻。在该方法的一些实施例中,第二蚀刻工艺是等离子体氧化物蚀刻。在该方法的一些实施例中,掩模层包括Ti、Cu、TiW、TaN、TiN或它们的组合。在该方法的一些实施例中,发光二极管包括:第一反射结构,包括半导体材料的第一掺杂层,交替的第一掺杂层掺杂有p型掺杂剂;第二反射结构,包括半导体材料的第二掺杂层,交替的第二掺杂层掺杂有n型掺杂剂;以及发射半导体区,设置在第一反射结构和第二反射结构之间。在一些实施例中,该方法还包括:在光敏密封剂中形成第二开口,第二开口暴露发光二极管;以及在第二开口中镀导线,导线连接发光二极管的第一反射结构和导电通孔。在该方法的一些实施例中,发光二极管还包括位于第二反射结构上的接触焊盘,并且将发光二极管连接到衬底包括:将发光二极管的接触焊盘连接到衬底。
在一个实施例中,一种方法包括:将第一结构连接到互连件,第一结构包括从载体衬底延伸的发光二极管,发光二极管的第一端子连接到互连件;去除载体衬底以暴露发光二极管;用光敏密封剂密封发光二极管;在密封发光二极管之后,形成延伸穿过光敏密封剂以接触互连件的第一导电通孔;以及形成将发光二极管的第二端子连接到第一导电通孔的导线。
在该方法的一些实施例中,载体衬底包括半导体材料,并且该方法还包括:在载体衬底上形成第一反射结构,第一反射结构包括半导体材料的第一掺杂层,交替的第一掺杂层掺杂有p型掺杂剂;在第一反射结构上形成发射半导体区;在发射半导体区上形成第二反射结构,第二反射结构包括半导体材料的第二掺杂层,交替的第二掺杂层掺杂有n型掺杂剂;并且图案化第一反射结构、第二反射结构和发射半导体区以形成发光二极管。在一些实施例中,该方法还包括:在第二反射结构上形成接触焊盘;在接触焊盘和第二反射结构上沉积钝化层;在钝化层中形成暴露接触焊盘的开口;并且在开口中形成凸块下金属(UBM)以耦合接触焊盘。在该方法的一些实施例中,将第一结构连接到互连件包括:形成将凸块下金属电连接到互连件的导电连接件,光敏密封剂还密封导电连接件。在该方法的一些实施例中,发光二极管连接到互连件的第一区,互连件包括位于第二区中的对准标记,并且该方法还包括:形成延伸穿过光敏密封剂以接触互连件的第二导电通孔。在该方法的一些实施例中,形成第一导电通孔包括:在光敏密封剂上形成掩模层;图案化掩模层以形成图案化的掩模;将图案化的掩模的图案转移到光敏密封剂,以在互连件的第一区上方的光敏密封剂中形成第一开口;在第一开口中镀第一导电通孔。在该方法的一些实施例中,形成第二导电通孔包括:将光敏密封剂的部分暴露于光;以及显影光敏密封剂的暴露部分,在互连件的第二区上方的光敏密封剂中形成第二开口;在第二开口中镀第二导电通孔。
在一个实施例中,一种器件包括:互连件;发光二极管,连接到互连件;光敏密封剂,围绕发光二极管;第一导电通孔,延伸穿过光敏密封剂,第一导电通孔电连接到互连件,第一导电通孔包括位于晶种层上的导电材料,晶种层设置在导电材料和互连件之间,晶种层进一步设置在导电材料和光敏密封剂之间;以及导线,将发光二极管连接到第一导电通孔。
在器件的一些实施例中,发光二极管包括:第一反射结构,包括半导体材料的第一掺杂层,交替的第一掺杂层掺杂有p型掺杂剂;第二反射结构,包括半导体材料的第二掺杂层,交替的第二掺杂层掺杂有n型掺杂剂;以及发射半导体区,设置在第一反射结构和第二反射结构之间。在该器件的一些实施例中,发光二极管还包括位于第二反射结构上的接触焊盘,并且互连件还包括接触焊盘。在该器件的一些实施例中,发光二极管还包括位于接触焊盘上的凸块下金属(UBM)。在一些实施例中,该器件还包括:导电连接件,将发光二极管的凸块下金属连接到互连件的接触焊盘,光敏密封剂围绕导电连接件。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到,这种等同构造并且不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中它们可以做出多种变化、替换以及改变。
Claims (10)
1.一种形成半导体器件的方法,包括:
将发光二极管连接到衬底;
用光敏密封剂密封所述发光二极管;
穿过邻近所述发光二极管的所述光敏密封剂形成第一开口;以及
在所述第一开口中形成导电通孔。
2.根据权利要求1所述的方法,其中,在所述第一开口中形成所述导电通孔包括:
在所述光敏密封剂上形成掩模层;
在所述掩模层上形成光刻胶;
用对应于所述第一开口的第一图案图案化所述光刻胶;
通过第一蚀刻工艺将所述第一图案从所述光刻胶转移到所述掩模层;
通过第二蚀刻工艺将所述第一图案从所述掩模层转移到所述光敏密封剂。
3.根据权利要求2所述的方法,其中,所述第一蚀刻工艺是湿蚀刻。
4.根据权利要求2所述的方法,其中,所述第二蚀刻工艺是等离子体氧化物蚀刻。
5.根据权利要求2所述的方法,其中,所述掩模层包括Ti、Cu、TiW、TaN、TiN或它们的组合。
6.根据权利要求1所述的方法,其中,所述发光二极管包括:
第一反射结构,包括半导体材料的第一掺杂层,交替的第一掺杂层掺杂有p型掺杂剂;
第二反射结构,包括半导体材料的第二掺杂层,交替的第二掺杂层掺杂有n型掺杂剂;以及
发射半导体区,设置在所述第一反射结构和所述第二反射结构之间。
7.根据权利要求6所述的方法,还包括:
在所述光敏密封剂中形成第二开口,所述第二开口暴露所述发光二极管;以及
在所述第二开口中镀导线,所述导线连接所述发光二极管的所述第一反射结构和所述导电通孔。
8.根据权利要求6所述的方法,其中,所述发光二极管还包括位于所述第二反射结构上的接触焊盘,并且将所述发光二极管连接到所述衬底包括:将所述发光二极管的所述接触焊盘连接到所述衬底。
9.一种形成半导体器件的方法,包括:
将第一结构连接到互连件,所述第一结构包括从载体衬底延伸的发光二极管,所述发光二极管的第一端子连接到所述互连件;
去除所述载体衬底以暴露所述发光二极管;
用光敏密封剂密封所述发光二极管;
在密封所述发光二极管之后,形成延伸穿过所述光敏密封剂以接触所述互连件的第一导电通孔;以及
形成将所述发光二极管的第二端子连接到所述第一导电通孔的导线。
10.一种半导体器件,包括:
互连件;
发光二极管,连接到所述互连件;
光敏密封剂,围绕所述发光二极管;
第一导电通孔,延伸穿过所述光敏密封剂,所述第一导电通孔电连接到所述互连件,所述第一导电通孔包括位于晶种层上的导电材料,所述晶种层设置在所述导电材料和所述互连件之间,所述晶种层还设置在所述导电材料和所述光敏密封剂之间;以及
导线,将所述发光二极管连接到所述第一导电通孔。
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