CN110581077B - 半导体封装件及其形成方法 - Google Patents

半导体封装件及其形成方法 Download PDF

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CN110581077B
CN110581077B CN201910184027.3A CN201910184027A CN110581077B CN 110581077 B CN110581077 B CN 110581077B CN 201910184027 A CN201910184027 A CN 201910184027A CN 110581077 B CN110581077 B CN 110581077B
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vias
forming
conductive trace
package
connection structure
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CN110581077A (zh
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陈建勋
吴俊毅
李建勋
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例提供了形成封装件的方法，该方法包括将封装组件放置在载体上方，将封装组件密封在密封剂中，以及在封装组件上方形成电连接至封装组件的第一连接结构。形成第一连接结构包括：在封装组件上方形成电连接至封装组件的第一通孔组，在第一通孔组上方形成接触第一通孔组的第一导电迹线，在第一导电迹线上面形成接触第一导电迹线的第二通孔组，其中，第一通孔组和第二通孔组的每个均包括多个通孔，在第二通孔组上方形成接触第二通孔组的第二导电迹线，在第二导电迹线上面形成接触第二导电迹线的顶部通孔，以及在顶部通孔上方形成接触顶部通孔的凸块下金属(UBM)。本发明的实施例还提供了封装件。

Description

半导体封装件及其形成方法
技术领域
本发明涉及半导体领域，并且更具体地，涉及半导体封装件及其形成方法。
背景技术
随着半导体技术的发展，半导体芯片/管芯变得越来越小。同时，需要将更多功能集成至半导体管芯。因此，半导体管芯需要将越来越多的I/O焊盘封装至更小的区域，并且I/O焊盘的密度随时间迅速上升。因此，半导体管芯的封装变得更加困难，这不利地影响了封装件的良率。
传统的封装技术可以分为两类。在第一类中，晶圆上的管芯在锯切之前封装。这种封装技术具有一些有利特征，诸如更高的产量和更低的成本。此外，需要较少的底部填充物或模塑料。然而，这种封装技术也存在缺点。由于管芯的尺寸变得越来越小，并且相应的封装件只能是扇入型封装件，其中，每个管芯的I/O焊盘限于相应管芯的表面正上方的区域。由于管芯的有限区域，I/O焊盘的数量由于I/O焊盘的间距的限制而受到限制。如果要减小焊盘的间距，则可能发生焊料桥接。此外，在固定的球尺寸要求下，焊球必须具有一定尺寸，这进而限制了可以封装在管芯表面上的焊球的数量。
在另一类封装件中，管芯在它们被封装之前从晶圆锯切。这种封装技术的一个有利特征是可以形成扇出封装件，这意味着管芯上的I/O焊盘可以再分布至比管芯更大的区域，并且因此可以增加封装在管芯的表面上的I/O焊盘的数量。该封装技术的另一有利特征是封装“已知良好管芯”，并且丢弃有缺陷的管芯，并且因此不会对有缺陷的管芯浪费成本和精力。
发明内容
根据本发明的实施例，提供了一种形成封装件的方法，包括：将封装组件放置在载体上方；将所述封装组件密封在密封剂中；以及在所述封装组件上方形成电连接至所述封装组件的第一连接结构，其中，形成所述第一连接结构包括：在所述封装组件上方形成电连接至所述封装组件的第一通孔组；在所述第一通孔组上方形成接触所述第一通孔组的第一导电迹线；在所述第一导电迹线上面形成接触所述第一导电迹线的第二通孔组，其中，所述第一通孔组和所述第二通孔组的每个均包括多个通孔；在所述第二通孔组上方形成接触所述第二通孔组的第二导电迹线；在所述第二导电迹线上面形成顶部通孔；以及在所述顶部通孔上方形成接触所述顶部通孔的凸块下金属(UBM)。
根据本发明的实施例，还提供了一种形成封装件的方法，包括：将第一封装组件和第二封装组件放置在载体上方，其中，所述第一封装组件具有比所述第二封装组件更大的顶视图区域，并且所述第一封装组件包括电连接件；将所述第一封装组件和所述第二封装组件密封在密封剂中；在所述第一封装组件的外围区域上方形成第一连接结构，其中，所述第一连接结构电连接至所述电连接件，并且所述第一连接结构包括：第一金属柱；第一顶部通孔，位于所述第一金属柱下面并且电连接至所述第一金属柱；第一导电迹线，位于所述第一顶部通孔下面；第一通孔组，位于所述第一导电迹线下面并且接触所述第一导电迹线，其中，所述第一通孔组包括多个第一通孔，并且所述第一通孔组具有第一轮廓区域；第二导电迹线，位于所述第一通孔组下面并且电连接至所述第一通孔组；以及第二通孔组，位于所述第二导电迹线下面并且接触所述第二导电迹线，其中，所述第二通孔组包括多个第二通孔，并且所述第二通孔组具有与所述第一轮廓区域重叠的第二轮廓区域。
根据本发明的实施例，还提供了一种封装件，包括：凸块下金属(UBM)；顶部通孔，位于所述凸块下金属下面并且电连接至所述凸块下金属；第一导电迹线，位于所述顶部通孔下面并且电连接至所述顶部通孔；第一通孔组，位于所述第一导电迹线下面并且接触所述第一导电迹线，其中，所述第一通孔组包括多个第一通孔，并且所述第一通孔组具有第一轮廓区域；第二导电迹线，位于所述第一通孔组下面并且电连接至所述第一通孔组；以及第二通孔组，位于所述第二导电迹线下面并且接触所述第二导电迹线，其中，所述第二通孔组包括多个第二通孔，并且所述第二通孔组具有与所述第一轮廓区域重叠的第二轮廓区域，并且所述多个第一通孔与所述多个第二通孔垂直未对准。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图10示出了根据一些实施例的扇出封装件的形成中的中间阶段的截面图。
图11示出了根据一些实施例的非接地连接结构的透视图。
图12A、图12B和图12C示出了根据一些实施例的非接地连接结构中的各个导电迹线(焊盘)的顶视图。
图13A、图13B、图13C和图13D示出了根据一些实施例的非接地连接结构中的通孔和对应的轮廓区域的顶视图。
图14A、图14B、图14C、图14D、图14E、图15至图18、图19A、图19B、图19C、图19D、图20A、图20B、图20C、图21A、图21B、图21C、图22A、图22B和图22C示出了根据一些实施例的非接地连接结构的截面图和顶视图。
图23示出了根据一些实施例的接地连接结构的透视图。
图24A、图24B和图24C示出了根据一些实施例的接地连接结构中的导电迹线(焊盘)的顶视图。
图25和图26示出了根据一些实施例的一些扇出封装件的布局。
图27示出了根据一些实施例的包括单通孔连接件的连接结构。
图28至图31示出了根据一些实施例的via-0结构和对应的封装件。
图32示出了根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据各个实施例提供了扇出封装件及其形成方法。根据一些实施例示出了形成扇出封装件的中间阶段。讨论了一些实施例的一些变型。贯穿各个附图和示例性实施例，相同的参考标号用于表示相同的元件。根据一些实施例，扇出封装件包括多通孔连接(通孔组)以提高可靠性，并且减小了产生的连接件的应力。
图1至图10示出了根据本发明的一些实施例的扇出封装件的形成中的中间阶段的截面图。图1至图10所示的工艺也示意性地反映在图32所示的工艺流程200中。
图1示出了载体20和形成在载体20上方的释放膜22。载体20可以是玻璃载体、陶瓷载体等。载体20可以具有圆形顶视图形状，并且可以具有硅晶圆的尺寸。例如，载体20可以具有8英寸直径、12英寸直径等。释放膜22可以由基于聚合物的材料(诸如，光热转换(LTHC)材料)形成，其可以与载体20一起从将在随后的步骤中形成的上面的结构去除。根据本发明的一些实施例，释放膜22由基于环氧树脂的热释放材料形成。根据本发明的一些实施例，释放膜22由紫外(UV)胶形成。
图1进一步示出了封装组件26(包括26A和26B)在载体20上方的放置。相应的工艺示出为图32所示的工艺流程中的工艺202。封装组件26可以通过管芯附接膜(DAF)24(其是粘合膜)粘合至释放膜22。根据本发明的一些实施例，封装组件26包括片上系统(SoC)管芯、存储器管芯、封装件(包括已经封装的器件管芯)、诸如高带宽存储器(HBM)块的管芯堆叠件等。
根据本发明的一些实施例，封装件的形成处于晶圆级。因此，放置多组封装组件，其中，封装组件组彼此相同。每组均可以包括多个封装组件26，它们可以彼此相同或彼此不同。
封装组件26A和26B可以分别包括半导体衬底28A和28B，其可以是硅衬底。可以在半导体衬底28A和28B上形成集成电路器件(未示出)。集成电路器件可以包括诸如晶体管和二极管的有源器件，并且可以包括或可以不包括诸如电阻器、电容器、电感器等的无源器件。封装组件26A和26B可以分别包括电连接件30A和30B，其可以是金属柱、金属焊盘等。电连接件30A和30B电连接至相应封装组件中的集成电路器件。金属柱30A和30B可以或可以不嵌入在介电层内，介电层可以由聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等形成。例如，图1示出了嵌入在介电层32内的金属柱30A。一些金属柱(诸如30B)可以暴露而不是由介电层覆盖。金属柱30A和30B可选地称为通孔via-0。
接下来，参照图2，将密封剂34密封(有时称为模制)在封装组件26A和26B上。相应的工艺示出为图32所示的工艺流程中的工艺204。密封剂34填充相邻的封装组件26A和26B之间的间隙。密封剂34可以包括模塑料、模塑底部填充物等。密封剂34可以包括基底材料34A(其可以是聚合物、环氧树脂和/或树脂)以及混合在基底材料34A中的填料颗粒34B。填料颗粒34B可以由二氧化硅、氧化铝等形成，并且可以具有球形形状。密封剂34的顶面高于金属柱30A和30B的顶端。
在随后的步骤中，如图3所示，实施诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺。相应的工艺示出为图32所示的工艺流程中的工艺206。降低密封剂34的顶面直至暴露金属柱30A和30B。由于平坦化，金属柱30A和30B的顶面与密封剂34的顶面基本共面。
图4和图5示出了前侧再分布线(RDL)和相应的介电层的形成。参照图4，形成介电层36。相应的工艺示出为图32所示的工艺流程中的工艺208。根据本发明的一些实施例，介电层36由诸如PBO、聚酰亚胺等的聚合物形成。根据本发明的可选实施例，介电层36由诸如氮化硅、氧化硅等的无机材料形成。
然后形成RDL 38以电连接至金属柱30A和30B。相应的工艺也示出为图32所示的工艺流程中的工艺208。根据本发明的一些实施例，RDL 38的形成包括在介电层36中形成开口以露出金属柱30A和30B，形成毯式铜晶种层，在毯式铜晶种层上方形成和图案化掩模层，实施镀以形成RDL 38，去除掩模层，以及蚀刻毯式铜晶种层的未由RDL 38覆盖的部分。RDL 38可以由金属或金属合金形成，金属或金属合金包括钛、铜、铝、钨和/或它们的合金。RDL 38包括位于介电层36中的通孔部分38A和位于介电层36上方的迹线部分38B。迹线部分可包括窄部分和宽部分，其中，宽部分可以用作金属焊盘。RDL 38可以互连封装组件26A和26B。
参照图5，根据本发明的一些实施例，形成更多介电层和相应的RDL层。相应的工艺示出为图32所示的工艺流程中的工艺210。应当理解，取决于设计要求，电介质和RDL的层可以比示出的更多或更少。根据一些实施例，使用选自用于形成介电层36的类似候选材料组中的材料形成介电层40、44和48。RDL 42和46形成为通过RDL 38电连接至封装组件26A和26B。通孔50也形成在介电层48中以连接至RDL 46。可以使用形成RDL 38的类似的材料和方法形成RDL 42和46以及通孔50。可以实施平坦化工艺以使通孔50和介电层48的顶面齐平。介电层36、40、44和48以及RDL 38、42和46以及通孔50组合形成互连结构49。
根据本发明的一些实施例，金属柱30A和30B可选地称为via-0，因为它们是位于互连结构49之下的通孔。RDL 38的通孔部分可选地称为通孔via-1，并且RDL 38的迹线部分可选地称为RDL迹线RDL1。RDL 42的通孔部分可选地称为通孔via-2，并且RDL 42的迹线部分可选地称为RDL迹线RDL2。RDL 46的通孔部分可选地称为通孔via-3，并且RDL 46的迹线部分可选地称为RDL迹线RDL3。通孔50形成在下面的RDL上方并且连接至下面的RDL。相应的工艺示出为图32所示的工艺流程中的工艺212。通孔50可选地称为通孔via-4或顶部通孔。应当理解，通孔和迹线的编号为0、1、2、3和4是为了识别相对位置，并且也可以包括更多或更少的层。
图6示出了电连接件52的形成。相应的工艺示出为图32所示的工艺流程中的工艺214。根据一些实施例，电连接件52包括金属柱52A和位于金属柱52A上方的焊料区域52B。电连接件52的形成可以包括使用镀形成金属柱52A，将焊球放置在金属柱52A的暴露部分上，并且然后回流焊球以形成焊料区域52B。根据本发明的可选实施例，电连接件52的形成包括实施镀步骤以形成金属柱52A并且在金属柱52A上方形成焊料区域，并且然后回流镀焊料区域以形成焊料区域52B。电连接件52和通孔50可以具有或不具有可区分的界面。
金属柱52A也可选地称为凸块下金属(UBM)52A。根据一些实施例，UBM 52A具有明显大于通孔50的水平尺寸HD2的水平尺寸(诸如长度、宽度或直径)HD1。例如，比率HD1/HD2可以大于约3或大于约5，并且可以在约3和约10之间的范围内。水平尺寸HD2也明显大于通孔via-1、via-2和via-3的水平尺寸HD3。例如，比率HD2/HD3可以大于约2或大于约5，并且可以在约3和约10之间的范围内。在整个说明书中，封装组件26A和26B、密封剂34和上面的互连结构49组合称为重建晶圆54。
接下来，参照图7，将重建晶圆54放置在框架56上，其中，电连接件52粘合至框架56中的带55。然后将重建晶圆54与载体20脱离，例如通过对释放膜22投射UV光或激光束，使得释放膜22在UV光或激光束的热量下分解。因此，重建晶圆54与载体20脱离。相应的工艺示出为图32所示的工艺流程中的工艺216。图8中示出了产生的重建晶圆54。然后实施框架切割以去除外部的框架56。可以(或可以不)实施背侧研磨以去除DAF 24(图7)(如果使用)，使得密封剂34的表面与封装组件26A和26B的背面共面。
参照图9，将重建晶圆54放置在切割间隙58上，并且去除带55(图8)。然后将重建晶圆54分割成多个封装件60，它们可以彼此相同。相应的工艺示出为图32所示的工艺流程中的工艺218。图25和图26示出了根据一些实施例的一些封装件60的顶视图。
图10示出了使用封装件60形成的封装件66。例如，封装组件62通过倒装芯片接合与封装件60接合。封装组件62可以是封装衬底、中介层等。封装组件62还可以接合至封装组件64，封装组件64可以是封装衬底、印刷电路板等。
图11示出了根据一些实施例的非接地连接结构70的透视图。非接地连接结构70是图9中的互连结构49的一部分。图6中也示出了其中定位非接地连接结构70的实例。如图11所示，多个RDL迹线RDL1、RDL2和RDL3的层以及多个通孔via-1、via-2和via-3连接至UBM52A以形成非接地连接结构70。术语“非接地”表示通孔via-1、via-2和via-3(作为组)的至少一些与相应上面的通孔via-4垂直未对准(偏离)。根据本发明的一些实施例，两个相邻RDL迹线之间的连接是通过通孔组(而不是单个通孔)，使得产生的结构更能抵抗产生的封装件中的应力。如图11所示，通孔组也称为VG-1、VG-2和VG-3，每个通孔组均包括多个通孔，这些通孔也单独和共同地称为通孔via-1、通孔via-2和通孔via-3。每个通孔组均可以包括2、3、4、5或多个通孔。
如图11所示，可以存在单个通孔via-4，其位于UBM 52A下面并且连接至UBM 52A。RDL迹线RDL3位于通孔via-4下面并且连接至通孔via-4，并且将连接从UBM 52A正下方的区域再分布至不在UBM 52A正下方的区域。通过组VG-3将RDL迹线RDL3连接至RDL迹线RDL2，RDL迹线RDL2位于通孔组VG-2上方并且接触通孔组VG-2。RDL迹线RDL1连接至通孔组VG-2，并且位于通孔组VG-1上方并且接触通孔组VG-1。通过组VG-1可以连接至通孔via-0，via-0是下面的封装组件26的一部分。
根据一些实施例，采用通孔组而不是单个通孔将RDL迹线连接至相应的下面的RDL迹线可以提高可靠性。此外，从UBM 52A正下方的区域转移通孔组VG-1、VG-2和VG-3中的至少一组，或可以是两组或三组，使得应力减小，并且因此减小了由应力引起的迹线变形，并且提高了产生的封装件的可靠性。
图12A示出了根据一些实施例的UBM 52A、通孔via-4、RDL迹线RDL3和通孔via-3(以及对应的通孔组VG-3)的顶视图。通孔组VG-3从UBM 52A和via-4正下方的区域偏离，其中，通孔组VG-3的任何部分都不与UBM 52A和via-4重叠。在整个说明书中，当通孔或通孔组称为从上面的部件“偏离”时，这意味着通孔组的中心在横向方向上偏离一段距离，使得通孔组的中心和上面的部件的中心未与同一垂直线对准。在整个说明书中，术语“中心”也可以意味着“形心”。根据一些实施例，UBM 52A具有细长形状，并且中心52A’从via-4的中心51偏离。此外，箭头57指向相应的扇出封装件60的中心的方向，并且中心52A’比通孔via-4的中心51偏离相应的扇出封装件60是中心。RDL迹线RDL3可以具有孔72，孔72形成为减小RDL的密度，并且孔72也是脱气孔。虽然示出了一个孔72，但是可以在RDL迹线RDL3中形成更多孔，这些孔填充有相应介电层的介电材料。孔72的形状可以是圆形、矩形或其它形状。通孔Via-3可以与环绕孔72的圆对准。
图12B示出了根据一些实施例的UBM 52A、RDL迹线RDL2和通孔via-2(以及对应的通孔组VG-2)的顶视图。通孔组VG-2也从UBM 52A正下方的区域偏离，其中，通孔组VG-2的任何部分都不与UBM 52A和通孔via-4重叠。
图12C示出了根据一些实施例的UBM 52A、RDL迹线RDL1和通孔via-1(以及对应的通孔组VG-1)的顶视图。通孔组VG-1可以位于UBM 52A正下方的区域中，并且可以或可以不位于通孔via-4正下方的区域中。RDL迹线RDL1可以具有孔73，其为脱气孔。
如图12A、图12B和图12C所示，非接地连接结构70具有与UBM 52A和通孔via-4垂直未对准(偏离)的至少一个通孔组(诸如图12B中的VG-2和VG-3)。根据一些实施例，通孔组VG-1可以与上面的通孔组VG-2未对准或重叠，并且通孔组VG-2可以与上面的通孔组VG-3未对准或重叠。在整个说明书中，如果第一通孔组的轮廓区域具有与第二通孔组的部分重叠的至少部分，则第一通孔组称为与第二通孔组重叠，其中，参照图13B、图13C和图13D来说明“轮廓区域”。例如，如图12A所示，通孔组VG-3与通孔组VG-2重叠。根据本发明的一些实施例，当第一通孔组与第二通孔组重叠时，第一通孔组中的通孔可以被设计为与第二通孔组中的通孔未对准。例如，图12B中示出了通孔via-2，以表明通孔组VG-3与通孔组VG-2重叠，但是通孔via-3与通孔via-2未对准。根据一些实施例，通孔via-2对准的环比通孔via-3对准的环更小(或更大)，使得通孔via-2未与对应的通孔via-3重叠。根据其它实施例，如图12B所示，通孔组VG-2相对于通孔组VG-3围绕通孔组VG-2和VG-3的中心76旋转，使得下面的通孔(诸如通孔via-2)未与上面的通孔(诸如via-3)重叠。此外，通孔via-2关于中心76旋转对称，这意味着它们与具有76作为其形心的相同圆对准，并且它们具有相等的距离。通孔via-3也可以关于中心76旋转对称。根据一些实施例，没有任何通孔via-1、via-2和via-3与相同的非接地连接结构70中的任何其它通孔重叠。根据其它实施例，没有任何通孔via-1、via-2和via-3与直接上面的通孔重叠，并且没有任何通孔与直接下面的通孔重叠。然而，如果两层通孔不在紧邻的通孔层中，则上面的通孔可以或可以不与下面的通孔重叠。例如，通孔via-3可能不与通孔via-2重叠，但可能与或可能不与通孔via-1重叠。
每个通孔或通孔组占据轮廓区域，如图13A、图13B、图13C和图13D所示，并且通孔组的轮廓区域是通孔组中的通孔和连接通孔的多边形占据的区域。例如，图13A示出了由五个通孔的通孔组占据的轮廓区域74，图13C示出了由两个通孔的通孔组占据的轮廓区域74，并且图13D示出了由六个通孔的通孔组占据的轮廓区域74。图13B示出了由单个通孔占据的轮廓区域74。根据本发明的一些实施例，如图13A的顶视图所示，通孔组VG-3的轮廓区域74的中心从通孔via-4的中心偏离。此外，轮廓区域74不具有与通孔via-4重叠的任何部分。将通孔组VG-3的轮廓区域74的中心从通孔via-4的中心偏离，但仍允许via-4与轮廓区域74的一部分重叠可以在产生的结构中生成高应力。因此，根据一些实施例，通孔组不会从via-4偏离，这意味着通孔组(诸如VG-3)的中心垂直对准通孔via-4的中心，或通孔组偏离的足够远，使得via-4不会与通孔组的轮廓区域的任何部分重叠。
图14A和图15至图18示出了非接地连接结构70的一些部分的截面图，其中，通孔组VG-3从通孔via-4和UBM 52A偏离。其它通孔组VG-2和VG-1可以与或可以不与通孔via-4重叠。例如，在图14A中，通孔via-3和对应的通孔组VG-3从via-4偏离。通孔组VG-2与通孔组VG-3重叠。通孔via-1(通孔组VG-1)可以与通孔via-4和/或UBM 52A重叠。
图14B、图14C和图14D示出了图14A所示的RDL迹线RDL3、RDL2和RDL1以及通孔via-4、via-3、via-2和via-1。顶视图也可以应用于图15至图18所示的实施例。根据一些实施例，UBM 52A具有横向尺寸(宽度或长度)W1，并且RDL迹线RDL3、RDL2和RDL1分别具有长度L3、L2和L1。根据一些实施例，长度L1、L2和L3的每个均小于2倍P的平方根，其中，P是UBM 52A的间距，如图14E所示。孔72(图14B)和73(图14D)的尺寸小于UBM 52A的横向尺寸W1(图14B)。
图15示出了从通孔via-4偏离的通孔via-3和对应的通孔组VG-3。通孔组VG-2也从通孔组VG-3偏离。通孔组VG-2与上面的通孔组VG-3垂直偏离，但是通孔组VG-2与通孔组VG-1重叠。通孔组VG-1和通孔组VG-2可以与通孔via-4和/或UBM 52A重叠。
图16示出了从via-4偏离的通孔via-3和对应的通孔组VG-3。通孔组VG-2和VG-1也从通孔组通孔via-4偏离。通孔组VG-3与通孔组VG-2和VG-1重叠。根据本发明的一些实施例，通孔via-1与上面的通孔via-2垂直偏离，其进一步与上面的通孔via-3垂直偏离。
图17示出了从via-4偏离的通孔via-3和对应的通孔组VG-3。通孔组VG-2与via-4和/或UBM 52A重叠。通孔via-1和通孔组VG-1不与任何通孔组VG-2、通孔组VG-3、通孔via-4和UBM 52A重叠。
图18示出了从via-4偏离的通孔via-3和对应的通孔组VG-3。通孔组VG-2也从通孔组VG-3偏离。通孔组VG-1不与任何通孔组VG-2和通孔组VG-3重叠。通孔组VG-2和VG-1可以与通孔via-4和UBM 52A部分重叠(未在图18中示出)。
图19A、图19B、图19C和图19D示出了根据一些实施例的非接地连接结构70的顶视图和截面图，其中，通孔组VG-2从相应的通孔via-4偏离。其它通孔组VG-3和VG-1可以或可以不与相应的通孔via-4重叠。图19A示出了顶视图，其示出了通孔via-2和对应的通孔组VG-2从通孔via-4和UBM 52A偏离。图19B示出了通孔组VG-3和通孔组VG-1与UBM 52A(并且可能的通孔via-4)重叠。图19C示出了通孔组VG-3与UBM 52A(并且可能的通孔via-4)重叠，而通孔组VG-1与通孔组VG-2重叠(其中，通孔via-1与通孔via-2未垂直对准)。图19D示出了通孔组VG-3与UBM 52A(以及可能的通孔via-4)重叠，而通孔组VG-1不与通孔组VG-3和通孔组VG-2中的任何一个重叠。
图20A、图20B和图20C示出了根据一些实施例的RDL迹线RDL3、RDL2和RDL1以及通孔via-4、via-3、via-2和via-1，其可以对应于图19A和图19B所示的结构。根据一些实施例，UBM 52A(图20B)具有横向尺寸W1，并且RDL迹线RDL3、RDL2和RDL1分别具有长度L3’、L2’和L1’。根据一些实施例，长度L1’、L2’和L3’的每个均小于2倍P的平方根，其中，P是UBM 52A的间距，如图14E所示。孔72(图20A)和73(图20C)的尺寸小于UBM 52A的横向尺寸W1(图20B)。
图21A、图21B和图21C示出了根据一些实施例的非接地连接结构70的顶视图和截面图，其中，通孔组VG-1从相应的通孔via-4偏离。其它通孔组VG-2和VG-3可以与或可以不与通孔via-4重叠。图21A示出了顶视图，其示出了通孔via-1和对应的通孔组VG-1从通孔via-4和UBM 52A偏离。图21B示出了通孔组VG-3和VG-2与UBM 52A(以及可能的通孔via-4)重叠。类似地，通孔via-3与通孔via-2未对准。图21C示出了通孔组VG-3与UBM 52A(以及可能的通孔via-4)重叠，而通孔组VG-1和VG-2都从通孔via-4和UBM 52A偏离，并且通孔组VG-1与通孔组VG-2偏离。
图22A、图22B和图22C示出了根据一些实施例的RDL迹线RDL3、RDL2和RDL1以及通孔via-4、via-3、via-2和via-1，其可以对应于图21A和图21B所示的结构。根据一些实施例，UBM 52A具有横向尺寸W1(图22C)，并且RDL迹线RDL3、RDL2和RDL1分别具有长度L3”、L2”和L1”。根据一些实施例，长度L3”大于长度L2”。根据一些实施例，长度L1”、L2”和L3”的每个均小于2倍P的平方根，其中，P是UBM 52A的间距，如图14E所示。孔72(图22A)和73(图22C)的尺寸小于UBM 52A的横向尺寸W1(图22C)。
图23示出了根据一些实施例的接地连接结构70’的透视图。这些实施例也具有减小应力的功能。如图23所示，多个RDL迹线RDL1、RDL2和RDL3层以及多个复合通孔via-1、via-2和via-3连接至UBM 52A。术语“接地”表示所有RDL迹线RDL1、RDL2和RDL3以及通孔组VG-1、VG-2和VG-3的中心与通孔via-4的中心垂直对准。然而，通孔via-1和via-2不分别与直接上面的通孔via-2和via-3重叠。通孔via-1可以与通孔via-3重叠，或可选地，通孔via-1可以与通孔via-3未对准。
图24A、图24B和图24C示出了根据一些实施例的RDL迹线RDL3、RDL2和RDL1以及通孔via-4、via-3、via-2和via-1的顶视图，其可以对应于图23所示的结构。根据一些实施例，RDL迹线RDL3、RDL2和RDL1具有圆形顶视图形状。UBM 52A具有横向尺寸W1，并且RDL迹线RDL3、RDL2和RDL1分别具有直径D3、D2和D1。根据一些实施例，直径D1、D2和D3的每个均在约0.5W1和约1.5W1之间的范围内。
图25和图26示出了根据一些实施例的封装件60的顶视图(布局)。根据一些实施例，封装组件26A是大封装组件，其顶视区域可以大于封装件60的顶视区域的约60％。应当理解，互连结构49(图9)包括承受较高应力的高应力区域和承受较低应力的低应力区域。高应力区域包括区域126A，其与封装组件26A的外围区域(包括拐角区域和边缘区域)重叠。根据一些实施例，封装组件26A的外围区域是从封装组件26A的边缘测量并且具有宽度Wa1和Wa2的区域，宽度Wa1和Wa2分别小于对应宽度Wb1和Wb2的约20％。低应力部分包括区域126B，其位于封装组件26B的中心部分正上方。低应力部分也可以包括位于封装组件26B正上方的部分，由于它们相对小的区域而引入低应力。一些高应力区域126A和低应力区域126B也在图9中示意性地示出。根据一些实施例，在高应力区域中形成非接地连接结构70(图11)和接地连接结构70’(图23)。在低应力区域126B中，可以以任何组合形成非接地连接结构70(图11)、接地连接结构70’，以及单通孔连接结构70”(图27)。
在图27中，可以存在将RDL迹线连接至下面的RDL迹线的单个通孔。此外，通孔via-3可以从通孔via-4偏离，但是偏离距离可以或可以不足够大，并且通孔via-3可以或可以不由UBM 52A和/或通孔via-4覆盖。因此，与非接地连接结构70和接地连接结构70’相比，单通孔连接结构70”承受更高的应力(并且具有更低的可靠性)。然而，由于单通孔连接结构70”形成在低应力区域中，因此其可靠性可能仍能够满足设计规范。单通孔连接结构70”不会形成在高应力区域126A(图25和图26)中。单通孔连接结构70”在设计上提供了更大的灵活性，并且由于单通孔连接可以占用小的芯片面积。
图26示出了根据一些实施例的封装件26的顶视图。这些实施例类似于图25中的实施例，除了形成更多的封装组件26B之外。类似地，标记了高应力区域126A，其中形成了非接地连接结构70(图11)和接地连接结构70’(图23)。在高应力区域126A中没有形成单通孔连接结构70”。非接地连接结构70、接地连接结构70’和单通孔连接结构70”可以以任何组合形成在低应力区域126B中。
进一步参照图25和图26，由于非接地连接结构70具有良好的可靠性，因此该区域中的应力最大，诸如封装组件26A的拐角区域上方的区域具有非接地性连接结构70但可以不具有单通孔连接结构70”。封装组件26A的边缘部分(不包括拐角区域)正上方的区域可以包括非接地连接结构70和/或接地连接结构70’，但是没有单通孔连接结构70”。
图28至图31示出了根据一些实施例的封装件60的一些部分的截面图，其中，示出了连接结构70和至封装组件26A和26B的对应连接。在图28和图31中，存在与多个通孔via-1连接的单个通孔via-0。在图29和图30中，存在与多个通孔via-1连接的多个通孔via-0。应当理解，在参照图11至图24A/图24B/图24C讨论的每个实施例所示的实施例中可以采用图28至图31所示的结构。图28和图29所示的封装件可以采用图1至图10所示的工艺形成。可以通过首先形成互连结构49作为衬底，并且然后通过倒装芯片接合将封装组件26A和26B接合至已经形成的互连结构49来形成图30和图31所示的封装件，其中，焊料区域82用于接合。然后可以施加底部填充物84，并且可以分配密封剂34以形成图30和图31所示的结构。
根据本发明的一些实施例，连接结构70(图11)、70’(图23)和70”(图27)是单分支连接结构，这意味着RDL迹线RDL1、RDL2和RDL3没有侧向连接至任何其它导电部件。换句话说，每个导电迹线RDL1、RDL2和RDL3的所有侧壁都与介电材料接触。因此，流过via-4的电流将等于流过via-0的电流。
在以上示出的实施例中，根据本发明的一些实施例讨论了一些工艺和部件。也可以包括其它部件和工艺。例如，可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括，例如，在再分布层中或衬底上形成的测试焊盘(允许3D封装件或3DIC的测试)、探针和/或探针卡的使用等。可以对中间结构以及最终结构实施验证测试。此外，本文所公开的结构和方法可以与结合已知良好管芯的中间验证的测试方法结合使用，以增加良率并且降低成本。
本发明的实施例具有一些有利特征。通过形成用于互连RDL迹线的通孔组(而不是单通孔连接)，提高了对应连接结构的可靠性。此外，通过在高应力区域采用非接地结构和接地结构，可以释放应力，并且因此进一步提高了连接结构的可靠性。
根据本发明的一些实施例，方法包括将封装组件放置在载体上方；将封装组件密封在密封剂中；以及在封装组件上方形成电连接至封装组件的第一连接结构，其中，形成第一连接结构包括：在封装组件上方形成电连接至封装组件的第一通孔组；在第一通孔组上方形成接触第一通孔组的第一导电迹线；在第一导电迹线上面形成接触第一导电迹线的第二通孔组，其中，第一通孔组和第二通孔组的每个均包括多个通孔；在第二通孔组上方形成接触第二通孔组的第二导电迹线；在第二导电迹线上面形成接触第二导电迹线的顶部通孔；以及在顶部通孔上方形成接触顶部通孔的UBM。在实施例中，该方法还包括在UBM上方形成接触UBM的焊料区域。在实施例中，第一通孔组和第二通孔组中的一个的轮廓区域从顶部通孔垂直地偏离。在实施例中，形成第一通孔组包括：在封装组件和密封剂上方形成介电层；在介电层中形成开口以暴露下面的导电部件；以及通过镀工艺形成第一导电迹线和第一通孔组。在实施例中，第一通孔组电连接至封装组件中的表面通孔，并且顶部通孔与表面通孔重叠，并且第一通孔组和第二通孔组中的一个的轮廓区域进一步与顶部通孔和表面通孔垂直未对准。在实施例中，该方法还在第一通孔组下面形成接触第一通孔组的第三导电迹线；以及在第三导电迹线下面形成接触第三导电迹线的第三通孔组，其中，第三通孔组进一步位于封装组件中的表面通孔上面并且接触封装组件中的表面通孔。在实施例中，第一通孔组的中心与第二通孔组的中心垂直对准，并且第一通孔组中的通孔与第二通孔组中的通孔垂直未对准。在实施例中，第一连接结构与封装组件的外围区域重叠，并且该方法还包括形成与封装组件的中心区域重叠的第二连接结构，并且形成第二连接结构形成在封装组件上方形成电连接至封装组件的单个通孔；在单个通孔上面形成接触单个通孔的附加导电迹线；在附加导电迹线上面形成接触附加导电迹线的附加顶部通孔；以及在附加顶部通孔上方形成接触附加顶部通孔的附加UBM，其中，单个通孔的中心从附加顶部通孔垂直偏离。在实施例中，附加顶部通孔包括与附加UBM重叠的部分。
根据本发明的一些实施例，方法包括将第一封装组件和第二封装组件放置在载体上方，其中，第一封装组件具有比第二封装组件更大的顶视图区域，并且第一封装组件包括电连接件；将第一封装组件和第二封装组件密封在密封剂中；在第一封装组件的外围区域上方形成第一连接结构，其中，第一连接结构电连接至电连接件，并且第一连接结构包括第一金属柱；第一顶部通孔，位于第一金属柱下面并且电连接至第一金属柱；第一导电迹线，位于第一顶部通孔下面；第一通孔组，位于第一导电迹线下面并且接触第一导电迹线，其中，第一通孔组包括多个第一通孔，并且第一通孔组具有第一轮廓区域；第二导电迹线，位于第一通孔组下面并且电连接至第一通孔组；以及第二通孔组，位于第二导电迹线下面并且接触第二导电迹线，其中，第二通孔组包括多个第二通孔，并且第二通孔组具有与第一轮廓区域重叠的第二轮廓区域。在实施例中，该方法还包括锯切穿过密封剂以形成离散封装件，其中，第一封装组件的第一顶视图区域大于离散封装件的顶视图区域的约60％。在实施例中，多个第一通孔与多个第二通孔垂直未对准。在实施例中，第一轮廓区域的中心与第二轮廓区域的中心重叠。在实施例中，该方法还包括形成与第二封装组件中的附加电连接件重叠并且电连接至附加电连接件的附加连接结构，其中，附加连接结构使用单个通孔来电连接附加连接结构中的两个导电迹线。在实施例中，在第一连接结构的顶视图中，多个第一通孔和多个第二通孔对准相同的圆环，并且多个第一通孔与多个第二通孔垂直未对准。
根据本发明的一些实施例，封装件包括UBM；顶部通孔，位于UBM下面并且电连接至UBM；第一导电迹线，位于顶部通孔下面并且电连接至顶部通孔；第一通孔组，位于第一导电迹线下面并且接触第一导电迹线，其中，第一通孔组包括多个第一通孔，并且第一通孔组具有第一轮廓区域；第二导电迹线，位于第一通孔组下面并且电连接至第一通孔组；以及第二通孔组，位于第二导电迹线下面并且接触第二导电迹线，第二通孔组包括多个第二通孔，并且第二通孔组具有与第一轮廓区域重叠的第二轮廓区域，并且多个第一通孔与多个第二通孔垂直未对准。在实施例中，封装件还包括器件管芯，该器件管芯包括金属柱；密封剂，将器件管芯密封在其中；以及介电层，与密封剂和金属柱重叠并且接触，其中，金属柱位于多个第二通孔的底面下面并且接触多个第二通孔的底面。在实施例中，金属柱与UBM重叠。在实施例中，UBM与器件管芯的外围区域重叠。在实施例中，多个第一通孔对称于第一垂直中心线分配，并且多个第二通孔对称于第二垂直中心线分配，并且第一垂直中心线和第二垂直中心线垂直未对准。
根据本发明的实施例，提供了一种形成封装件的方法，包括：将封装组件放置在载体上方；将所述封装组件密封在密封剂中；以及在所述封装组件上方形成电连接至所述封装组件的第一连接结构，其中，形成所述第一连接结构包括：在所述封装组件上方形成电连接至所述封装组件的第一通孔组；在所述第一通孔组上方形成接触所述第一通孔组的第一导电迹线；在所述第一导电迹线上面形成接触所述第一导电迹线的第二通孔组，其中，所述第一通孔组和所述第二通孔组的每个均包括多个通孔；在所述第二通孔组上方形成接触所述第二通孔组的第二导电迹线；在所述第二导电迹线上面形成顶部通孔；以及在所述顶部通孔上方形成接触所述顶部通孔的凸块下金属(UBM)。
根据本发明的实施例，还包括在所述凸块下金属上方形成接触所述凸块下金属的焊料区域。
根据本发明的实施例，所述第一通孔组和所述第二通孔组中的一个的轮廓区域从所述顶部通孔垂直地偏离。
根据本发明的实施例，形成所述第一通孔组包括：在所述封装组件和所述密封剂上方形成介电层；在所述介电层中形成开口以暴露下面的导电部件；以及在所述开口中形成第一通孔组。
根据本发明的实施例，所述第一通孔组电连接至所述封装组件中的表面通孔，并且所述顶部通孔与所述表面通孔重叠，并且所述第一通孔组和所述第二通孔组中的一个的轮廓区域进一步与所述顶部通孔和所述表面通孔垂直未对准。
根据本发明的实施例，所述方法还包括：在所述第一通孔组下面形成接触所述第一通孔组的第三导电迹线；以及在所述第三导电迹线下面形成接触所述第三导电迹线的第三通孔组，其中，所述第三通孔组进一步位于所述封装组件中的表面通孔上面并且接触所述封装组件中的表面通孔。
根据本发明的实施例，所述第一通孔组的中心与所述第二通孔组的中心垂直对准，并且所述第一通孔组中的通孔与所述第二通孔组中的通孔垂直未对准。
根据本发明的实施例，所述第一连接结构与所述封装组件的外围区域重叠，并且所述方法还包括形成与所述封装组件的中心区域重叠的第二连接结构，并且形成所述第二连接结构包括：在所述封装组件上方形成电连接至所述封装组件的单个通孔；在所述单个通孔上面形成接触所述单个通孔的附加导电迹线；在所述附加导电迹线上面形成接触所述附加导电迹线的附加顶部通孔；以及在所述附加顶部通孔上方形成接触所述附加顶部通孔的附加凸块下金属，其中，所述单个通孔的中心从所述附加顶部通孔垂直偏离。
根据本发明的实施例，所述附加顶部通孔包括与所述附加凸块下金属重叠的部分。
根据本发明的实施例，还提供了一种形成封装件的方法，包括：将第一封装组件和第二封装组件放置在载体上方，其中，所述第一封装组件具有比所述第二封装组件更大的顶视图区域，并且所述第一封装组件包括电连接件；将所述第一封装组件和所述第二封装组件密封在密封剂中；在所述第一封装组件的外围区域上方形成第一连接结构，其中，所述第一连接结构电连接至所述电连接件，并且所述第一连接结构包括：第一金属柱；第一顶部通孔，位于所述第一金属柱下面并且电连接至所述第一金属柱；第一导电迹线，位于所述第一顶部通孔下面；第一通孔组，位于所述第一导电迹线下面并且接触所述第一导电迹线，其中，所述第一通孔组包括多个第一通孔，并且所述第一通孔组具有第一轮廓区域；第二导电迹线，位于所述第一通孔组下面并且电连接至所述第一通孔组；以及第二通孔组，位于所述第二导电迹线下面并且接触所述第二导电迹线，其中，所述第二通孔组包括多个第二通孔，并且所述第二通孔组具有与所述第一轮廓区域重叠的第二轮廓区域。
根据本发明的实施例，还包括锯切穿过所述密封剂以形成离散封装件，其中，所述第一封装组件的第一顶视图区域大于所述离散封装件的顶视图区域的60％。
根据本发明的实施例，所述多个第一通孔与所述多个第二通孔垂直未对准。
根据本发明的实施例，所述第一轮廓区域的中心与所述第二轮廓区域的中心重叠。
根据本发明的实施例，还包括形成与所述第二封装组件中的附加电连接件重叠并且电连接至所述附加电连接件的附加连接结构，其中，所述附加连接结构使用单个通孔来电连接所述附加连接结构中的两个导电迹线。
根据本发明的实施例，在所述第一连接结构的顶视图中，所述多个第一通孔和所述多个第二通孔对准相同的圆环，并且所述多个第一通孔与所述多个第二通孔垂直未对准。
根据本发明的实施例，还提供了一种封装件，包括：凸块下金属(UBM)；顶部通孔，位于所述凸块下金属下面并且电连接至所述凸块下金属；第一导电迹线，位于所述顶部通孔下面并且电连接至所述顶部通孔；第一通孔组，位于所述第一导电迹线下面并且接触所述第一导电迹线，其中，所述第一通孔组包括多个第一通孔，并且所述第一通孔组具有第一轮廓区域；第二导电迹线，位于所述第一通孔组下面并且电连接至所述第一通孔组；以及第二通孔组，位于所述第二导电迹线下面并且接触所述第二导电迹线，其中，所述第二通孔组包括多个第二通孔，并且所述第二通孔组具有与所述第一轮廓区域重叠的第二轮廓区域，并且所述多个第一通孔与所述多个第二通孔垂直未对准。
根据本发明的实施例，还包括：器件管芯，包括金属柱；密封剂，将所述器件管芯密封在所述密封剂中；以及介电层，与所述密封剂和所述金属柱重叠并且接触，其中，所述金属柱位于所述多个第二通孔的底面下面并且接触所述多个第二通孔的底面。
根据本发明的实施例，所述金属柱与所述凸块下金属重叠。
根据本发明的实施例，所述凸块下金属与所述器件管芯的外围区域重叠。
根据本发明的实施例，所述多个第一通孔对称于第一垂直中心线分配，并且所述多个第二通孔对称于第二垂直中心线分配，并且所述第一垂直中心线和所述第二垂直中心线垂直未对准。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应当理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (20)

1.一种形成封装件的方法，包括：
将封装组件放置在载体上方；
将所述封装组件密封在密封剂中；以及
在所述封装组件上方形成电连接至所述封装组件的第一连接结构，其中，形成所述第一连接结构包括：
在所述封装组件上方形成电连接至所述封装组件的第一通孔组，其中，所述第一通孔组包括第一多个通孔，所述第一多个通孔与所述封装组件的单个通孔直接接触；
在所述第一通孔组上方形成第一导电迹线，其中，所述第一导电迹线的第一底部表面物理接触每个所述第一多个通孔的第一顶部表面；
在所述第一导电迹线上面形成第二通孔组，其中，所述第二通孔组包括第二多个通孔，并且其中每个所述第二多个通孔的第二底部表面物理接触所述第一导电迹线的第二顶部表面；
在所述第二通孔组上方形成物理接触所述第二通孔组的第二导电迹线；
在所述第二导电迹线上面形成顶部通孔；以及
在所述顶部通孔上方形成接触所述顶部通孔的凸块下金属(UBM)，
所述第一连接结构的每个导电迹线均没有侧向连接至任何其它导电部件。
2.根据权利要求1所述的方法，还包括在所述凸块下金属上方形成接触所述凸块下金属的焊料区域，
所述凸块下金属具有细长形状，并且所述凸块下金属的中心从所述顶部通孔的中心偏离，并且所述凸块下金属的中心比所述顶部通孔的中心偏离所述封装件的中心。
3.根据权利要求1所述的方法，其中，所述第一通孔组和所述第二通孔组中的一个的轮廓区域从所述顶部通孔垂直地偏离。
4.根据权利要求1所述的方法，其中，形成所述第一通孔组包括：
在所述封装组件和所述密封剂上方形成介电层；
在所述介电层中形成开口以暴露下面的导电部件；以及
在所述开口中形成第一通孔组。
5.根据权利要求1所述的方法，其中，所述第一通孔组电连接至所述封装组件中的表面通孔，并且所述顶部通孔与所述表面通孔重叠，并且所述第一通孔组和所述第二通孔组中的一个的轮廓区域进一步与所述顶部通孔和所述表面通孔垂直未对准。
6.根据权利要求5所述的方法，其中，所述方法还包括：
在所述第一通孔组下面形成接触所述第一通孔组的第三导电迹线；以及
在所述第三导电迹线下面形成接触所述第三导电迹线的第三通孔组，其中，所述第三通孔组进一步位于所述封装组件中的表面通孔上面并且接触所述封装组件中的表面通孔。
7.根据权利要求1所述的方法，其中，所述第一通孔组的中心与所述第二通孔组的中心垂直对准，并且所述第一通孔组中的通孔与所述第二通孔组中的通孔垂直未对准。
8.根据权利要求1所述的方法，其中，所述第一连接结构与所述封装组件的外围区域重叠，并且所述方法还包括形成与所述封装组件的中心区域重叠的第二连接结构，并且形成所述第二连接结构包括：
在所述封装组件上方形成电连接至所述封装组件的单个通孔；
在所述单个通孔上面形成接触所述单个通孔的附加导电迹线；
在所述附加导电迹线上面形成接触所述附加导电迹线的附加顶部通孔；以及
在所述附加顶部通孔上方形成接触所述附加顶部通孔的附加凸块下金属，其中，所述单个通孔的中心从所述附加顶部通孔垂直偏离。
9.根据权利要求8所述的方法，其中，所述附加顶部通孔包括与所述附加凸块下金属重叠的部分。
10.一种形成封装件的方法，包括：
将第一封装组件和第二封装组件放置在载体上方，其中，所述第一封装组件具有比所述第二封装组件更大的顶视图区域，并且所述第一封装组件包括电连接件；
将所述第一封装组件和所述第二封装组件密封在密封剂中；
在所述第一封装组件的外围区域上方形成第一连接结构，其中，所述第一连接结构中的多个通孔电连接至所述电连接件中的单个通孔，并且所述第一连接结构包括：
第一金属柱；
第一顶部通孔，位于所述第一金属柱下面并且电连接至所述第一金属柱；
第一导电迹线，位于所述第一顶部通孔下面；
第一通孔组，位于所述第一导电迹线下面并且接触所述第一导电迹线，其中，所述第一通孔组包括多个第一通孔，所述多个第一通孔的每个与所述第一导电迹线物理接触，并且所述第一通孔组具有第一轮廓区域；
第二导电迹线，位于所述第一通孔组下面并且电连接至所述第一通孔组；以及
第二通孔组，位于所述第二导电迹线下面，其中，所述第二通孔组包括多个第二通孔，所述多个第二通孔的每个与所述第二导电迹线物理接触，并且所述第二通孔组具有与所述第一轮廓区域重叠的第二轮廓区域，
所述第一连接结构的每个导电迹线均没有侧向连接至任何其它导电部件。
11.根据权利要求10所述的方法，还包括锯切穿过所述密封剂以形成离散封装件，其中，所述第一封装组件的第一顶视图区域大于所述离散封装件的顶视图区域的60％。
12.根据权利要求10所述的方法，其中，所述多个第一通孔与所述多个第二通孔垂直未对准。
13.根据权利要求12所述的方法，其中，所述第一轮廓区域的中心与所述第二轮廓区域的中心重叠。
14.根据权利要求10所述的方法，还包括形成与所述第二封装组件中的附加电连接件重叠并且电连接至所述附加电连接件的附加连接结构，其中，所述附加连接结构使用单个通孔来电连接所述附加连接结构中的两个导电迹线。
15.根据权利要求10所述的方法，其中，在所述第一连接结构的顶视图中，所述多个第一通孔和所述多个第二通孔对准相同的圆环，并且所述多个第一通孔与所述多个第二通孔垂直未对准。
16.一种封装件，包括：
第一封装组件，在所述第一封装组件的外围区域上方形成第一连接结构，所述第一连接结构中的多个通孔电连接至所述第一封装组件的单个通孔，
所述第一连接结构包括：
凸块下金属(UBM)；
顶部通孔，位于所述凸块下金属下面并且电连接至所述凸块下金属；
第一导电迹线，位于所述顶部通孔下面并且电连接至所述顶部通孔；
第一通孔组，位于所述第一导电迹线下面并且接触所述第一导电迹线，其中，所述第一通孔组包括多个第一通孔，所述多个第一通孔的每个与所述第一导电迹线物理接触，并且所述第一通孔组具有第一轮廓区域；
第二导电迹线，位于所述第一通孔组下面并且电连接至所述第一通孔组；以及
第二通孔组，位于所述第二导电迹线下面并且接触所述第二导电迹线，其中，所述第二通孔组包括多个第二通孔，所述多个第二通孔的每个与所述第二导电迹线物理接触，并且所述第二通孔组具有与所述第一轮廓区域重叠的第二轮廓区域，并且所述多个第一通孔与所述多个第二通孔垂直未对准，
所述第一连接结构的每个导电迹线均没有侧向连接至任何其它导电部件。
17.根据权利要求16所述的封装件，还包括：
器件管芯，包括金属柱；
密封剂，将所述器件管芯密封在所述密封剂中；以及
介电层，与所述密封剂和所述金属柱重叠并且接触，其中，所述金属柱位于所述多个第二通孔的底面下面并且接触所述多个第二通孔的底面，
其中，所述金属柱与所述凸块下金属重叠。
18.根据权利要求16所述的封装件，还包括：
器件管芯，包括金属柱；
密封剂，将所述器件管芯密封在所述密封剂中；以及
介电层，与所述密封剂和所述金属柱重叠并且接触，其中，所述金属柱位于所述多个第二通孔的底面下面并且接触所述多个第二通孔的底面，
其中，所述凸块下金属与所述器件管芯的外围区域重叠。
19.根据权利要求16所述的封装件，其中，所述多个第一通孔对称于第一垂直中心线分配，并且所述多个第二通孔对称于第二垂直中心线分配，并且所述第一垂直中心线和所述第二垂直中心线垂直未对准。
20.一种封装件，包括：
第一封装组件，在所述第一封装组件的外围区域上方形成第一连接结构，所述第一连接结构中的多个通孔电连接至所述第一封装组件的单个导电部件，
所述第一连接结构包括：
凸块下金属(UBM)；
顶部通孔，位于所述凸块下金属下面并且电连接至所述凸块下金属；
第一导电迹线，位于所述顶部通孔下面并且电连接至所述顶部通孔；
第一通孔组，位于所述第一导电迹线下面并且接触所述第一导电迹线，其中，所述第一通孔组包括多个第一通孔，并且所述第一通孔组具有第一轮廓区域；
第二导电迹线，位于所述第一通孔组下面并且电连接至所述第一通孔组；以及
第二通孔组，位于所述第二导电迹线下面并且接触所述第二导电迹线，其中，所述第二通孔组包括多个第二通孔，并且所述第二通孔组具有与所述第一轮廓区域重叠的第二轮廓区域，并且所述多个第一通孔与所述多个第二通孔垂直未对准，
所述第一连接结构的每个导电迹线均没有侧向连接至任何其它导电部件；
所述第一封装组件包括：
器件管芯，包括金属柱；
密封剂，将所述器件管芯密封在所述密封剂中；以及
介电层，与所述密封剂和所述金属柱重叠并且接触，其中，所述金属柱位于所述多个第二通孔的底面下面并且接触所述多个第二通孔的底面，
其中，所述第二导电迹线包括交叉的第一部分和第二部分，一部分所述多个第二通孔位于所述第一部分下面，另一部分所述多个第二通孔位于所述第二部分下面。
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