CN110544650A - 半导体装置的制造方法和基板处理装置 - Google Patents

半导体装置的制造方法和基板处理装置 Download PDF

Info

Publication number
CN110544650A
CN110544650A CN201910445691.9A CN201910445691A CN110544650A CN 110544650 A CN110544650 A CN 110544650A CN 201910445691 A CN201910445691 A CN 201910445691A CN 110544650 A CN110544650 A CN 110544650A
Authority
CN
China
Prior art keywords
oxide film
semiconductor device
manufacturing
film
polymer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910445691.9A
Other languages
English (en)
Other versions
CN110544650B (zh
Inventor
山口达也
野泽秀二
佐藤渚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of CN110544650A publication Critical patent/CN110544650A/zh
Application granted granted Critical
Publication of CN110544650B publication Critical patent/CN110544650B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67138—Apparatus for wiring semiconductor or solid state device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67115—Apparatus for thermal treatment mainly by radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
    • H01L2221/1047—Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Photovoltaic Devices (AREA)
  • Multi-Process Working Machines And Systems (AREA)

Abstract

本发明涉及半导体装置的制造方法和基板处理装置。本发明提供一种能确保层间绝缘膜的机械强度的技术。本公开的一方式的半导体装置的制造方法包括如下工序：填埋工序、氧化膜形成工序和脱离工序。填埋工序中，以具有脲键的聚合物填埋形成于基板上的孔隙。氧化膜形成工序中，在前述基板上形成氧化膜。脱离工序中，使前述聚合物解聚，由此使解聚后的前述聚合物通过前述氧化膜而从前述孔隙脱离。

Description

半导体装置的制造方法和基板处理装置
技术领域
公开的实施方式涉及半导体装置的制造方法和基板处理装置。
背景技术
以往，多层化了的半导体装置中，作为减小层间绝缘膜的相对介电常数的方法，已知有如下方法：在上述层间绝缘膜中填埋基板上的凹部时，利用作为填埋不良而形成的孔隙(参照专利文献1)。
现有技术文献
专利文献
专利文献1：日本特开2012-54307号公报
发明内容
发明要解决的问题
本公开提供一种能确保层间绝缘膜的机械强度的技术。
用于解决问题的方案
本公开的一方式的半导体装置的制造方法包括：填埋工序、氧化膜形成工序和脱离工序。填埋工序中，以具有脲键的聚合物填埋形成于基板上的孔隙。氧化膜形成工序中，在前述基板上形成氧化膜。脱离工序中，使前述聚合物解聚，由此使解聚后的前述聚合物通过前述氧化膜而从前述孔隙脱离。
发明的效果
根据本公开，能确保层间绝缘膜的机械强度。
附图说明
图1A为示出实施方式的半导体装置的制造方法的一部分的说明图(1)。
图1B为示出实施方式的半导体装置的制造方法的一部分的说明图(2)。
图1C为示出实施方式的半导体装置的制造方法的一部分的说明图(3)。
图2A为示出实施方式的半导体装置的制造方法的一部分的说明图(4)。
图2B为示出实施方式的半导体装置的制造方法的一部分的说明图(5)。
图2C为示出实施方式的半导体装置的制造方法的一部分的说明图(6)。
图3A为示出实施方式的半导体装置的制造方法的一部分的说明图(7)。
图3B为示出实施方式的半导体装置的制造方法的一部分的说明图(8)。
图3C为示出实施方式的半导体装置的制造方法的一部分的说明图(9)。
图4A为示出实施方式的半导体装置的制造方法的一部分的说明图(10)。
图4B为示出实施方式的半导体装置的制造方法的一部分的说明图(11)。
图4C为示出实施方式的半导体装置的制造方法的一部分的说明图(12)。
图5A为示出实施方式的半导体装置的制造方法的一部分的说明图(13)。
图5B为示出实施方式的半导体装置的制造方法的一部分的说明图(14)。
图5C为示出实施方式的半导体装置的制造方法的一部分的说明图(15)。
图6为示出通过基于共聚的反应生成实施方式的具有脲键的聚合物的情况的说明图。
图7为示出实施方式的填埋部的构成的截面图。
图8为示出实施方式的脱离部的构成的截面图。
图9A为示出实施方式的变形例的半导体装置的制造方法的一部分的说明图(1)。
图9B为示出实施方式的变形例的半导体装置的制造方法的一部分的说明图(2)。
图9C为示出实施方式的变形例的半导体装置的制造方法的一部分的说明图(3)。
图10A为示出实施方式的变形例的半导体装置的制造方法的一部分的说明图(4)。
图10B为示出实施方式的变形例的半导体装置的制造方法的一部分的说明图(5)。
图11为示出实施方式的基板处理装置所执行的基板处理的步骤的流程图。
图12为示出实施方式的变形例的基板处理装置所执行的基板处理的步骤的流程图。
附图标记说明
W 晶圆
20、120 低介电常数膜
21 孔部(孔隙的一例)
22、122 聚脲(聚合物的一例)
29 导通孔
30 沟槽
31、123 氧化膜
32 势垒金属层
121 沟槽(孔隙的一例)
具体实施方式
以下，参照所附附图，对本申请公开的半导体装置的制造方法和基板处理装置的实施方式详细地进行说明。需要说明的是，本公开不受以下所示的实施方式的限定。另外，附图为示意性的，需要注意的是，各要素的尺寸的关系、各要素的比率等有时与现实不同。进而，附图的相互之间，有时也包含彼此的尺寸的关系、比率不同的部分。
以往，多层化了的半导体装置中，作为减小层间绝缘膜的相对介电常数的方法，已知有如下方法：在上述层间绝缘膜中填埋基板上的凹部时，利用作为填埋不良而形成的孔隙。
另一方面，作为填埋不良的形成于层间绝缘膜的孔隙没有由其他膜等所支撑，因此，对于形成有上述孔隙的层间绝缘膜，有机械强度降低的担心。
因此，可以期待确保层间绝缘膜的机械强度。
＜半导体装置的制造方法＞
首先，边参照图1A～图5C，边对实施方式的半导体装置的制造方法进行说明。图1A～图5C为示出实施方式的半导体装置的制造方法的一部分的说明图(1)～(15)。需要说明的是，该说明中，对通过双嵌入形成半导体装置的布线的处理中应用实施方式的例子进行说明。
如图1A所示那样，实施方式中，作为基板的半导体晶圆W(参照图7。以下，称为晶圆W)上形成有层间绝缘膜11、铜布线12、蚀刻阻止膜13和低介电常数膜20。层间绝缘膜11为下层侧的层间绝缘膜。铜布线12填埋至上述层间绝缘膜11，作为多层布线的一部分发挥功能。
蚀刻阻止膜13在后述的蚀刻处理时作为止挡件发挥功能。上述蚀刻阻止膜13例如由SiC(碳化硅)、SiCN(碳化氮化硅)等形成。
然后，在蚀刻阻止膜13上，形成有作为层间绝缘膜的低介电常数膜20。实施方式中，低介电常数膜20使用有SiOC膜。上述SiOC膜例如在CVD装置中将DEMS(二乙氧基甲基硅烷(Diethoxymethylsilane))等离子体化而成膜。需要说明的是，下层侧的层间绝缘膜11可以使用SiOC膜。
另外，低介电常数膜20为多孔，在内部形成有多个孔部21。实施方式中，孔部21为孔隙的一例。需要说明的是，图1A～图5C中，极示意性地图示上述孔部21。
实施方式中的半导体装置的制造方法中，如图1A所示那样，从在晶圆W的表面形成有下层侧的电路部分、且在上述电路部分上形成有低介电常数膜20的状态开始处理。
接着，如图1B所示那样，以聚脲22填埋低介电常数膜20内的孔部21。上述聚脲22为具有脲键的聚合物的一例，例如通过使多种原料单体利用蒸镀聚合进行共聚而形成。
图6为示出通过基于共聚的反应生成实施方式的具有脲键的聚合物的情况的说明图。如图6所示那样，聚脲22可以如下形成：使作为原料单体的异氰酸酯和胺以形成脲键的方式进行共聚，从而可以形成。需要说明的是，图6中的R例如为烷基(直链状烷基或环状烷基)或芳基，n为2以上的整数。
作为胺，例如可以使用脂环式化合物或脂肪族化合物。作为上述脂环式化合物，例如可以举出1,3-双(氨基甲基)环己烷(H6XDA)，作为上述脂肪族化合物，例如可以举出1,12-二氨基十二烷(DAD)。
作为异氰酸酯，例如可以使用脂环式化合物、脂肪族化合物、芳香族化合物等。作为上述脂环式化合物，例如可以举出1,3-双(异氰酸酯甲基)环己烷(H6XDI)，作为上述脂肪族化合物，例如可以举出六亚甲基二异氰酸酯。
以聚脲22填埋低介电常数膜20内的孔部21的处理在填埋部4中进行。图7为示出实施方式的填埋部4的构成的截面图。上述填埋部4例如为CVD装置。
填埋部4具有真空容器40和排气机构41。真空容器40用于划分真空气氛。排气机构41将真空容器40内排气用来形成上述真空气氛。
另外，借助供给管43a、43b将以液体收纳作为原料单体的异氰酸酯的原料供给源42a、和以液体收纳作为原料单体的胺的原料供给源42b与真空容器40连接。
由上述原料供给源42a、42b供给的异氰酸酯的液体和胺的液体被夹设于供给管43a、43b的气化器44a、44b气化。然后，异氰酸酯和胺的蒸气导入至作为气体喷出部的喷头45。
喷头45例如设置于真空容器40的上部，在下面形成有大量喷出孔。而且，对于喷头45，将所导入的异氰酸酯的蒸气和胺的蒸气从各喷出孔喷出至真空容器40内。
另外，搬入至填埋部4的内部的晶圆W载置于具备温度调节机构的载置台46。然后，在使真空容器40内为规定的压力的真空气氛的状态下，对晶圆W供给异氰酸酯的蒸气和胺的蒸气，从而在孔部21发生蒸镀聚合反应，以聚脲22填埋孔部21。
如此进行蒸镀聚合时的真空容器40内的温度可以根据原料单体的种类而确定，例如可以设为40℃～150℃。例如，原料单体的蒸气压较低的情况下，优选晶圆W的温度较高，原料单体的蒸气压较高的情况下，优选晶圆W的温度较低。
回到实施方式的半导体装置的制造方法的说明。如图1B所示那样，以聚脲22填埋低介电常数膜20的孔部21内后，对低介电常数膜20进行导通孔29(参照图3B)和沟槽30(布线填埋用的槽。参照图4A)的形成处理。
首先，如图1C所示那样，在低介电常数膜20的表面使对应于沟槽30的部位开口。例如，通过公知的方法形成由TiN(氮化钛)膜形成的蚀刻用的图案掩模即硬掩模23。
接着，如图2A所示那样，在低介电常数膜20和硬掩模23上，依次层叠对导通孔29进行蚀刻时成为掩模的掩模膜24、防反射膜25和抗蚀膜26。
掩模膜24例如可以使用以碳为主成分的有机膜。上述有机膜例如如下形成：在形成防反射膜25和抗蚀膜26并形成抗蚀图案的装置内，将化学溶液旋涂于晶圆W，从而可以形成。
接着，如图2B所示那样，对抗蚀膜26进行曝光和显影，从而在对应于导通孔29的部位形成作为抗蚀图案的开口部27。然后，如图2C所示那样，使用上述抗蚀图案，利用例如CF系的气体，对防反射膜25进行蚀刻。
接着，如图3A所示那样，以防反射膜25为掩模，利用例如等离子体化了的氧气气体对掩模膜24进行蚀刻。需要说明的是，通过上述氧气气体的等离子体，抗蚀膜26也被蚀刻而去除。通过至此的处理，在掩模膜24上，在对应于导通孔29的部位形成开口部28。
接着，如图3B所示那样，使用掩模膜24作为蚀刻掩模，对低介电常数膜20进行蚀刻，形成导通孔29。作为SiOC膜的低介电常数膜20的蚀刻例如可以利用等离子体化了的C6F6气体而进行。需要说明的是，上述情况下，可以在C6F6气体中进一步添加微量的氧气气体。
接着，如图3C所示那样，利用等离子体化了的氧气气体，将掩模膜24灰化而去除。然后，如图4A所示那样，通过与形成导通孔29的工艺同样的工艺，使用硬掩模23，对低介电常数膜20进行蚀刻，在包围导通孔29的区域形成沟槽30。
接着，如图4B所示那样，在导通孔29和沟槽30的内壁形成氧化膜31。氧化膜31例如为SiO2的低温氧化膜(LTO：Low TemperatureOxide)，与在高温下形成的热氧化膜相比为稀疏的膜。上述氧化膜31例如在应用作为公知的方法的ALD(原子层沉积(Atomic LayerDeposition))法的氧化膜形成部形成。
如此在导通孔29和沟槽30的内壁形成氧化膜31后，如图4C所示那样，使填埋低介电常数膜20的孔部21的聚脲22脱离。
使填埋低介电常数膜20的孔部21的聚脲22脱离的处理在脱离部5中进行。图8为示出实施方式的脱离部5的构成的截面图。
脱离部5具有处理容器51和排气管52。处理容器51用于划分处理气氛。排气管52将处理容器51内排气用来形成上述处理气氛。上述处理气氛例如为常压气氛，也可以为真空气氛。
用于供给氮气气体的供给管53与处理容器51连接。另外，搬入至脱离部5的内部的晶圆W载置于载置台54。然后，在使处理容器51内为规定的处理气氛的状态下，使灯罩55内的红外线灯56工作，从而可以加热晶圆W。
通过将填埋至孔部21的聚脲22加热至300℃以上、例如350℃，从而可以解聚成作为原料单体的胺和异氰酸酯。然后，上述解聚中产生的胺通过作为稀疏的膜的氧化膜31，从而可以使聚脲22从以氧化膜31密封的低介电常数膜20内的孔部21脱离。
此处，实施方式中，可以边以氧化膜31支撑形成有孔部21的低介电常数膜20，边使填埋至孔部21的聚脲22脱离。因此，根据实施方式，可以通过孔部21确保相对介电常数变小的低介电常数膜20的机械强度。
另外，实施方式中，可以使氧化膜31的形成处理在低于聚脲22的脱离处理的温度下进行。由此，形成氧化膜31时，可以抑制填埋至孔部21的聚脲22引起解聚反应。
另外，实施方式中，在低于脱离处理的温度下形成氧化膜31，从而可以将氧化膜31制成稀疏的膜，因此，可以使解聚中产生的胺通过氧化膜31顺利地脱离。
需要说明的是，实施方式中，示出了以聚脲22填埋孔部21的例子，但填埋孔部21的聚合物不限定于为高分子的聚脲22，只要为具有脲键的聚合物即可，也可以不是高分子。
上述脱离处理中，为了不对晶圆W上已经形成的元件部分、特别是铜布线造成不良影响，可以在低于400℃、优选390℃以下、更优选300～350℃进行加热。
另外，进行聚脲22的脱离的时间(加热时间)从抑制对元件的热损伤的观点出发，例如优选5分钟以下。因此，作为加热制程的优选例，可以举出350℃、5分钟以下。
另外，作为加热方法，可以使用红外线灯56，或者可以使晶圆W载置于内置有加热器的载置台54上并加热。需要说明的是，加热气氛例如可以设为氮气气体等非活性气体气氛。
接着，如图5A所示那样，对导通孔29的底部的蚀刻阻止膜13进行蚀刻而去除。蚀刻阻止膜13例如为SiC膜的情况下，上述蚀刻可以利用等离子体化了的CF4气体而进行。
接着，如图5B所示那样，在导通孔29和沟槽30的内壁形成势垒金属层32。势垒金属层32例如由Ti与TiON的层叠膜形成。
最后，如图5C所示那样，在导通孔29和沟槽30形成铜布线33，形成上层电路部分。具体而言，在导通孔29和沟槽30中填埋铜，多余的铜通过CMP(化学机械抛光(ChemicalMechanical Polishing))去除。需要说明的是，图5C中省略图示，但在形成铜布线33前，可以在势垒金属层32的表面形成由铜形成的晶种层。
如上述，实施方式中，在导通孔29和沟槽30的内壁形成氧化膜31后，将导通孔29的底部的蚀刻阻止膜13以蚀刻去除。由此，可以抑制由于上述蚀刻阻止膜13的蚀刻而对低介电常数膜20造成损伤。
另外，实施方式中，在导通孔29和沟槽30的内壁，势垒金属层32可以借助氧化膜31形成于低介电常数膜20而不是直接形成于低介电常数膜20。由此，可以抑制势垒金属层32的构成元素扩散至低介电常数膜20内。
需要说明的是，进行至此说明的各种处理的基板处理装置除上述填埋部4、氧化膜形成部、脱离部5之外，还具备输送机构。上述输送机构用于在填埋部4、氧化膜形成部、脱离部5等之间进行晶圆W的输送。
另外，实施方式的基板处理装置具备控制装置。上述控制装置例如为计算机，其具备控制部和存储部。上述控制部包含：具有CPU((中央处理单元)CentralProcessingUnit)、ROM((只读存储器)Read Only Memory)、RAM((随机存取存储器)Random AccessMemory)、输入输出端等的微型计算机、各种电路。
上述微型计算机的CPU通过读出存储于ROM的程序并执行，从而实现填埋部4、氧化膜形成部、脱离部5和输送机构等的控制。
需要说明的是，上述程序记录于能由计算机读取的存储介质，且由该存储介质安装于控制装置的存储部。作为能由计算机读取的存储介质，例如有：硬盘(HD)、软盘(FD)、光盘(CD)、磁光碟(MO)、记忆卡等。
存储部例如由RAM、闪速存储器(Flash Memory)等半导体存储元件、或、硬盘、光盘等存储装置实现。
实施方式的基板处理装置具备：填埋部4、氧化膜形成部、脱离部5和输送机构。填埋部4中，以具有脲键的聚合物(聚脲22)填埋形成于基板(晶圆W)上的孔隙(孔部21)。氧化膜形成部中，在基板(晶圆W)上形成氧化膜31。脱离部5中，使聚合物(聚脲22)解聚，由此使解聚后的聚合物(聚脲22)通过氧化膜31而从孔隙(孔部21)脱离。输送机构中，进行对基板(晶圆W)进行处理的各部之间的输送。由此，可以通过孔隙确保相对介电常数变小的低介电常数膜20的机械强度。
＜变形例＞
接着，对实施方式的变形例中涉及的半导体装置的制造方法，边参照图9A～图10B边进行说明。图9A～图10B为示出实施方式的变形例的半导体装置的制造方法的一部分的说明图(1)～(5)。
如图9A所示那样，实施方式中，在作为基板的晶圆W上，形成低介电常数膜120作为层间绝缘膜。另外，上述低介电常数膜120上形成有多个沟槽121。变形例中，沟槽121为孔隙的一例。
接着，如图9B所示那样，以聚脲122填埋低介电常数膜120内的沟槽121。上述聚脲122与实施方式同样地为具有脲键的聚合物，例如使多种原料单体利用蒸镀聚合进行共聚而形成。聚脲122例如使用上述填埋部4被填埋至沟槽121。
需要说明的是，变形例中，以聚脲122填埋沟槽121的方法不限定于蒸镀聚合，例如可以通过涂布法，以聚脲122填埋沟槽121。
接着，对以聚脲122填埋了沟槽121的低介电常数膜120实施规定的热处理，从而如图9C所示那样，使聚脲122从低介电常数膜120的上面和沟槽121的上部脱离。
接着，如图10A所示那样，在低介电常数膜120的上面形成氧化膜123。氧化膜123例如为SiO2的低温氧化膜(LTO)，与在高温下形成的热氧化膜相比，为稀疏的膜。另外，变形例中，聚脲122从沟槽121的上部脱离，因此，氧化膜123也被填埋至沟槽121的上部。
如此，在低介电常数膜120的上面和沟槽121的上部形成氧化膜123后，如图10B所示那样，使填埋低介电常数膜120的沟槽121的聚脲122脱离。聚脲122例如使用上述脱离部5从沟槽121脱离。
变形例中，聚脲122解聚而产生的胺通过作为稀疏的膜的氧化膜123，从而可以使聚脲122从以氧化膜123密封的低介电常数膜120内的沟槽121脱离。然后，在聚脲122脱离了的部位形成孔隙124。
此处，变形例中，在低介电常数膜120内形成孔隙124，因此，可以减小作为层间绝缘膜的低介电常数膜120的相对介电常数。而且，变形例中，可以边以氧化膜123支撑低介电常数膜120的沟槽121，边使填埋了沟槽121的聚脲122脱离。
因此，根据变形例，可以通过孔隙124确保相对介电常数变小的低介电常数膜120的机械强度。
另外，变形例中，使沟槽121的上部的聚脲122脱离，从而形成氧化膜123使其填埋至上述沟槽121的上部。由此，对于沟槽121保持氧化膜123使其成为固定件，因此，形成孔隙124后，也可以使氧化膜123充分保持在低介电常数膜120上。
＜处理的步骤＞
接着，对实施方式和变形例的基板处理的步骤，边参照图11和图12边进行说明。图11为示出实施方式的基板处理装置所执行的基板处理的步骤的流程图。
最初，以聚脲22填埋低介电常数膜20内的孔部21(步骤S101)。上述聚脲22为具有脲键的聚合物的一例，例如在填埋部4中，使多种原料单体利用蒸镀聚合进行共聚而形成。
接着，通过上述各种处理，在以聚脲22填埋孔部21的低介电常数膜20中形成导通孔29和沟槽30(步骤S102)。然后，在氧化膜形成部中，在导通孔29和沟槽30的内壁形成氧化膜31(步骤S103)。上述氧化膜31例如为SiO2的低温氧化膜，与在高温下形成的热氧化膜相比，为稀疏的膜。
接着，在脱离部5中，使填埋至孔部21的聚脲22解聚，由此使解聚后的聚脲22通过氧化膜31而从孔部21脱离(步骤S104)。例如，在脱离部5中，将晶圆W加热至350℃，从而可以使填埋孔部21的聚脲22解聚成作为原料单体的胺和异氰酸酯。
接着，将在导通孔29的底部露出的蚀刻阻止膜13以蚀刻去除(步骤S105)。然后，在导通孔29和沟槽30的内壁形成势垒金属层32(步骤S106)。
最后，通过上述各种处理，在导通孔29和沟槽30上形成铜布线33(步骤S107)，完成处理。
实施方式的半导体装置的制造方法包括如下工序：填埋工序(步骤S101)、氧化膜形成工序(步骤S103)和脱离工序(步骤S104)。填埋工序(步骤S101)中，以具有脲键的聚合物(聚脲22)填埋形成于基板(晶圆W)上的孔隙(孔部21)。氧化膜形成工序(步骤S103)中，在基板(晶圆W)上形成氧化膜31。脱离工序(步骤S104)中，使聚合物(聚脲22)解聚，由此使解聚后的聚合物(聚脲22)通过氧化膜31而从孔隙(孔部21)脱离。由此，可以通过孔隙确保相对介电常数变小的低介电常数膜20的机械强度。
另外，实施方式的半导体装置的制造方法中，填埋工序(步骤S101)中，以由蒸镀聚合形成的聚合物(聚脲22)填埋孔隙(孔部21)。由此，对于形成于低介电常数膜20内的微细的孔部21，也可以充分填埋聚脲22。
另外，实施方式的半导体装置的制造方法中，氧化膜形成工序(步骤S103)在低于脱离工序(步骤S104)的温度下进行。由此，形成氧化膜31时，可以抑制填埋至孔部21的聚脲22引起解聚反应。
另外，实施方式的半导体装置的制造方法中，孔隙为形成于低介电常数膜20的内部的孔部21。由此，可以降低低介电常数膜20的相对介电常数。
另外，实施方式的半导体装置的制造方法还包括如下导通孔形成工序(步骤S102)：在以聚合物(聚脲22)填埋孔部21的低介电常数膜20中形成导通孔29。而且，氧化膜形成工序(步骤S103)在导通孔形成工序(步骤S103)后进行。由此，可以以氧化膜31支撑形成有孔部21和导通孔29的低介电常数膜20。
另外，实施方式的半导体装置的制造方法在氧化膜形成工序(步骤S103)后还包括如下去除工序(步骤S105)：去除在导通孔29的底部露出的蚀刻阻止膜13。由此，可以抑制由于上述蚀刻阻止膜13的蚀刻而对低介电常数膜20造成损伤。
另外，实施方式的半导体装置的制造方法在脱离工序(步骤S104)后还包括：在氧化膜31上形成势垒金属层32的势垒金属层形成工序(步骤S106)：。由此，使聚脲22从孔部21脱离时，可以抑制势垒金属层32成为上述脱离的障碍，且可以抑制势垒金属层32的构成元素扩散至低介电常数膜20内。
图12为示出实施方式的变形例的基板处理装置所执行的基板处理的步骤的流程图。最初，在填埋部4中，以聚脲122填埋形成于低介电常数膜120的沟槽121(步骤S201)。
接着，实施规定的热处理，从而使聚脲122从低介电常数膜120的上面和沟槽121的上部脱离(步骤S202)。然后，在氧化膜形成部中，在聚脲122脱离了的低介电常数膜120的上面和沟槽121的上部形成氧化膜123(步骤S203)。
接着，在脱离部5中，使填埋至沟槽121的聚脲122解聚，由此使解聚后的聚脲122通过氧化膜123而从沟槽121脱离(步骤S204)，完成处理。
实施方式的变形例的半导体装置的制造方法中，孔隙为形成于基板(晶圆W)上的沟槽121。由此，可以降低低介电常数膜120的相对介电常数。
以上，对本公开的实施方式进行了说明，但本公开不限定于上述实施方式，只要不脱离其主旨就可以进行各种变更。例如上述实施方式中，示出了由ALD法形成氧化膜31的例子，但可以由除ALD法以外的方法形成氧化膜31。
另外，上述实施方式中，作为填埋至孔部21的聚合物，对以聚脲22为例进行了说明，但上述聚合物不限定于聚脲。例如，上述聚合物可以使用具有氨基甲酸酯键的聚氨酯。
聚氨酯例如可以通过使具有醇基的单体与具有异氰酸酯基的单体进行共聚而合成，且通过加热至规定的温度，从而可以解聚成具有醇基的单体和具有异氰酸酯基的单体。
因此，可以使用聚氨酯代替上述聚脲22作为填埋至孔部21的聚合物。进而，作为填埋至孔部21的聚合物，只要为能解聚的聚合物即可，可以使用除聚脲、聚氨酯以外的聚合物。
另外，上述实施方式中，作为氧化膜31，对以SiO2的低温氧化膜为例进行了说明，但上述氧化膜不限定于SiO2的低温氧化膜。例如，上述氧化膜可以使用SiOC那样的多孔膜。
此次公开的实施方式在全部方面为示例，且应认为没有限制。实际上，上述实施方式能以各种方式具体化。另外，上述实施方式在不脱离所附的权利要求书和其主旨的情况下，可以以各种方式省略、置换、变更。

Claims (9)

1.一种半导体装置的制造方法，其包括如下工序：
填埋工序，以具有脲键的聚合物填埋形成于基板上的孔隙；
氧化膜形成工序，在所述基板上形成氧化膜；和，
脱离工序，使所述聚合物解聚，由此使解聚后的所述聚合物通过所述氧化膜而从所述孔隙脱离。
2.根据权利要求1所述的半导体装置的制造方法，其中，所述填埋工序中，以蒸镀聚合形成的所述聚合物填埋所述孔隙。
3.根据权利要求1或2所述的半导体装置的制造方法，其中，所述氧化膜形成工序在低于所述脱离工序的温度下进行。
4.根据权利要求1～3中任一项所述的半导体装置的制造方法，其中，所述孔隙为形成于低介电常数膜的内部的孔部。
5.根据权利要求4所述的半导体装置的制造方法，其中，还包括如下导通孔形成工序：在以所述聚合物填埋所述孔部的所述低介电常数膜中形成导通孔，
所述氧化膜形成工序在所述导通孔形成工序后进行。
6.根据权利要求5所述的半导体装置的制造方法，其中，在所述氧化膜形成工序后，还包括如下去除工序：去除在所述导通孔的底部露出的蚀刻阻止膜。
7.根据权利要求5或6所述的半导体装置的制造方法，其中，在所述脱离工序后，还包括如下势垒金属层形成工序：在所述氧化膜上形成势垒金属层。
8.根据权利要求1～3中任一项所述的半导体装置的制造方法，其中，所述孔隙为形成于所述基板上的沟槽。
9.一种基板处理装置，其具备：
填埋部，其以具有脲键的聚合物填埋形成于基板上的孔隙；
氧化膜形成部，其在所述基板上形成氧化膜；
脱离部，其使所述聚合物解聚，由此使解聚后的所述聚合物通过所述氧化膜而从所述孔隙脱离；和，
输送机构，其进行对所述基板进行处理的各部之间的输送。
CN201910445691.9A 2018-05-28 2019-05-27 半导体装置的制造方法和基板处理装置 Active CN110544650B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-101331 2018-05-28
JP2018101331A JP7045929B2 (ja) 2018-05-28 2018-05-28 半導体装置の製造方法および基板処理装置

Publications (2)

Publication Number Publication Date
CN110544650A true CN110544650A (zh) 2019-12-06
CN110544650B CN110544650B (zh) 2024-04-19

Family

ID=68614098

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910445691.9A Active CN110544650B (zh) 2018-05-28 2019-05-27 半导体装置的制造方法和基板处理装置

Country Status (5)

Country Link
US (1) US11342223B2 (zh)
JP (1) JP7045929B2 (zh)
KR (1) KR102447740B1 (zh)
CN (1) CN110544650B (zh)
TW (1) TWI779196B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6960839B2 (ja) * 2017-12-13 2021-11-05 東京エレクトロン株式会社 半導体装置の製造方法
JP7065741B2 (ja) * 2018-09-25 2022-05-12 東京エレクトロン株式会社 半導体装置の製造方法
US11164956B2 (en) * 2019-08-23 2021-11-02 Taiwan Semiconductor Manufacturing Co., Ltd. Capping layer for gate electrodes
JP7489786B2 (ja) * 2020-02-28 2024-05-24 東京エレクトロン株式会社 半導体装置の製造方法
JP7341100B2 (ja) * 2020-04-28 2023-09-08 東京エレクトロン株式会社 半導体装置の製造方法
JP7539297B2 (ja) 2020-10-29 2024-08-23 東京エレクトロン株式会社 基板処理方法および基板処理システム
JP2023025578A (ja) 2021-08-10 2023-02-22 東京エレクトロン株式会社 成膜装置

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10289903A (ja) * 1997-04-11 1998-10-27 Ulvac Japan Ltd 低比誘電性絶縁膜及びその形成方法並びに層間絶縁膜
US5942802A (en) * 1995-10-09 1999-08-24 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of producing the same
TWI222426B (en) * 1998-04-01 2004-10-21 Asahi Kasei Corp Method for producing a circuit structure
JP2005353674A (ja) * 2004-06-08 2005-12-22 Seiko Epson Corp 半導体装置の製造方法及び半導体装置。
US20060069171A1 (en) * 2004-09-07 2006-03-30 Rohm And Haas Electronic Materials Llc Composition and method
CN101329999A (zh) * 2007-06-20 2008-12-24 株式会社半导体能源研究所 半导体衬底及其制造方法
US20090152732A1 (en) * 2007-12-14 2009-06-18 Panasonic Corporation Semiconductor device and method of manufacturing the same
CN101868852A (zh) * 2007-12-04 2010-10-20 日立化成工业株式会社 感光性胶粘剂、半导体装置及半导体装置的制造方法
US20150332955A1 (en) * 2014-05-15 2015-11-19 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same
CN107644804A (zh) * 2016-07-21 2018-01-30 东京毅力科创株式会社 半导体装置的制造方法、真空处理装置及基板处理装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0300366A1 (en) * 1987-07-20 1989-01-25 Air Products And Chemicals, Inc. Non-fugitive aromatic diamine catalytic chain extenders
US8492239B2 (en) * 2010-01-27 2013-07-23 International Business Machines Corporation Homogeneous porous low dielectric constant materials
JP5560144B2 (ja) 2010-08-31 2014-07-23 東京エレクトロン株式会社 半導体装置の製造方法
JP5636277B2 (ja) * 2010-12-27 2014-12-03 富士フイルム株式会社 多孔質絶縁膜及びその製造方法
US8932934B2 (en) * 2013-05-28 2015-01-13 Global Foundries Inc. Methods of self-forming barrier integration with pore stuffed ULK material
US9508549B2 (en) * 2014-12-26 2016-11-29 Dow Global Technologies Llc Methods of forming electronic devices including filling porous features with a polymer
US10008382B2 (en) * 2015-07-30 2018-06-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a porous low-k structure
JP6465189B2 (ja) * 2016-07-21 2019-02-06 東京エレクトロン株式会社 半導体装置の製造方法及び真空処理装置

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5942802A (en) * 1995-10-09 1999-08-24 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of producing the same
JPH10289903A (ja) * 1997-04-11 1998-10-27 Ulvac Japan Ltd 低比誘電性絶縁膜及びその形成方法並びに層間絶縁膜
TWI222426B (en) * 1998-04-01 2004-10-21 Asahi Kasei Corp Method for producing a circuit structure
JP2005353674A (ja) * 2004-06-08 2005-12-22 Seiko Epson Corp 半導体装置の製造方法及び半導体装置。
US20060069171A1 (en) * 2004-09-07 2006-03-30 Rohm And Haas Electronic Materials Llc Composition and method
CN101329999A (zh) * 2007-06-20 2008-12-24 株式会社半导体能源研究所 半导体衬底及其制造方法
CN101868852A (zh) * 2007-12-04 2010-10-20 日立化成工业株式会社 感光性胶粘剂、半导体装置及半导体装置的制造方法
US20090152732A1 (en) * 2007-12-14 2009-06-18 Panasonic Corporation Semiconductor device and method of manufacturing the same
US20150332955A1 (en) * 2014-05-15 2015-11-19 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same
CN107644804A (zh) * 2016-07-21 2018-01-30 东京毅力科创株式会社 半导体装置的制造方法、真空处理装置及基板处理装置

Also Published As

Publication number Publication date
TWI779196B (zh) 2022-10-01
JP2019207909A (ja) 2019-12-05
JP7045929B2 (ja) 2022-04-01
TW202013470A (zh) 2020-04-01
KR20190135410A (ko) 2019-12-06
KR102447740B1 (ko) 2022-09-28
US11342223B2 (en) 2022-05-24
US20190363011A1 (en) 2019-11-28
CN110544650B (zh) 2024-04-19

Similar Documents

Publication Publication Date Title
CN110544650B (zh) 半导体装置的制造方法和基板处理装置
KR102268929B1 (ko) 반도체 장치의 제조 방법
JP6465189B2 (ja) 半導体装置の製造方法及び真空処理装置
KR102548634B1 (ko) 반도체 장치의 제조 방법 및 기판 처리 장치
KR102317534B1 (ko) 반도체 장치의 제조 방법
US11495490B2 (en) Semiconductor device manufacturing method
JP6696491B2 (ja) 半導体装置の製造方法及び真空処理装置
CN110546744B (zh) 绝缘膜的成膜方法、绝缘膜的成膜装置及基板处理系统
CN110942978B (zh) 半导体装置的制造方法
KR20190045071A (ko) 반도체 장치의 제조 방법
CN111192854B (zh) 半导体存储器的制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant