CN110534498A - 封装的半导体器件 - Google Patents

封装的半导体器件 Download PDF

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Publication number
CN110534498A
CN110534498A CN201910426938.2A CN201910426938A CN110534498A CN 110534498 A CN110534498 A CN 110534498A CN 201910426938 A CN201910426938 A CN 201910426938A CN 110534498 A CN110534498 A CN 110534498A
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CN
China
Prior art keywords
trace
blocking condenser
semiconductor devices
layer
blocking
Prior art date
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Application number
CN201910426938.2A
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English (en)
Inventor
唐逸麒
R·M·穆卢干
M·R·库卡尼
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Texas Instruments Inc
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Texas Instruments Inc
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Publication of CN110534498A publication Critical patent/CN110534498A/zh
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H01L27/0733—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with capacitors only
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Abstract

本申请公开封装的半导体器件。封装的半导体器件(300)包括塑封的互连衬底，塑封的互连衬底具有信号层(221)和底部金属层(223)，信号层包括在具有通孔的介电层(222)上的第一和第二通道，底部金属层用于提供接地回波路径。信号层包括接触焊盘，第一和第二通道的迹线包括变窄的迹线区域(221s)，且底部金属层包括含有接地切割区域(223a)的图案化层。DC阻隔电容器(C1、C2、C3、C4)串联在第一和第二通道的迹线内，用于提供AC耦合，DC阻隔电容器在一个接地切割中的上方具有一个极板。集成电路(IC)(210)包括经耦合以接收来自DC阻隔电容器的输出的第一和第二差分输入通道，其中其上的凸块阵列(218)倒装芯片安装到接触焊盘以提供第一和第二差分输出信号。

Description

封装的半导体器件
相关申请的交叉引用
本申请要求于2018年5月23日提交的临时申请序列号62/675,396，标题为“用于高速(56Gbps+)应用的MIS多层FC-QFN封装结构”的权益，其全部内容通过参考并入本文。
技术领域
本公开涉及高速封装的半导体器件。
背景技术
一些高速信号/数据器件(诸如重定时器电路、中继器和时钟合成器)是通常封装在倒装芯片球栅阵列(FC BGA)封装中的高容量和中高引脚数器件，该FC BGA封装为相对较高的成本封装。具有成本效益的替代方案是引线键合BGA封装。然而，高速(>5千兆位/秒(Gbps))的引线键合BGA封装的电气性能相对较差，诸如具有差的插入损耗和差的回波损耗(return loss)。
集成电路(IC)封装可以基于称为塑封互连衬底(MIS)的新兴技术。MIS以专用衬底材料开始，用于选择IC封装。MIS本身由各种供应商开发和销售，然后封装厂通常采用MIS并在其周围组装IC封装，包括添加成型。有些人将MIS称为引导框架。
MIS与传统衬底不同，因为MIS技术包括具有一个或更多个金属层的预塑封结构。每层通常预先配置有至少一个顶部和一个底部铜镀层，在铜层之间具有介电层，该铜层具有通孔以在封装中提供电连接。
发明内容
提供本发明内容是为了以简化的形式介绍所公开的概念的简要选择，这些概念将在下面的详细描述(包括所提供的附图)中进一步描述。本发明内容不旨在限制所要求保护的主题的范围。
通过开发物理结构加上封装中的DC阻隔电容器来提供较便宜的MIS QFN技术(其具有经调谐以提供与传统FC BGA封装类似性能的MIS)，所公开的方面解决了用于高速器件的FC BGA封装的高成本的问题(因为需要满足高电气性能，例如，56Gbps或更高的数据速率)。所公开的性能调谐包括使信号层上的相应迹线(例如，每个通道的负(N)信号迹线和正(P)信号迹线)变窄并提供具有接地切割(ground cuts)的底部金属层，其中变窄的信号迹线延伸超过接地切割并且DC阻隔电容器各自在接地切割上方有一个极板。
所公开的方面包括封装的半导体器件，其包括具有信号层和底部金属层的塑封互连衬底，该信号层包括在具有通孔的介电层上的第一通道和第二通道，以及该底部金属层用于提供接地回波路径。信号层包括接触焊盘，第一和第二通道的迹线包括变窄的迹线区域，并且底部金属层包括含有接地切割区域的图案化层。DC阻隔电容器串联在第一和第二通道的迹线内，用于提供AC耦合，其中DC阻隔电容器在接地切割中的一个上方具有一个极板。IC包括经耦合以接收来自DC阻隔电容器的输出的第一和第二差分输入通道，其中其上的凸块阵列倒装芯片安装到接触焊盘以提供第一和第二差分输出信号。
附图说明
现在将参考附图，附图不一定按比例绘制，其中：
图1A是示例封装的基于MIS QFN的半导体器件的不具有其塑封的部分，该器件具有两个通道，并且每个通道具有两条迹线，总共四条迹线，每条迹线具有串联的DC阻隔电容器。
图1B是图1A中所示的封装的基于MIS QFN的半导体器件的部分的原理图。
图2是根据一个示例方面的示例封装的基于MIS QFN的半导体器件的具有塑封料(mold compound)的截面图，其针对通过示出为C1的DC阻隔电容器的通道的一个差分输入，示出了信号层中的信号路径。
图3是示例封装的基于MIS QFN的半导体器件的不具有其塑封的部分的特写描绘，其中一个DC阻隔电容器被移除以示出所公开的接地切割和所公开的“细长”迹线调谐。
图4A-图4B将图4A中的已知的基于FC BGA的半导体器件之间的模拟的插入损耗和图4B中的插入损耗进行了比较，图4B的插入损耗针对缺少所公开的性能调谐的原始的基于MIS QFN的半导体器件，以及针对包括所公开的性能调谐的基于MIS QFN的半导体器件。要满足的规范是在14GHz处，<0.5dB的插入损耗；在14GHz处，<15dB(推至<20dB)的插入损耗，其中器件在14GHz(56Gbps)处操作。
图4C-图4D将图4C中的已知的基于FC BGA的半导体器件之间的模拟的回波损耗和图4D中的插入损耗进行了比较，图4D的回波损耗针对缺少所公开的性能调谐的原始的基于MIS QFN的半导体器件，以及针对包括所公开的性能调谐的基于MIS QFN的半导体器件。
具体实施方式
参考附图描述示例实施例，其中相同的附图标记用于表示相似或等同的元件。不应将行为或事件的所说明的排序视为限制，因为某些行为或事件可能以不同的顺序发生和/或与其他行为或事件同时发生。此外，可能不需要一些所说明的动作或事件来实施根据本公开的方法。
图1A描绘了示例封装的基于MIS QFN的半导体器件100的四分之一(25％)，其被示为双通道器件，具有第一通道和第二通道，包括MIS 220，具有第一、第二、第三和第四直流(DC)阻隔电容器C1、C2、C3和C4，其中每个通道有两个(一个用于P迹线，一个用于N迹线，或‘管脚(legs)’)DC阻隔电容器，用于为每个输入提供用于阻隔低频分量的DC阻隔电容器。IC管芯210通过凸块阵列附接到MIS 220，凸块阵列具有示为218的凸块。凸块阵列可以包括铜柱，其上具有位于IC管芯210的接合焊盘上的焊料凸块。
尽管通常存在用于所公开的封装器件的塑封料，但是图1A中未示出塑封料以避免模糊特征。而且，虽然未示出，但是还存在来自IC管芯210的另一端的输入信号，由IC管芯210处理，然后从第一和第二通道输出。如图1B的简化原理图中所示，如IC管芯部分210’所示的IC管芯具有接收器(Rx)2110、2111和发送器(Tx)2130、2131，其通过用于修复输入信号的时钟数据恢复(CDR)电路2120、2121耦合在一起，然后输出修复后的信号。
封装的半导体器件100通常可以包括与高速信号路径交流耦合的任何器件，高速信号路径穿过MIS 220行进到IC管芯210并且从IC管芯210穿过MIS 220行进。例如，高速信号调节器，诸如信号重定时器，或高性能计算群集(computing farm)应用程序中使用的信号中继器。所公开的基于MIS QFN的半导体器件可以被调谐以通常用于任何串行器/解串器(Serdes)或高速通道。
MIS 220包括提供顶表面的信号层221和底部金属层223，信号层211包括位于具有通孔的介电层222上的接触焊盘，以及底部金属层223提供接地回波路径，其也可用于附加的信号迹线。通过介电层222中的通孔布线到达底部金属层的信号层221上的迹线将是封装的基于MIS QFN的半导体器件的物理底部，客户通常将其焊接(图1A中未示出图案化的焊料层，但是参见下面描述的图2中的图案化焊料层219)到PCB 240所示的其印刷电路板(PCB)。图案化焊料层可以包括附接到MIS封装220的底部金属层223的焊球或者可以包括印刷到PCB 240上的焊料膏丝网(solder paste screen)。虽然未示出，但MIS衬底220可以包括多于所示的3层。
信号层221和底部金属层223通常包括铜或铜合金。介电层222通常包括塑封料作为层221和223之间的介电材料。封装中已知的塑封料通常是复合材料，其包括环氧树脂、酚类硬化剂、二氧化硅、催化剂、颜料和脱模剂。
MIS 220提供共面波导(CPW)微带结构。MIS 220的厚度可以是约80μm，信号层221和底部金属层223的厚度约为20μm，并且介电层222的厚度约为40μm。DC阻隔电容器通常具有0.05μF至2μF的电容。该电容范围高于IC上的电容器通常可能的电容范围，因此DC阻隔电容器通常是与IC分离的器件。在0201尺寸(0.6x0.3mm)中，DC阻隔电容器的典型电容为0.22μF。
图1B示出了图1A中所示的差分输入通道的简化等效电路。对于每个通道，存在差分信号，其示为每个通道的N迹线和P迹线，对于第一通道，示为RX0P和RX0N，对于第二通道，示为RX1P和RX1N。底部金属层223为每个信号迹线提供回波路径以提供阻抗匹配。信号本身是差分信号，即N和P。具体地选择信号层221中的迹线的间隙/宽度以最大化信号的差分传输。
在IC的输入端(示为IC管芯部分210’)处是DC阻隔电容器C1、C2、C3和C4。在信号层221上的迹线、介电层222中的通孔、凸块(参见下面描述的图2)和在C1、C2、C3和C4任一侧上连接到IC管芯部分210’的路径中的互连由所示的实线表示。在IC管芯部分210’的输出侧上，每个通道存在两个的DC阻隔电容器，示为C5、C6、C7和C8，并且信号层221上的封装迹线、介电层222中的通孔和凸块(参见下面描述的图2)和从IC管芯到DC阻隔电容器的路径中的互连也由所示的实线表示。
图2是示例封装的基于MIS QFN的半导体器件200的具有塑封料260的横截面图，其针对通过示出为C1的DC阻隔电容器的通道的一个差分输入，用箭头示出了显示为“信号输入”的信号路径。IC管芯210具有凸块阵列(其中一个凸块218被标识)，其倒装芯片附接(FCattached)到MIS的信号层221上的接触焊盘。在基于MIS QFN的半导体器件200外部，在底部金属层223上存在图案化的焊料层219(诸如焊球)，该焊料层219从MIS 220的底部上的塑封料260暴露，用于将底部金属层223耦合到在PCB 240上的连接盘(land)。
所示箭头标识从PCB 240到图案化焊料层219、到底部金属层223、到介电层222中的通孔、到信号层221上的节点、到C1的一个极板的信号流。在通过C1之后，信号到达C1的另一个极板，然后到达信号层221上的另一个节点，到达凸块218(例如，带有焊料的Cu柱凸块)，并且最后到达IC管芯210。
图3是示例封装的基于MIS QFN的半导体器件300的不具有其塑封的部分的特写描绘，其中一个DC阻隔电容器C1被移除以示出所公开的接地切割223a和包括在接地切割223a上方的所公开的细长迹线221s，接地切割和细长迹线两者都是用于MIS性能调谐。包括所示的接地切割223a的接地切割区域缺少介电层222，使得接地切割223a上方的电容器极板在其下方没有底部金属层。注意到图3中的空白区域填充有电介质，是塑封料(例如，参见上面所描述的图2中的塑封料260)。
例如，所示的50μm的标称线宽可以用于信号层221，而细长迹线221s可以具有如所示的30μm的宽度，其中该特定示例布置表示细长迹线221s具有40％的迹线宽度减小。给定的器件性能要求通过调谐来满足，该调谐使用信号层221上的迹线变窄以提供细长迹线区域和接地切割223a，两者通常用于满足器件规范，诸如在给定工作频率下的插入损耗和回波损耗。对于一个特定的示例规范，该规范是在14GHz处，<0.5dB的插入损耗；在14GHz处，<15dB(推至<20dB)的插入损耗，其中器件在14GHz(56Gbps)处操作。
信号层221上的迹线变窄的百分比范围(％范围)是5％至50％，诸如标准50μm迹线宽度中的25μm的细长迹线221s。如图3中所示，第一信号层221中的迹线的宽度通常可以是50μm。然而，当第一信号层221迹线相对靠近电容器焊盘(其中一个焊盘在接地切割区域上方)时，迹线宽度显着减小，诸如对于细长迹线调谐而言为30μm。
可以看到示出为C2和C3的DC阻隔电容器的一个极板位于接地切割223a上方。图3所示的框中的信号层221上的金属焊盘用于在上面附接C1的一个极板，就像C2和C3附接相应的金属焊盘，该附接包括接地切割223a上方的其极板中的一个。
关于信号层迹线的调谐，可以根据塑封料材料属性微调迹线。信号层221的细长迹线的迹线宽度可以最初由理论和/或经验预先定义，然后可以由2D场模拟器预先模拟到几个迹线维度候选者内，然后可以通过对其端性能上的全波3D模拟来进行验证。在所有这些步骤期间，介电层222中的塑封料属性(其介电常数和损耗角正切)，以及所期望的特性阻抗Zo作为参数被输入，特性阻抗Zo对于单端通常为50欧姆和对于差分通常为100欧姆。
关于可应用的理论，下面抄写的微带线的Zo的经验方程示出了介电常数如何是一种塑封料属性，因为介电层222中的电介质影响信号层221迹线的特性阻抗，这被认为对阻抗匹配很重要，因此对器件性能也很重要。微带线的方程示出了其特性阻抗Zo与迹线的尺寸以及介电层222的介电常数∈e之间的关系，其中W是迹线宽度，并且d是通孔厚度，通孔厚度由介电层222的厚度设置，该介电层222的厚度决定信号层221和底部金属层223之间的距离。
对于
如上面所描述的，Zo范围通常被控制为单端50欧姆和差分100欧姆。射频(RF)电子领域中已知的微带线通常在电介质区域中具有其大部分场力线，这里电介质层222集中在信号层221和底部金属层223之间。所公开的接地切割的放置位于电容器焊盘中的一个的正下方，使得每个DC阻隔电容器都具有带接地切割的焊盘。底部金属层223中的相同接地切割也在细长迹线下方实施。DC阻隔电容器焊盘由于他们与接地平面的耦合而通常是非常电容性的，因此接地切割降低了封装的整体电容性表现。在信号层221上的细长迹线下方也存在接地切割，以进一步增加细长迹线的电感。
图4A-图4B将图4A中的已知的基于FC BGA的半导体器件之间的模拟的插入损耗和图4B中的插入损耗进行了比较，图4B的插入损耗针对缺少所公开的性能调谐的原始的基于MIS QFN的半导体器件，以及针对包括所公开的性能调谐的基于MIS QFN的半导体器件。该IC是一个数据中心重定时器，用于扩展长的、有损、串扰受损的高速串行链路的范围和鲁棒性，同时实现10到15或更低的误码率(BER)。要满足的规范是在14GHz处，<0.5dB的插入损耗；在14GHz处，<15dB(推至<20dB)的插入损耗，其中器件在14GHz(56Gbps)处操作。
图4C-图4D将图4C中的已知的基于FC BGA的半导体器件之间的模拟的回波损耗和图4D中的插入损耗进行了比较，图4D的回波损耗针对缺少所公开的性能调谐的原始的基于MIS QFN的半导体器件，以及针对包括所公开的性能调谐的基于MIS QFN的半导体器件。
图4A-图4D中的数据证明了：如本文所描述的，通过使用显著便宜的MIS QFN技术(其可以经调谐以提供与传统基于FC BGA封装的器件相类似的性能)来开发物理结构加上封装中的DC阻隔电容器，用于高速器件的传统FC BGA封装技术的高成本的问题(因为需要满足高电气性能，56Gbps+的数据速率)被解决。公开的基于MIS QFN的封装器件提供传统FC-BGA封装技术的性能，其中封装成本降低了约40％至60％，并且由于MIS工艺流程比传统封装衬底制造更快，因此生产周期缩短了1到2周。
所公开的实施例可以集成到各种组装流程中以形成各种不同的封装器件和相关产品。该组件可包括单个半导体管芯或多个半导体管芯，诸如包括多个堆叠半导体管芯的PoP配置。可以使用各种封装衬底。半导体管芯可以包括其中的各种元件和/或其上的层，包括阻隔层、介电层、器件结构、有源元件和无源元件，其包括源区、漏区、位线、基极、发射极、集电极、导电线、导电通孔等。此外，半导体管芯可以由各种工艺形成，包括双极型晶体管、绝缘栅双极晶体管(IGBT)、CMOS、BiCMOS和MEMS。
本公开所涉及领域的技术人员将了解，在要求保护的发明的范围内，实施例的许多其他实施例和变型是可能的，并且在不背离本公开的范围的情况下，可以对所描述的实施例进行进一步的添加、删除、替换和修改。

Claims (18)

1.一种封装的半导体器件，其包括：
多层塑封的互连衬底即MIS，其具有信号层和底部金属层，所述信号层包括用于在具有通孔的介电层上的第一通道的第一迹线和第二迹线以及用于在具有通孔的所述介电层上的第二通道的第一迹线和第二迹线，并且所述介电层下面的所述底部金属层用于提供接地回波路径，所述信号层包括接触焊盘，其中所述第一通道和所述第二通道的所述第一迹线和所述第二迹线包括变窄的迹线区域，以及所述底部金属层包括含有多个接地切割区域的图案化层；
串联在所述第一通道的所述第一迹线和所述第二迹线内的第一直流阻隔电容器即DC阻隔电容器和第二DC阻隔电容器，用于提供交流耦合即AC耦合，所述第一DC阻隔电容器和所述第二DC阻隔电容器各自在所述接地切割中的一个上具有一个极板；
串联在所述第二通道的所述第一迹线和所述第二迹线内的第三DC阻隔电容器和第四DC阻隔电容器，用于提供AC耦合，所述第三DC阻隔电容器和所述第四DC阻隔电容器各自在所述接地切割中的一个上方具有一个极板，并且
集成电路即IC，其包括：第一差分输入通道，其经耦合以接收来自所述第一DC阻隔电容器和所述第二DC阻隔电容器的输出；以及至少第二差分输入通道，其经耦合以接收所述第三DC阻隔电容器和所述第四DC阻隔电容器的输出，其中其上的凸块阵列倒装芯片安装到所述接触焊盘，以提供第一差分输出信号和第二差分输出信号。
2.根据权利要求1所述的封装的半导体器件，其中，与所述信号层上的其他迹线的宽度相比，所述变窄的迹线区域至少变窄20％。
3.根据权利要求1所述的封装的半导体器件，其中，与所述信号层上的其他迹线的宽度相比，所述变窄的迹线区域至少变窄40％。
4.根据权利要求1所述的封装的半导体器件，其中，所述凸块阵列包括铜柱，所述铜柱在其上具有焊料凸块。
5.根据权利要求1所述的封装的半导体器件，其还包括印刷电路板即PCB和位于所述底部金属层和所述PCB之间的焊料图案，以及为所述封装的半导体器件提供包封的塑封料。
6.根据权利要求1所述的封装的半导体器件，其中，所述IC包括通信器件，所述通信器件包括含有解码器的接收器和包括编码器的发射器。
7.根据权利要求1所述的封装的半导体器件，其中，所述第一DC阻隔电容器、所述第二DC阻隔电容器、所述第三DC阻隔电容器和所述第四DC阻隔电容器的电容为0.05μF至2μF。
8.根据权利要求1所述的封装的半导体器件，其中，所述变窄的迹线区域位于接近所述DC阻隔电容器的所述极板的第一接地切割上方，所述DC阻隔电容器的所述极板在所述第一接地切割上方。
9.根据权利要求1所述的封装的半导体器件，其中，所述介电层包括复合材料，所述复合材料包括环氧树脂。
10.一种制造封装的半导体器件的方法，其包括：
提供多层塑封的互连衬底即MIS，其具有信号层和底部金属层，所述信号层包括用于在具有通孔的介电层上的第一通道的第一迹线和第二迹线以及用于在具有通孔的所述介电层上的第二通道的第一迹线和第二迹线，并且所述介电层下面的所述底部金属层用于提供接地回波路径，所述信号层包括接触焊盘，其中所述第一通道和所述第二通道的所述第一迹线和所述第二迹线包括变窄的迹线区域，以及所述底部金属层包括含有多个接地切割区域的图案化层；
在所述第一通道的所述第一迹线和所述第二迹线内串联地附接第一直流阻隔电容器即DC阻隔电容器和第二DC阻隔电容器，用于提供交流耦合即AC耦合，所述第一DC阻隔电容器和所述第二DC阻隔电容器各自在所述接地切割中的一个上方具有一个极板，以及在所述第二通道的所述第一迹线和所述第二迹线内串联地附接第三DC阻隔电容器和第四DC阻隔电容器，用于提供AC耦合，所述第三DC阻隔电容器和所述第四DC阻隔电容器各自在所述接地切割中的一个上方具有一个极板，并且
附接集成电路即IC包括：第一差分输入通道，其经耦合以接收来自所述第一DC阻隔电容器和所述第二DC阻隔电容器的输出；以及至少第二差分输入通道，其经耦合以接收所述第三DC阻隔电容器和所述第四DC阻隔电容器的输出，其中其上的凸块阵列倒装芯片安装到所述接触焊盘，以提供第一差分输出信号和第二差分输出信号。
11.根据权利要求10所述的方法，其中，与所述信号层上的其他迹线的宽度相比，所述变窄的迹线区域至少变窄20％。
12.根据权利要求10所述的方法，其中，与所述信号层上的其他迹线的宽度相比，所述变窄的迹线区域至少变窄40％。
13.根据权利要求10所述的方法，其还包括：
根据所述介电层的介电属性设计所述变窄的迹线区域；
为所述变窄的迹线区域最初预定义迹线宽度；
通过使用二维场模拟器预先模拟到若干迹线宽度候选者内，
使用全波三维模拟器进行验证以确定性能，其中所述介电层的所述介电属性和所述介电层的厚度，连同所述迹线宽度和期望的特性阻抗一起作为参数输入。
14.根据权利要求10所述的方法，其中，所述凸块阵列包括铜柱，所述铜柱在其上具有焊料凸块。
15.根据权利要求10所述的方法，其还包括提供印刷电路板即PCB，以及在所述底部金属层和所述PCB之间提供焊料图案，以及提供为所述封装的半导体器件提供包封的塑封料。
16.根据权利要求10所述的方法，其中，所述IC包括通信器件，所述通信器件包括含有解码器的接收器和包括编码器的发射器。
17.根据权利要求10所述的方法，其中所述第一DC阻隔电容器、所述第二DC阻隔电容器、所述第三DC阻隔电容器和所述第四DC阻隔电容器的电容为0.05μF至2μF。
18.根据权利要求10所述的方法，其还包括将所述变窄的迹线区域定位在接近所述DC阻隔电容器的所述极板的第一接地切割上方，所述DC阻隔电容器的所述极板在所述第一接地切割上方。
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