CN103700639A - 封装组件及其制造方法 - Google Patents
封装组件及其制造方法 Download PDFInfo
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- CN103700639A CN103700639A CN201310755505.4A CN201310755505A CN103700639A CN 103700639 A CN103700639 A CN 103700639A CN 201310755505 A CN201310755505 A CN 201310755505A CN 103700639 A CN103700639 A CN 103700639A
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- 238000000034 method Methods 0.000 claims description 41
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Abstract
公开了一种封装组件及其制造方法。所述封装组件包括:多个半导体芯片,堆叠成包括最底部层面和至少一个上部层面的多个层面;多个层面的封装料,分别用于覆盖相应层面的半导体芯片;以及芯片承载装置,用于安装最底部层面的半导体芯片,其中,至少一个上部层面的半导体芯片的导电路径包括位于前一个层面的封装料的表面上的延伸导电部件,以及至少穿过前一个层面的封装料而从封装组件的底部暴露的通道导电部件。该封装组件可以改善高频性能,以及满足封装组件小型化和多功能化的要求。
Description
技术领域
本发明涉及半导体技术,更具体地涉及其中堆叠半导体芯片的封装组件及其制造方法。
背景技术
随着电子元件的小型化、轻量化以及多功能化的需求的增加,对半导体封装密度的要求越来越高,以达到减小封装尺寸的效果。使用芯片承载装置并且包含多个半导体芯片的的封装组件已经成为新的热点。芯片承载装置例如是引线框。包封在封装料中的半导体芯片通过引线框电连接至外部的其他电子元件。此外,芯片承载装置还可以是电路板。安装在电路板上的半导体芯片通过电路板电连接至外部的其他电子元件。在这种封装组件中,多个半导体芯片的配置及其连接方法对封装组件的尺寸和性能具有至关重要的影响。
图1示出根据现有技术的堆叠封装组件100的分解透视图。在封装组件100中,引线框110包括芯片垫111和多条指状的引脚112。在图1中示出了将两层的半导体芯片安装在引线框110上的情形,其中,下层的半导体芯片120的下表面固定在芯片垫111上,上层的半导体芯片130的下表面采用粘合剂123固定在位于下方的半导体芯片130的上表面上。在半导体芯片120的上表面的边缘处设置焊垫121,然后采用键合线122将焊垫121与引脚112电连接。在半导体芯片130的上表面设置焊垫131,然后采用键合线132将焊垫131与引脚112电连接。封装料160覆盖引线框110、半导体芯片120和130。引线框110的引脚112的外侧部分从封装料160中露出,用于提供封装组件与外部电路(例如电路板)的电连接。
在上述根据现有技术的封装组件100中,为了暴露位于下方的半导体芯片120的上表面的边缘,半导体芯片130的尺寸(长度和宽度中的至少一个)应当小于集成电路120,这对半导体芯片的尺寸引入了附加的限制。
此外,半导体芯片120和130的所有输入端和输出端都需要采用键合线122和132连接到引线框110的引脚112。大量的键合线之间的干扰也会影响半导体芯片的高频性能。此外,在引线框110的引脚112表面需要提供与键合线相应数量的互连区。这不仅导致封装组件的尺寸较大,而且限制了封装组件的触点数量和多功能化。
因此,期望进一步实现堆叠封装组件的小型化、多功能化及改善电性能。
发明内容
有鉴于此,本发明的目的在于可以提供一种改进的封装组件,以解决现有技术中键合线连接对封装组件的尺寸和性能造成不利影响的问题。
根据本发明的第一方面,提供一种封装组件,包括:多个半导体芯片,堆叠成包括最底部层面和至少一个上部层面的多个层面;多个层面的封装料,分别用于覆盖相应层面的半导体芯片;以及芯片承载装置,用于安装最底部层面的半导体芯片,其中,至少一个上部层面的半导体芯片的导电路径包括位于前一个层面的封装料的表面上的延伸导电部件,以及至少穿过前一个层面的封装料而从封装组件的底部暴露的通道导电部件。
优选地,在所述封装组件中,所述通道导电部件的底端提供外部触点。
优选地,在所述封装组件中,所述至少一个层面的半导体芯片的尺寸大于、小于或等于位于其下方层面的半导体芯片的尺寸。
优选地,在所述封装组件中,所述多个半导体芯片的安装方式为选自正面键合和倒装中的一种。
优选地,在所述封装组件中,所述至少一个层面的半导体芯片的安装方式为正面键合,并且采用键合线连接到所述延伸导电部件的表面上。
优选地,在所述封装组件中,所述至少一个层面的半导体芯片的安装方式为正面键合,并且包括导电凸块,所述导电凸块与所述延伸导电部件的表面形成焊料互连。
优选地,在所述封装组件中,所述多个层面的数量为两层或更多层。
优选地,在所述封装组件中,所述芯片承载装置是选自引线框和电路板中的一种。
根据本发明的第二方面提供一种制造封装组件的方法,包括:a)在芯片承载装置上安装最底部层面的半导体芯片;b)采用装料封装覆盖最底部层面的半导体芯片;c)在前一个层面的封装料的表面形成延伸导电部件;d)在延伸导电部件上安装一个上部层面的半导体芯片;以及e)采用装料封装覆盖所述一个上部层面的半导体芯片,其中,在形成所述一个上部层面的半导体芯片的延伸导电部件之前,提供所述一个上部层面的半导体芯片的通道导电部件,所述通道导电部件至少穿过前一个层面的封装料而从封装组件的底部暴露。
优选地,在所述方法中,重复步骤c)至e),以堆叠多个上部层面的半导体芯片。
优选地,在所述方法中,在步骤a)之前,提供用于所有上部层面的半导体芯片的通道导电部件。
优选地,在所述方法中,在步骤a)和b)之间,提供用于第一个上部层面的半导体芯片的通道导电部件。
优选地,在所述方法中,在步骤b)和第一个上部层面的半导体芯片的步骤c)之间,提供用于第一个上部层面的半导体芯片的通道导电部件。
优选地,在所述方法中,在前一个上部层面的半导体芯片的步骤d)和前一个上部层面的半导体芯片的步骤e)之间,提供用于当前一个上部层面的半导体芯片的通道导电部件。
优选地,在所述方法中,在前一个上部层面的半导体芯片的步骤e)和当前一个上部层面的半导体芯片的步骤c)之间,提供用于当前一个上部层面的半导体芯片的通道导电部件。
优选地,在所述方法中,所述提供通道导电部件的步骤包括放置预成形的通道导电部件。
优选地,在所述方法中,所述提供通道导电部件的步骤包括在前一个层面的封装料中开口,以及在开口内形成通道导电部件。
优选地,在所述方法中,采用正面键合或倒装方式安装每一个层面的半导体芯片。
优选地,在所述方法中,步骤c)包括:在前一个层面的封装料的表面镀敷金属层;在金属层上形成抗蚀剂掩模;以及采用抗蚀剂掩模,通过蚀刻将金属层图案化成延伸导电部件。
在本发明的封装组件中,至少一个上部层面的半导体芯片安装在延伸导电部件上,而非安装在下部层面的半导体芯片的表面上,从而两个层面的半导体芯片的尺寸关系可以是任意的。
在至少一个上部层面的半导体芯片中,由延伸导电部件和通道导电部件组成的导电路径代替键合线的至少一部分,从而可以改善高频性能。
进一步地,由于通道导电部件的底端提供外部触点,因此不需要在引线框的引脚的表面上设置用于上部层面的半导体芯片的互连区。而且,上部的半导体芯片的导电凸块与延伸导电部件形成焊料互连,从而通道导电部件本身不需要提供互连区。因此,在本发明的封装组件中,通道导电部件提供的外部触点尺寸小,可以形成密集的触点阵列。本发明的封装组件可以满足封装组件小型化和多功能化的要求。
附图说明
通过以下参照附图对本发明实施例的描述,本发明的上述以及其他目的、特征和优点将更为清楚,在附图中:
图1示出根据现有技术的堆叠封装组件的分解透视图;
图2示出根据本发明的第一实施例的堆叠封装组件的分解透视图;
图3示出根据本发明的第一实施例的堆叠封装组件的底视图;
图4示出根据本发明的第二实施例的堆叠封装组件的分解透视图;
图5示出根据本发明的第三实施例的堆叠封装组件的分解透视图;
图6示出根据本发明的第四实施例的堆叠封装组件的分解透视图;
图7示出根据本发明的第五实施例的堆叠封装组件的制造方法的流程图;以及
图8a至8j示出根据本发明的第五实施例的堆叠封装组件的制造方法实例中各个阶段的俯视图和截面图。
具体实施方式
以下将参照附图更详细地描述本发明的各种实施例。在各个附图中,相同的元件采用相同或类似的附图标记来表示。为了清楚起见,附图中的各个部分没有按比例绘制。为了简明起见,可以在一幅图中描述经过数个步骤后获得的封装结构。
应当理解,在描述封装结构时,当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时,可以指直接位于另一层、另一个区域上面,或者在其与另一层、另一个区域之间还包含其它的层或区域。并且,如果将器件翻转,该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。如果为了描述直接位于另一层、另一个区域上面的情形,本文将采用“直接在……上面”或“在……上面并与之邻接”的表述方式。
在下文中描述了本发明的许多特定的细节,例如封装组件的结构、材料、尺寸、处理工艺和技术,以便更清楚地理解本公开。但正如本领域的技术人员能够理解的那样,可以不按照这些特定的细节来实现本公开。
图2示出根据本发明的第一实施例的堆叠封装组件200的分解透视图。为了清晰而将封装料260和270与封装组件200的其他部分分离表示。作为示例,芯片承载装置例如为引线框210,在封装组件200中以倒装方式安装两层半导体芯片220和230。
半导体芯片220包括内部电路、与内部电路电连接的多个导电凸块221(例如焊料凸块或铜凸块)。半导体芯片220安装在引线框210上。引线框210包括多条指状的引脚211。半导体芯片220下表面的导电凸块221通过焊料与引脚211形成焊料互连。封装料260覆盖引线框210和半导体芯片220。在本申请中,封装料可以选自模塑料、陶瓷或金属。在封装料为金属时,还需要提供附加的绝缘层以实现电隔离。
引线框210的引脚211的底部从封装料260露出,用于提供半导体芯片220与外部电路(例如电路板)的电连接。此外,通道导电部件212(例如铜柱)贯穿封装料260。通道导电部件212的底端从封装料260露出,用于提供半导体芯片230与外部电路(例如电路板)的电连接。
半导体芯片230位于半导体芯片220上方,包括内部电路、与内部电路电连接的多个导电凸块231。半导体芯片230下表面的导电凸块231通过焊料与延伸导电部件222形成焊料互连。延伸导电部件222例如是位于封装料260表面上的图案化金属层。延伸导电部件222从半导体芯片230下方延伸至接触通道导电部件212的顶端,从而与通道导电部件212一起作为半导体芯片230在封装料内的导电路径的一部分。封装料270覆盖延伸导电部件222和半导体芯片230。
图3示出根据本发明的第一实施例的堆叠封装组件200的底视图。如上所述,引线框210的引脚211的底部从封装料260露出,此外,通道导电部件212的底端从封装料260露出。
在根据本发明的堆叠封装组件200中,通道导电部件212的底端可以直接作为外部触点。或者,通道导电部件212的底端可以附加焊料,从而采用焊料作为外部触点。如图3所示,通道导电部件212提供的外部触点尺寸小,可以形成密集的触点阵列。
图4示出根据本发明的第二实施例的堆叠封装组件300的分解透视图。为了清晰而将封装料360和370与封装组件300的其他部分分离表示。作为示例,芯片承载装置例如为引线框310,在封装组件300中以正面键合方式安装半导体芯片320,以倒装方式安装半导体芯片330。
半导体芯片320包括内部电路、与内部电路电连接的多个焊垫321(例如铜焊垫)。引线框310包括芯片垫311和多条指状的引脚312。半导体芯片320的下表面固定在芯片垫311上。在半导体芯片320的上表面设置焊垫321,然后采用键合线322将焊垫321与引脚312电连接。封装料360覆盖引线框310和半导体芯片320。
引线框310的引脚311的底部从封装料360露出,用于提供半导体芯片320与外部电路(例如电路板)的电连接。此外,通道导电部件313(例如铜柱)贯穿封装料360。通道导电部件313的底端从封装料360露出,用于提供半导体芯片330与外部电路(例如电路板)的电连接。
半导体芯片330位于半导体芯片320上方,包括内部电路、与内部电路电连接的多个导电凸块331。半导体芯片330下表面的导电凸块331通过焊料与延伸导电部件322形成焊料互连。延伸导电部件322例如是位于封装料360表面上的图案化金属层。延伸导电部件322从半导体芯片330下方延伸至接触通道导电部件313的顶端,从而与通道导电部件313一起作为半导体芯片330在封装料内的导电路径的一部分。封装料370覆盖延伸导电部件322和半导体芯片330。
与图1所示的现有技术的封装组件100不同,在根据本发明的封装组件300中,针对上部层面的半导体芯片330,采用由延伸导电部件322和通道导电部件313组成的导电路径代替键合线。
图5示出根据本发明的第三实施例的堆叠封装组件400的分解透视图。为了清晰而将封装料460和470与封装组件400的其他部分分离表示。作为示例,芯片承载装置例如为引线框410,在封装组件400中以倒装方式安装半导体芯片420,以正面键合方式安装半导体芯片430。
半导体芯片420包括内部电路、与内部电路电连接的多个导电凸块421(例如焊料凸块或铜凸块)。半导体芯片420安装在引线框410上。引线框410包括多条指状的引脚411。半导体芯片420下表面的导电凸块421通过焊料与引脚411形成焊料互连。封装料460覆盖引线框410和半导体芯片420。
引线框410的引脚411的底部从封装料460露出,用于提供半导体芯片420与外部电路(例如电路板)的电连接。此外,通道导电部件412(例如铜柱)贯穿封装料460。通道导电部件412的底端从封装料460露出,用于提供半导体芯片430与外部电路(例如电路板)的电连接。
半导体芯片430位于半导体芯片420上方,包括内部电路、与内部电路电连接的多个焊垫431(例如铜焊垫)。半导体芯片430的下表面固定在芯片垫422上。在半导体芯片430的上表面设置焊垫431,然后采用键合线432将焊垫431与引延伸导电部件423电连接。芯片垫422和延伸导电部件423例如是位于封装料460表面上的图案化金属层。延伸导电部件423从半导体芯片430下方延伸至接触通道导电部件412的顶端,从而与通道导电部件412一起作为半导体芯片430在封装料内的导电路径的一部分。封装料470覆盖延伸导电部件423和半导体芯片430。
与图1所示的现有技术的封装组件100不同,在根据本发明的封装组件400中,针对上部层面的半导体芯片430,采用由延伸导电部件423和通道导电部件412组成的导电路径代替键合线的一部分。
图6示出根据本发明的第四实施例的堆叠封装组件500的分解透视图。为了清晰而将封装料560和570与封装组件500的其他部分分离表示。作为示例,芯片承载装置例如为引线框510,在封装组件500中以正面键合方式安装两层半导体芯片520和530。
半导体芯片520包括内部电路、与内部电路电连接的多个焊垫521(例如铜焊垫)。引线框510包括芯片垫511和多条指状的引脚512。半导体芯片520的下表面固定在芯片垫511上。在半导体芯片520的上表面设置焊垫521,然后采用键合线522将焊垫521与引脚512电连接。封装料560覆盖引线框510和半导体芯片520。
引线框510的引脚511的底部从封装料560露出,用于提供半导体芯片520与外部电路(例如电路板)的电连接。此外,通道导电部件513(例如铜柱)贯穿封装料560。通道导电部件513的底端从封装料560露出,用于提供半导体芯片530与外部电路(例如电路板)的电连接。
半导体芯片530位于半导体芯片520上方,包括内部电路、与内部电路电连接的多个焊垫531(例如铜焊垫)。半导体芯片530的下表面固定在芯片垫522上。在半导体芯片530的上表面设置焊垫531,然后采用键合线532将焊垫531与引延伸导电部件523电连接。芯片垫522和延伸导电部件523例如是位于封装料560表面上的图案化金属层。延伸导电部件523从半导体芯片530下方延伸至接触通道导电部件513的顶端,从而与通道导电部件513一起作为半导体芯片530在封装料内的导电路径的一部分。封装料570覆盖延伸导电部件523和半导体芯片530。
与图1所示的现有技术的封装组件100不同,在根据本发明的封装组件500中,针对上部层面的半导体芯片530,采用由延伸导电部件523和通道导电部件513组成的导电路径代替键合线的一部分。
在上述的第一至第四实施例中,描述了其中安装两层半导体芯片的封装组件。在替代的实施例中,封装组件包含多于两个层面的半导体芯片中。除了最下部层面的半导体芯片安装在引线框上之外,上部层面的半导体芯片中的至少一个安装在延伸导电部件之上,然后经由通道导电部件实现外部电连接。在本发明的封装组件中,针对上部层面的至少一个半导体芯片,由延伸导电部件和通道导电部件组成的导电路径代替键合线的至少一部分。
图7示出根据本发明的第五实施例的堆叠封装组件的制造方法的流程图,图8a至8j示出根据本发明的第五实施例的堆叠封装组件的制造方法实例中各个阶段的俯视图和截面图。在图8a至8j中,左侧是封装结构的俯视图,右侧是封装结构的截面图。在图8a的俯视图中线AA示出了所有截面图的截取位置,其中线AA横穿引线框的一行引脚以及一行通道导电部件。该方法是用于形成根据本发明的第一实施例的封装组件200的一种示例方法,但在封装组件200中以倒装方式安装三个层面的半导体芯片220、230和240。
该方法开始于提供芯片承载装置(步骤S01),例如引线框210。引线框210例如是冲压成型的铜框架,包括用于在一个表面提供互连区以及在相对的表面提供外部触点的引脚。然后,提供用于第一个上部层面的半导体芯片的通道导电部件212(步骤S02),如图8a所示。通道导电部件212例如是铜柱,将用于第一个上部层面的半导体芯片的导电路径的一部分,并且底端将用于提供外部触点。例如,通道导电部件212是采用冲压等方法形成的预成形部件。优选地,引线框210的底部和通道导电部件212的底端位于同一表面上。例如,在制造工艺中,可以采用放置工具将通道导电部件212放置在所需位置。
然后,将最底部层面的半导体芯片220安装在引线框210上(步骤S03),如图8b所示。半导体芯片220包括内部电路、与内部电路电连接的多个导电凸块221(例如焊料凸块或铜凸块)。半导体芯片220下表面的导电凸块221通过焊料与引脚211形成焊料互连。然后,采用封装料260(例如模塑料)覆盖引线框210和半导体芯片220(步骤S04),如图8c所示。封装料260的上表面例如经过平整,使得通道导电部件212的顶端暴露。也即,通道导电部件212贯穿封装料260。应当注意,封装料260的上表面可以选择性平整,从而形成两个或多个高度的局部表面。在通道导电部件212的顶端暴露的情形下,通道导电部件212的顶端可以低于半导体芯片220的上表面。
然后,在封装料260的上表面镀敷金属以形成金属层。在金属层上形成抗蚀剂掩模,以限定延伸导电部件的图案。采用抗蚀剂掩模,通过蚀刻金属层,完全去除金属层的暴露部分,将金属层图案化成延伸导电部件222(步骤S05),如图8d所示。延伸导电部件222的一端位于将要放置的半导体芯片下方,另一端延伸至至接触通道导电部件212的顶端。
然后,将第一个上部层面的半导体芯片230安装在导电部件212上(步骤S06),如图8e所示。半导体芯片230包括内部电路、与内部电路电连接的多个导电凸块231(例如焊料凸块或铜凸块)。半导体芯片230下表面的导电凸块231通过焊料与延伸导电部件222形成焊料互连。延伸导电部件222与通道导电部件212一起作为半导体芯片230在封装料内的导电路径的一部分。进一步地,判断是否存在下一个上部层面的半导体芯片(步骤S07)。在该实例中将设置第二个上部层面的半导体芯片,因此提供用于半导体芯片240的通道导电部件232(步骤S08),如图8f所示。通道导电部件232例如是铜柱,将用于第二个上部层面的半导体芯片的导电路径的一部分,并且底端将用于提供外部触点。优选地,引线框210的底部和通道导电部件232的底端位于同一表面上。然后,采用封装料270(例如模塑料)覆盖延伸导电部件222、通道导电部件232和半导体芯片230(步骤S09),如图8g所示。封装料270的上表面例如经过平整,使得通道导电部件232的顶端暴露。也即,通道导电部件232贯穿封装料270。
进一步地,判断是否已经完成所有层面的半导体芯片封装(步骤S10)。在该实例中将设置第二个上部层面的半导体芯片,因此重复上述步骤S05至S09,在封装料270的表面形成延伸导电部件233(如图8h所示),在延伸导电部件233上安装半导体芯片240(如图8i所示),采用封装料280(例如模塑料)覆盖延伸导电部件233和半导体芯片240(如图8j所示)。半导体芯片240下表面的导电凸块241通过焊料与延伸导电部件233形成焊料互连。延伸导电部件233与通道导电部件232一起作为半导体芯片240在封装料内的导电路径的一部分。
在上述的第五实施例中,描述了堆叠封装组件的制造方法,其中针对各个上部层面的半导体芯片,在封装前一半导体芯片之前,预先放置该半导体芯片的通道导电部件。
在一个替代的实施例中,可以针对各个上部层面的半导体芯片,在封装前一半导体芯片之后和安装该半导体芯片之前,形成该半导体芯片的通道导电部件,即反转步骤S08和S09的顺序。例如,首先形成穿透所有先前层面的封装料的开口,然后在开口内填充导电材料,从而形成通道导电部件。
在另一个替代的实施例中,代替步骤S02,可以针对所有上部层面的半导体芯片,与引线框同时放置所有的通道导电部件,从而省去随后的步骤S07至S09。
应当说明的是,在本文中,诸如“第一”和“第二”等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来,而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且,术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
依照本发明的实施例如上文所述,这些实施例并没有详尽叙述所有的细节,也不限制该发明仅为所述的具体实施例。显然,根据以上描述,可作很多的修改和变化。本说明书选取并具体描述这些实施例,是为了更好地解释本发明的原理和实际应用,从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。
Claims (19)
1.一种封装组件,包括:
多个半导体芯片,堆叠成包括最底部层面和至少一个上部层面的多个层面;
多个层面的封装料,分别用于覆盖相应层面的半导体芯片;以及
芯片承载装置,用于安装最底部层面的半导体芯片,
其中,至少一个上部层面的半导体芯片的导电路径包括位于前一个层面的封装料的表面上的延伸导电部件,以及至少穿过前一个层面的封装料而从封装组件的底部暴露的通道导电部件。
2.根据权利要求1所述的封装组件,其中所述通道导电部件的底端提供外部触点。
3.根据权利要求1所述的封装组件,其中所述至少一个上部层面的半导体芯片的尺寸大于、小于或等于位于其下方层面的半导体芯片的尺寸。
4.根据权利要求1所述的封装组件,其中所述多个半导体芯片的安装方式为选自正面键合和倒装中的一种。
5.根据权利要求4所述的封装组件,其中所述至少一个层面的半导体芯片的安装方式为正面键合,并且采用键合线连接到所述延伸导电部件的表面上。
6.根据权利要求4所述的封装组件,其中所述至少一个层面的半导体芯片的安装方式为正面键合,并且包括导电凸块,所述导电凸块与所述延伸导电部件的表面形成焊料互连。
7.根据权利要求1所述的封装组件,其中所述多个层面的数量为两层或更多层。
8.根据权利要求1所述的封装组件,其中所述芯片承载装置是选自引线框和电路板中的一种。
9.一种制造封装组件的方法,包括:
a)在芯片承载装置上安装最底部层面的半导体芯片;
b)采用装料封装覆盖最底部层面的半导体芯片;
c)在前一个层面的封装料的表面形成延伸导电部件;
d)在延伸导电部件上安装一个上部层面的半导体芯片;以及
e)采用装料封装覆盖所述一个上部层面的半导体芯片,
其中,在形成所述一个上部层面的半导体芯片的延伸导电部件之前,提供所述一个上部层面的半导体芯片的通道导电部件,所述通道导电部件至少穿过前一个层面的封装料而从封装组件的底部暴露。
10.根据权利要求9所述的方法,其中,重复步骤c)至e),以堆叠多个上部层面的半导体芯片。
11.根据权利要求10所述的方法,其中,在步骤a)之前,提供用于所有上部层面的半导体芯片的通道导电部件。
12.根据权利要求10所述的方法,其中,在步骤a)和b)之间,提供用于第一个上部层面的半导体芯片的通道导电部件。
13.根据权利要求10所述的方法,其中,在步骤b)和第一个上部层面的半导体芯片的步骤c)之间,提供用于第一个上部层面的半导体芯片的通道导电部件。
14.根据权利要求10所述的方法,其中,在前一个上部层面的半导体芯片的步骤d)和前一个上部层面的半导体芯片的步骤e)之间,提供用于当前一个上部层面的半导体芯片的通道导电部件。
15.根据权利要求10所述的方法,其中,在前一个上部层面的半导体芯片的步骤e)和当前一个上部层面的半导体芯片的步骤c)之间,提供用于当前一个上部层面的半导体芯片的通道导电部件。
16.根据权利要求11、12或14所述的方法,其中所述提供通道导电部件的步骤包括放置预成形的通道导电部件。
17.根据权利要求13或15所述的方法,其中所述提供通道导电部件的步骤包括在前一个层面的封装料中开口,以及在开口内形成通道导电部件。
18.根据权利要求9所述的方法,其中采用正面键合或倒装方式安装每一个层面的半导体芯片。
19.根据权利要求9所述的方法,其中步骤c)包括:
在前一个层面的封装料的表面镀敷金属层;
在金属层上形成抗蚀剂掩模;以及
采用抗蚀剂掩模,通过蚀刻将金属层图案化成延伸导电部件。
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US9324633B2 (en) | 2013-12-31 | 2016-04-26 | Silergy Semiconductor Technology (Hangzhou) Ltd. | Multi-level package assembly having conductive vias coupled to chip carrier for each level and method for manufacturing the same |
US10128221B2 (en) | 2014-01-20 | 2018-11-13 | Silergy Semiconductor Technology (Hangzhou) Ltd. | Package assembly having interconnect for stacked electronic devices and method for manufacturing the same |
CN104269385A (zh) * | 2014-10-21 | 2015-01-07 | 矽力杰半导体技术(杭州)有限公司 | 封装组件及其制造方法 |
US9595453B2 (en) | 2015-06-11 | 2017-03-14 | Silergy Semiconductor Technology (Hangzhou) Ltd. | Chip package method and package assembly |
CN110400668A (zh) * | 2018-04-24 | 2019-11-01 | 莫列斯有限公司 | 电子元器件 |
CN110400668B (zh) * | 2018-04-24 | 2022-02-08 | 莫列斯有限公司 | 电子元器件 |
CN114582578A (zh) * | 2018-04-24 | 2022-06-03 | 莫列斯有限公司 | 电子元器件 |
CN110517895A (zh) * | 2019-07-24 | 2019-11-29 | 长安大学 | 一种SiO2-MoS2电极材料、制备方法及应用 |
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US9324633B2 (en) | 2016-04-26 |
US20150187738A1 (en) | 2015-07-02 |
CN103700639B (zh) | 2017-09-01 |
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