CN110534470A - 陶瓷制静电夹头的制造方法 - Google Patents

陶瓷制静电夹头的制造方法 Download PDF

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CN110534470A
CN110534470A CN201811011041.5A CN201811011041A CN110534470A CN 110534470 A CN110534470 A CN 110534470A CN 201811011041 A CN201811011041 A CN 201811011041A CN 110534470 A CN110534470 A CN 110534470A
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松原学
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Abstract

本发明提供了一种陶瓷制静电夹头的制造方法。该方法包含以下步骤：在由密度95％以上的陶瓷或复合陶瓷所构成的介电层中形成作为电极的图案的沟；在该沟中形成金属作为电极图案；在该介电层中形成用于接合的接合层；将该接合层加以研磨并进行活性化处理；以及将具有同样加以研磨并进行活性化处理的接合层的由密度95％以上的陶瓷或复合陶瓷所构成的绝缘体层接合至该介电层。

Description

陶瓷制静电夹头的制造方法
技术领域
本发明涉及陶瓷制静电夹头的制造方法，尤其涉及在半导体或液晶面板的生产中使用的陶瓷制静电夹头的制造方法。
背景技术
以往，就陶瓷制静电夹头的制造方法而言，一般为以下方法：将生胚与涂布有作为电极的钨或钼等高熔点金属膏剂的生胚加以迭层并同时烧成的方法；以及将作为电极的钨或钼等高熔点金属板以陶瓷粉末包夹并通过热压等同时烧成的方法。
专利文献1：日本特开2009-004649和专利文献2：日本特开平07-273164介绍了上述方法。
然而，在上述方法中，高温下的烧成由于陶瓷的收缩，形成的介电层的厚度会产生偏差。此外，在利用生胚的迭层所为的方法中，必须添加为了获得成形体的助剂以及为了获得与高熔点金属之密接性的扩散成分，因此不易获得陶瓷的高纯度化。再者，在利用热压所为的方法中，陶瓷与作为电极的高熔点金属板之界面容易发生空洞，因此电极必须做成网状，此为其限制。
发明内容
有鉴于上述问题，本发明提出一种能将介电层的高纯度化及厚度的偏差抑制到最小的陶瓷制静电夹头的制造方法，包含以下步骤：在密度95％以上的陶瓷或复合陶瓷介电层中形成作为电极的图案的沟；在该沟中形成金属作为电极图案；形成用于接合的活性化接合层；以及接合密度95％以上的陶瓷或复合陶瓷绝缘体层。
根据本发明的一个优选实施方案，该由陶瓷或复合陶瓷所构成的介电层及绝缘体层的体积电阻率在1.0E+8(Ωcm)以上。
根据本发明的另一优选实施方案，接合后的接合层的厚度为合计在50μm以下。
本发明无须已知方法中的用于提升烧结性的添加物，即使在为了具有控制电阻値等功能而加了某些添加物的复合陶瓷中，亦不含其他添加物。
附图说明
图1是根据本发明的方法制作的静电夹头的剖面图。
图2是本发明的方法的各步骤的剖面图。
图3是根据本发明的方法制作的其它静电夹头的剖面图。
图4是根据本发明的方法制作的其它静电夹头的剖面图。
具体实施方式
图1为本发明所制造的静电夹头的剖面图。
如图1所示，静电夹头1包含：介电层2；电极图案3-a；介电层侧的接合层4-a与第1绝缘体层侧的接合层4-b；以及第1绝缘体层5-a。
介电层2是由密度95％以上的陶瓷原料或复合陶瓷原料的烧结体所构成的介电质。就陶瓷原料而言，可使用Al2O3、蓝宝石、Y2O3、AlN、Si3N4等。就烧结体的陶瓷或复合陶瓷的体积电阻率而言，介电层及绝缘体层均可为例如1.0E+8(Ωcm)以上。此外，亦可将为了调整电阻值而添加SiC、TiO2、TiN等的复合材料均用于介电层及绝缘体层。
电极图案3-a是由在介电层2作为图案的沟中埋入的金属等材料所构成的电极。就金属而言，例如使用元素周期表的IVB族至IB族所含的金属或其合金。
介电层侧的接合层4-a及第1绝缘体层侧的接合层4-b用于接合介电层2与第1绝缘体层5-a，接合层4-a和接合层4-b由表面经过活性化的陶瓷所构成。接合层的厚度并不特别限定，但接合后的接合层优选地合计在50μm以下的程度。
第1绝缘体层5-a是由密度95％以上的陶瓷原料或复合陶瓷原料的烧结体所构成的绝缘体。
以下参照图2，说明本发明的陶瓷制静电夹头的制造方法。
将高纯度的陶瓷原料或复合陶瓷原料加以烧结，以预先准备密度95％以上的介电质。
如图2中的(A)所示，将上述烧结的密度95％以上的陶瓷或复合陶瓷的介电质加工成平面度在0.05mm以下，并加工成用于形成期望电极图案的沟，以作为介电层2。
接着，如图2中的(B)所示，在介电层2的加工有上述沟的面形成作为电极的金属层3-b。形成金属的方法可使用镀层、熔喷、CVD或PVD等金属化方法，但宜形成为厚于加工的沟的深度。然后，如图2中的(C)所示，通过将形成有金属层3-b的面加以研磨及抛光而使得仅有形成于沟内的金属露出表面，以作为电极图案3-a。
如图2中的(D)所示，在形成有介电层2的电极图案3的面形成用于与第1绝缘体层5-a接合的介电层侧的接合层4-a。介电层侧的接合层4-a的形成方法可使用CVD或PVD等的薄膜形成手法。介电层侧的接合层4-a的膜厚被形成为大于形成电极图案的面的表面粗度Rz。此外，预先准备与介电层2接合的第1绝缘体层5-a。与介电层2同样地，在第1绝缘体层5-a形成第1绝缘体层侧的接合层4-b。
介电层侧的接合层4-a及第1绝缘体侧的接合层4-b通过抛光调整表面粗度，从而在接合后不产生空隙。表面粗度Ra优选地为0.1μm以下。
将已调整表面粗度的介电层侧的接合层4-a及第1绝缘体侧的接合层4-b通过电浆等而加以活性化。
最后，将经过表面活性化的接合层彼此重迭，通过在低温低负载下接合，从而获得如图2中的(E)所示的内置有电极图案3的静电夹头1。因为可将经过烧结及加工的陶瓷或复合陶瓷彼此在低温低负载下接合，所以能制造出高纯度且抑制介电层厚度的偏差的静电夹头。
此外，如图3所示，在本方法中，在内置静电夹头电极之外，亦可内置作为加热器的金属。在图3的实施例中，先在第1绝缘体层5-a形成加热器图案6，再接合第2绝缘体层5-b。在此种情形下，4-c为加热器侧的接合层，4-d为第2绝缘体层侧的接合层。
再者，可如图4所示地，内置为了冷却吸附对象物而导入至吸附面的冷却气体等的沟。在图4的实施例中，在第1绝缘体层5-a形成有导入沟7，再接合有第2绝缘体层5-b。在此种情形下，4-e为导入沟侧的接合层，4-f为第2绝缘体层侧的接合层。
以上，已说明本发明的实施例及变形，但并非限定。本发明的权利要求，当然包含所属技术领域普通技术人员所能思及的变形、变更。
【符号说明】
1 静电夹头
2 介电层
3-a 电极图案
3-b 金属层
4-a 介电层侧的接合层
4-b 第1绝缘体层侧的接合层
4-c 加热器侧的接合层
4-d 第2绝缘体层侧的接合层
4-e 导入沟侧的接合层
4-f 第2绝缘体层侧的接合层
5-a 第1绝缘体层
5-b 第2绝缘体层
6 加热器图案
7 导入沟

Claims (3)

1.一种陶瓷制静电夹头的制造方法，其特征在于包含以下步骤：
在由密度95％以上的陶瓷或复合陶瓷所构成的介电层中形成作为电极的图案的沟；
在该沟中形成金属作为电极图案；
在该介电层中形成用于接合的接合层；
将该接合层加以研磨并进行活性化处理；以及
将具有同样加以研磨并进行活性化处理的接合层的由密度95％以上的陶瓷或复合陶瓷所构成的绝缘体层接合至该介电层。
2.如权利要求1所述的陶瓷制静电夹头的制造方法，其特征在于，该由陶瓷或复合陶瓷所构成的介电层及绝缘体层的体积电阻率在1.0E+8(Ωcm)以上。
3.如权利要求1或2所述的陶瓷制静电夹头的制造方法，其特征在于，接合后的接合层的厚度为合计在50μm以下。
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