CN110459542B - 半导体装置结构及其形成方法 - Google Patents
半导体装置结构及其形成方法 Download PDFInfo
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- CN110459542B CN110459542B CN201910376157.7A CN201910376157A CN110459542B CN 110459542 B CN110459542 B CN 110459542B CN 201910376157 A CN201910376157 A CN 201910376157A CN 110459542 B CN110459542 B CN 110459542B
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Abstract
本发明公开一种半导体装置结构,包括:栅极结构,设置在基板上,沿第一方向延伸;第一外延结构,设有第一接触结构围绕所述第一外延结构;电源轨,与所述栅极结构和所述第一外延结构间隔开,其中所述电源轨沿第二方向延伸,所述第二方向垂直于所述第一方向;以及第二外延结构,由直接设置在所述电源轨的下方的第二接触结构围绕;其中所述第二外延结构电连接到所述电源轨。通过在电源轨下方形成第二外延结构并且将第二外延结构与电源轨电连接,可以有效地降低电源轨电阻,可以抑制IR压降,并且可以改善电子迁移。
Description
技术领域
本发明涉及半导体技术领域,尤其涉及一种半导体装置结构及其形成方法。
背景技术
半导体集成电路产业经历了快速增长。集成电路设计的发展和材料技术的进步已经产生了几代集成电路。每一代都有比上一代更小,更复杂的电路。在集成电路开发过程中,几何尺寸逐渐减小。
目前已经引入了全栅极(GAA,gate-all around)纳米片(NS,nanosheet)装置以努力通过增加栅极和沟道(channel)耦合,减少截止状态(OFF-state)泄漏电流,并减少短沟道效应(SCE,short-channel effects)来改善栅极控制。全栅极纳米片装置具有围绕信道区域缠绕的栅极堆栈,从而在四个侧面提供通道。全栅极纳米片装置的栅极在硅纳米片中提供通道。
随着集成电路的缩小,晶体管和金属线的尺寸减小。因此,电源轨电阻可能增加,并且IR压降(IR drop)可能导致较差的电路性能和较差的电子迁移(EM,electronmigration)。
尽管现有的纳米片场效应晶体管装置结构通常已经足够用于它们的预期目的,但它们不是在所有方面都完全令人满意的,并需要改进。尤其对于控制电源轨电阻。
发明内容
有鉴于此,本发明提供一种半导体装置结构,以降低电源轨电阻。
根据本发明的第一方面,公开一种半导体装置结构,包括:
栅极结构,设置在基板上,沿第一方向延伸;
第一外延结构,设有第一接触结构围绕所述第一外延结构;
电源轨,与所述栅极结构和所述第一外延结构间隔开,其中所述电源轨沿第二方向延伸,所述第二方向垂直于所述第一方向;以及
第二外延结构,由直接设置在所述电源轨的下方的第二接触结构围绕;
其中所述第二外延结构电连接到所述电源轨。
根据本发明的第二个方面,公开一种半导体装置结构的形成方法,包括:
形成纳米片堆栈,所述纳米片堆栈包括在基板上垂直交替堆栈的第一半导体层和第二半导体层,其中所述基板包括装置区和边界区,并且所述装置区包括沟道区和源极区/漏极区;
去除所述纳米片堆栈并在所述源极区/漏极区和边界区形成外延结构;
去除所述沟道区中的所述纳米片堆栈的第一半导体层并形成围绕所述第二半导体层的栅极堆栈;
形成围绕所述源极区/漏极区和所述边界区中的外延结构的接触结构;以及
直接在位于所述边界区中的外延结构的正上方的形成位于所述边界区中的电源轨,其中所述电源轨与所述边界区中的外延结构电连接,
其中,所述源极区/漏极区中的外延结构和所述边界区中的外延结构彼此间隔开。
根据本发明的第三个方面,公开一种半导体装置结构,包括:
第一栅极结构,设置在基板上;
第一外延结构,设置在第一栅极结构之间;以及
一对第一接触结构,分别设置于第一外延结构的相对的两侧,其中所述一对第一接触结构围绕所述第一外延结构的一部分,所述一对第一接触结构通过第一外延结构彼此间隔开。
本发明提供的半导体封装由于包括:栅极结构,设置在基板上,沿第一方向延伸;第一外延结构,设有第一接触结构围绕所述第一外延结构;电源轨,与所述栅极结构和所述第一外延结构间隔开,其中电源轨沿第二方向延伸,所述第二方向垂直于所述第一方向;以及第二外延结构,由直接设置在所述电源轨的下方的第二接触结构围绕;其中所述第二外延结构电连接到所述电源轨。通过在电源轨下方形成第二外延结构并且将第二外延结构与电源轨电连接,可以有效地降低电源轨电阻,可以抑制IR压降,并且可以改善电子迁移。
附图说明
图1是根据一些实施例的纳米片场效应晶体管装置结构的俯视图。
图2A-1,2A-2,2A-3,2B-1,2B-2,2B-3,2C-1,2C-2,2C-3,2D-1,2D-2,2D-3,2E-1,2E-2,2E-3,2F-1,2F-2,2F-3,2G-1,2G-2,2G-3是根据一些实施例形成纳米片场效应晶体管装置结构的各个阶段的横截面图。
图3A-3D是根据一些其他的实施例形成纳米片场效应晶体管装置结构的各个阶段的横截面图式。
图4A-4E是根据一些其他的实施例的形成纳米片场效应晶体管装置结构的各个阶段的横截面图。
图5是根据一些其他的实施例的纳米片场效应晶体管装置结构的横截面图。
图6是根据一些另外的实施例的纳米片场效应晶体管装置结构的透视图。
图7是根据一些另外的实施例的纳米片场效应晶体管装置结构的俯视图。
图8是根据一些其他的实施例的纳米片场效应晶体管装置结构的横截面图。
图9是根据一些其他的实施例的纳米片场效应晶体管装置结构的横截面图。
图10是根据一些其他的实施例的纳米片场效应晶体管装置结构的横截面图。
具体实施方式
以下公开内容提供了用于实现本发明的不同特征的许多不同实施例或示例。以下描述组件和布置的具体示例以简化本发明。当然,这些仅仅是示例,而不是限制性的。例如,在以下描述中在第二特征之上或之上形成的第一特征可以包括其中第一特征和第二特征以直接接触形成的实施例,还可以包括在第一特征和第二特征之间可以形成附加特征,使得第一和第二特征可以不直接接触的实施例。另外,本发明可以在各种示例中重复参考数字元和/或字母。该重复是为了简单和清楚的目的,并且本身并不表示所讨论的各种实施例和/或配置之间的关系。
此外,本文可以使用空间相对术语,例如“在…下方”,“在…下面”,“下方”,“在…上方”,“上方”等,以便于描述以描述如图所示的一个组件或特征与其他组件或特征的关系。除了图中所示的方向取向之外,空间相对术语旨在涵盖使用或操作中的装置的不同方向取向。装置可以以其他方式重新定向(旋转90度或在其他方向上),并且同样的可以相应地解释在此使用空间相对描述语。
在本文中,术语“大约”,“大概”,“大体上”通常意指在给定值或在定制的20%的范围内,优选在10%的范围内,并且更好地在5%的范围内,或3%或2%的范围内,或者1%,或0.5%的范围内。应该指出的是,这里的数量是一个大体上的数量,这意味着即使没有具体提到大约”,“大概”,“大体上”这些术语,大约”,“大概”,“大体上”的含义仍然是隐含上述含义的
尽管以特定顺序执行的操作讨论了一些实施例,但是可以以另一逻辑顺序执行这些操作。在不同的实施例中,可以在本发明所描述的阶段之前,期间和/或之后提供额外的操作。对于不同的实施例,可以替换或消除所描述的一些阶段。可以将附加特征添加到本发明中的半导体结构。对于不同的实施例,可以替换或消除下面描述的一些特征。
本发明的实施例提供纳米片场效应晶体管装置结构。通过在电源轨下方形成外延(epitaxial)结构并电连接到电源轨,可以降低电源轨电阻并且可以提高电路性能并且可以减轻电子迁移(EM)。此外,通过在外延结构的相对侧上形成接触(contact)结构,提供了在前端(front-end)工艺中产生的电阻器。可以进一步减小晶圆面积和屏蔽(mask)的成本。
图1是根据一些实施例的纳米片场效应晶体管装置结构100的俯视图。纳米片场效应晶体管装置结构100属于半导体装置(或半导体结构,或半导体装置结构,或半导体封装等)中的一部分。图2A-1,2A-2,2A-3,2B-1,2B-2,2B-3,2C-1,2C-2,2C-3,2D-1,2D-2,2D-3,2E-1,2E-2,2E-3,2F-1,2F-2,2F-3,2G-1,2G-2,2G-3是根据一些实施例形成如图1中示出的纳米片场效应晶体管装置结构100的各个阶段的横截面图。图2A-1,2B-1,2C-1,2D-1,2E-1,2F-1,2G-1示出了沿图1中的虚线1-1'截取的横截面图。图2A-2,2B-2,2C-2,2D-2,2E-2,2F-2,2G-2示出了沿图1中的虚线2-2'截取的横截面图。图2A-3,2B-3,2C-3,2D-3,2E-3,2F-3,2G-3示出了沿图1中的虚线3-3'截取的横截面图。
根据一些实施例,如图1所示,纳米片场效应晶体管装置结构100包括装置区10D和边界区10B。装置区10D包括在Y方向上延伸的栅极结构121和在X方向上延伸的纳米片堆栈104。其中,图1中示出了三个栅极结构121,沿X方向上依次排列,并且每个栅极结构121具有在Y方向上的长度。此外三个栅极结构之间可以通过在X方向上延伸的栅极连接结构相互连接起来,可以根据需要使栅极结构之间电连接或断开电连接。栅极结构121上设有栅极接触结构(例如图1中虚线3-3’上的靠近3的方块部分),与栅极结构121电连接,用于为栅极结构121提供栅极电压。纳米片堆栈104在Y方向上的尺寸有一定规则,具体来说,纳米片堆栈104与电源轨132之间具有一定的距离(该距离可根据工艺要求或设计需求调整),并且与栅极接触结构之间具有一定的距离(该距离可根据工艺要求或设计需求调整)。也就是说,纳米片堆栈104在Y方向上来说,位于电源轨132与栅极接触结构之间,Y方向上不会接触到两者(竖直投影方向上也不会有重叠);而纳米片堆栈104在X方向上可以根据需要延伸,可以延伸的很长。装置区10D中的纳米片堆栈104包括栅极结构121下方的沟道区16和栅极结构121之间的源极区/漏极区18(源极区/漏极区18表示此处可能是源极区,也可能是漏极区,可以根据需要设置,例如N型或P型)。边界区10B包括沿X方向延伸的电源轨132和另一个纳米片堆栈104(图未示),其中电源轨132可以为源极区/漏极区18提供电压(例如VDD,VSS)。边界区10B中的另一个纳米片堆栈104(图1未示)直接形成在电源轨132下方并电连接到电源轨132。根据一些实施例,如图1所示,源极区/漏极区18电连接到电源轨132。通过在边界区10B中形成形成在电源轨132的正下方的纳米片堆栈104,并且纳米片堆栈104电连接到电源轨132,可以减小电源轨电阻(或称为连接到电源轨的电阻,或与电源轨连接后的电阻)。
以下描述描述了图1中的纳米片场效应晶体管装置结构100的形成方法。根据一些实施例,提供了如图2A-1,2A-2和2A-3所示的基板102。基板102可以是半导体晶圆(wafer),例如硅晶圆。基板102还可以包括其他基本半导体材料,化合物半导体材料和/或合金半导体材料。基本半导体材料的示例可包括但不限于晶体硅,多晶硅,非晶硅,锗和/或金刚石。化合物半导体材料的示例可包括但不限于碳化硅,氮化镓,砷化镓,磷化镓,磷化铟,砷化铟和/或锑化铟。合金半导体材料的示例可包括但不限于SiGe,GaAsP,AlInAs,AlGaAs,GaInAs,GaInP和/或GaInAsP。在一些实施例中,基板102包括外延层。例如,基板102具有覆盖体半导体的外延层。另外,基板102也可以是绝缘体上半导体(SOI,semiconductor oninsulator)。SOI基板可以通过晶圆键合(bonding)工艺,硅膜转移(silicon filmtransfer)工艺,通过氧注入分离(SIMOX,separation by implantation of oxygen)工艺,其他适用的方法或上述这些组合来制造。在一些实施例中,基板102可以是N型基板。在一些实施例中,基板102可以是P型基板。
接下来,根据一些实施例,如图1,2A-1,2A-2和2A-3所示,在基板102上形成纳米片堆栈104。纳米片堆栈104可以包括垂直交替地堆栈在基板102上的第一半导体层106和第二半导体层108。应当注意,尽管在第2A-1,2A-2和2A-3图中所示的实施例中,存在四层第一半导体层106和三层第二半导体层108,然而第一半导体层106和第二半导体层108的数量并不限于此。
第一半导体层106可以由硅,硅锗,锗锡,硅锗锡,砷化镓,砷化铟镓,砷化铟,其他合适的材料或上述这些组合制成。半导体材料层108可以由硅,硅锗,锗锡,硅锗锡,砷化镓,砷化铟镓,砷化铟,其他合适的材料或上述这些组合制成。在一些实施例中,第一半导体层106和第二半导体材料层108由不同材料制成。例如,第一半导体层106由硅锗制成,第二半导体层108由硅制成。使用不同的材料可以方便在去除一种材料时,不会影响另一种材料,例如去除第一第一半导体层106,而不会影响第二半导体材料层108。
第一半导体材料层106和第二半导体材料层108可以通过外延生长(epitaxialgrowth)工艺形成。第一半导体材料层106和第二半导体材料层108中的每一个可以通过选择性外延生长(SEG,selective epitaxial growth)工艺,化学气相沉积(CVD,chemicalvapor deposition)工艺(例如,气相外延(VPE,vapor-phase epitaxy)工艺,低压CVD(LPCVD,low-pressure CVD)工艺和/或超高真空CVD(UHV-CVD,ultra-high vacuum CVD)工艺)),分子束外延(molecular beam epitaxy)工艺,另一种可应用的工艺或上述这些组合形成。
之后,可以在纳米片堆栈104上形成光阻(photoresist)层(图未示)。可以通过包括光刻(photolithography)工艺和蚀刻(etching)工艺的图案化工艺来图案化光阻层。光刻工艺可包括光阻涂覆(例如,旋涂(spin-on coating)),软烘烤,屏蔽对准,曝光,曝光后烘烤,显影光阻,漂洗和干燥(例如,硬烘烤)。蚀刻工艺可包括干蚀刻工艺或湿蚀刻工艺。
接下来,根据一些实施例,如图2B-1和2B-3所示,在图案化光阻层之后,通过使用图案化的光阻层作为屏蔽来图案化纳米片堆栈104和基板102的上部(upper portion)。因此,可以获得图案化的纳米片堆栈104和图案化的基板102。然后,可以去除图案化的光阻层。
接下来,根据一些实施例,如图2B-1和2B-3所示,形成隔离层110以覆盖纳米片堆栈104和基板102。隔离层110可以由氧化硅,氮化硅,氮氧化硅,氟化物掺杂的硅酸盐玻璃(FSG,fluoride-doped silicate glass)或其他低k电介质材料制成。隔离层110可以通过沉积(deposition)工艺沉积,例如化学气相沉积(CVD)工艺,旋涂玻璃工艺或其他适用的工艺。
根据一些实施例,如图1和2B-1所示,在图案化纳米片堆栈104之后,分别在装置区10D和边界区10B中的源极区/漏极区18中形成单独的纳米片堆栈104。纳米片堆栈104可以由隔离层110分开。
之后,在一些实施例中,平坦化隔离层110以暴露纳米片堆栈104的上表面(图未示)。在一些实施例中,可以通过化学机械抛光(CMP,chemical mechanical polishing)工艺平坦化隔离层110。
接下来,根据一些实施例,如图2C-1和2C-3所示,在隔离层110上执行蚀刻工艺。在一些实施例中,完全去除隔离层110。因此,纳米片堆栈104和基板102被暴露,如图2C-1所示。在一些实施例中,去除隔离层110的一部分。因此,纳米片堆栈104可以被暴露,并且剩余的隔离层110可以围绕基板102的顶部(top portion)。剩余的隔离层110可以是隔离结构,例如围绕顶部的浅沟槽隔离(STI,shallow trench isolation)结构。隔离结构可以配置为防止电性干扰或串扰。
之后,根据一些实施例,如图2C-2和2C-3所示,在纳米片堆栈104的上表面和侧壁上形成虚设(dummy)栅极层112。虚设栅极层112可以限定沟道区16和源极区/漏极区18。如图2C-2所示,根据一些实施例,沟道区16直接位于虚设栅极层112下方,并且源极区/漏极区18位于沟道区16的(两个)相对侧,并且未被虚设栅极层112覆盖。其中虚设栅极层112可以为后续形成栅极结构121提供定位,以便在对应的位置形成栅极结构121。此外,虚设栅极层121也可以为后续工艺中进行蚀刻或去除步骤(例如第2D-2图中去除第一半导体106)提供屏蔽(例如作为阻挡层)。因此虚设栅极层121具有多种功能,方便了制造过程,提高了制造效率。
虚设栅极层112可以包括虚设介电层和虚设闸电极层(图未示)。虚设介电层可以首先共形地(conformally)形成在纳米片堆栈104上。虚设介电层可以由介电材料制成,例如氧化硅,氮化硅,氮氧化硅,具有高介电常数(高k,high-k)的介电材料或上述这些组合。虚设介电层可以通过沉积工艺形成,例如化学气相沉积(CVD),物理气相沉积(PVD,physical vapor deposition),原子层沉积(ALD,atomic layer deposition),高密度等离子体CVD(HDPCVD,high density plasma CVD),金属有机CVD(MOCVD,metal organic CVD),或等离子体增强CVD(PECVD,plasma enhanced CVD)。
在形成虚设介电层之后,可以在虚设介电层上共形地形成虚设闸电极层。虚设闸电极层可以由多晶硅制成。虚设栅极电极层可以通过沉积工艺形成,例如化学气相沉积(CVD),物理气相沉积(PVD),原子层沉积(ALD),高密度等离子体CVD(HDPCVD),金属有机CVD(MOCVD),或等离子体增强CVD(PECVD)。
之后,根据一些实施例,如图2C-1,2C-2和2C-3所示,在虚设栅极层112上执行蚀刻工艺,以通过使用图案化的硬屏蔽层114形成虚设栅极结构112。蚀刻工艺可以是干蚀刻工艺或湿蚀刻工艺。在一些实施例中,通过干蚀刻工艺蚀刻虚设介电层和虚设闸电极层。干蚀刻工艺可包括使用基于氟的蚀刻剂气体,例如SF6,CxFy(其中x和y可以是正整数),NF3或上述这些组合。如图2C-1和2C-2所示,在蚀刻工艺之后,纳米片堆栈104在源极区/漏极区18和边界区10B中暴露出来。
接下来,在一些实施例中,如图2D-1和2D-2所示,去除源极区/漏极区18中的第一半导体层106,并且在虚设栅极层112的侧壁上形成间隔物116(例如在两个相对的侧壁上形成一对间隔物116,当然也可以在一个侧壁上形成间隔物116)。源极区/漏极区18中的第一半导体层106可以通过干蚀刻工艺去除,例如各向异性蚀刻(anisotropic etching)工艺。间隔物116可以由氧化硅,氮化硅,氮氧化硅和/或介电材料制成。间隔物116可以通过化学气相沉积(CVD)工艺,旋涂玻璃工艺或其他合适的工艺形成。在一些实施例中,间隔物116还填充源极区/漏极区18中的第一半导体层106之间的间隙(该填充在图中未示出)。
接下来,根据一些实施例,如图2E-1和2E-2所示,外延结构118形成在源极区/漏极区18和边界区10B中。在一些实施例中,去除源/漏区18中的第二半导体层108,并且通过外延(epi,epitaxial)工艺生长应变(strain)材料,以在源极区/漏极区18和边界区10B中形成外延结构118。另外,应变材料的晶格常数(lattice constant)可以不同于基板102的晶格常数。在一些实施例中,源极区/漏极区18中的第二半导体层108可以未被去除,并且应变材料生长为包覆在源极区/漏极区18和边界区10B中的第二半导体层108。本发明中的应变材料的类型不受限制,应变材料的类型取决于对流动性(mobility)或电阻的改进的需要。在一些实施例中,如图2E-1和2E-2所示,外延结构118包括竖直(或垂直方向)布置的外延层。例如如图2E-1所示,位于源极区/漏极区18的外延结构118包括三个外延层,位于边界区10B的外延结构118包括三个外延层。
外延结构118可以包括Ge,SiGe,InAs,InGaAs,InSb,GaAs,GaSb,InAlP,InP,SiC,SiP,其他合适的材料或上述这些组合。外延结构118可以通过外延生长步骤形成,例如金属有机化学气相沉积(MOCVD),金属有机气相外延(MOVPE,metalorganic vapor phaseepitaxy),等离子体增强化学气相沉积(PECVD,plasma-enhanced chemical vapordeposition)和远程等离子体增强化学气相沉积(RP-CVD,remote plasma-enhancedchemical vapor deposition),分子束外延(MBE,molecular beam epitaxy),氢化物气相外延(HVPE,hydride vapor phase epitaxy),液相外延(LPE,liquid phase epitaxy),氯化物气相外延(Cl-VPE,chloride vapor phase epitaxy)或任何其它合适的方法。
如图2E-1和2E-2所示,根据一些实施例,在形成外延结构118之后,形成层间电介质(ILD,inter-layer dielectric)结构119以覆盖外延结构118。层间电介质结构119可包括由多种介电材料制成的多个层,例如氧化硅,氮化硅,氮氧化硅,磷硅酸盐玻璃(PSG,phosphosilicate glass),硼磷硅酸盐玻璃(BPSG,borophosphosilicate glass),低k(low-k)介电材料和/或其他合适的介电材料。低k介电材料的示例包括但不限于氟化二氧化硅玻璃(FSG),碳掺杂氧化硅,无定形氟化碳,聚对二甲苯,双苯并环丁烯(BCB,bis-benzocyclobutenes)或多酰亚胺。层间电介质结构119可以通过化学气相沉积(CVD),旋涂或其他合适的工艺形成。
此后,根据一些实施例,在层间电介质结构119上执行平坦化工艺,直到露出虚设栅极层112的上表面(该步骤未有图示出)。在平坦化工艺之后,虚设栅极层112的上表面可以与间隔物116和层间电介质结构119的上表面基本齐平。平坦化工艺可以包括研磨工艺,化学机械抛光(CMP)工艺,蚀刻工艺,另一种可应用的工艺或上述这些组合。
接下来,如图2E-2和2E-3所示,根据一些实施例,去除沟道区16中的虚设栅极层112。因此,可以暴露沟道区16中的第一半导体层106和第二半导体层108。可以通过蚀刻工艺去除虚设栅极层112,例如干蚀刻工艺或湿蚀刻工艺。
根据一些实施例,如图2E-2和2E-3所示,在去除沟道区16中的虚设栅极层112之后,去除沟道区16中的第一半导体106。第二半导体层108保留在沟道区16中。沟道区16中的第一半导体106可以通过蚀刻工艺去除,例如各向异性蚀刻工艺。
接下来,根据一些实施例,如图2E-2和2E-3所示,在沟道区16中围绕第二半导体层108形成栅极堆栈120。在一些实施例中,栅极堆栈120填充沟道区16中的第二半导体层108之间的空间。栅极堆栈120可以包括栅极介电层,功函数(work function)层和闸电极层(图未示)。根据一些实施例,如图2E-2和2E-3所示,在形成栅极堆栈120之后,沟道区16中的栅极结构121包括由栅极堆栈120围绕的竖直(或垂直方向)布置的第二半导体层108。栅极结构121包括栅极堆栈120和第二半导体层108,其中栅极堆栈120是导电的,因此可以通过栅极堆栈120的电流控制第二半导体层108是否导电。也就是说沟道区16中的沟道可以指位于第二半导体层108位于沟道区16的部分。
栅极介电层可以包括高k介电层(例如,介电常数大于3.9),例如氧化铪(HfO2)。高k介电层可以包括其他高k电介质,例如LaO,AlO,ZrO,TiO,Ta2O5,Y2O3,SrTiO3,BaTiO3,BaZrO,HfZrO,HfLaO,HfTaO,HfSiO,HfSiON,HfTiO,LaSiO,AlSiO,BaTiO3,SrTiO3,Al2O3,其他适用的高k介电材料,或上述这些组合。可以通过化学气相沉积工艺(CVD)(例如,等离子体增强化学气相沉积(PECVD)工艺,金属有机化学气相沉积(MOCVD)工艺或高密度等离子体化学气相沉积(HDPCVD)),原子层沉积(ALD)工艺(例如,等离子体增强原子层沉积(PEALD,plasma enhanced atomic layer deposition)工艺),物理气相沉积(PVD)工艺(例如,真空蒸发工艺或溅射工艺),其他适用的制程或上述这些组合来形成栅极介电层。
功函数金属层可以围绕栅极介电层形成。功函数金属层可以为晶体管提供期望的功函数以增强装置性能,包括改善阈值电压。功函数金属层可以由金属材料制成,并且金属材料可以包括N-功函数金属或P-功函数金属。对于N型晶体管,N功函数金属可包括钨(W),铜(Cu),钛(Ti),银(Ag),铝(Al),钛铝合金(TiAl),钛铝氮化物(TiAlN),碳化钽(TaC),氮化钽(TaCN),氮化钽(TaSiN),锰(Mn),锆(Zr)或它们的组合。对于P型晶体管,P-功函数金属可包括氮化钛(TiN),氮化钨(WN),氮化钽(TaN),钌(Ru)或它们的组合。
围绕功函数金属层形成闸电极层。闸电极层可以由导电材料制成,例如铝,铜,钨,钛,钽,氮化钛,氮化钽,硅化镍,硅化钴,TaC,TaSiN,TaCN,TiAl,TiAlN或其他适用的材料。可以通过化学气相沉积工艺(例如,低压化学气相沉积工艺,或等离子体增强化学气相沉积工艺),物理气相沉积工艺(例如,真空蒸发工艺或溅射制程),其他适用的制程,或上述这些组合来形成闸电极层。
接下来,根据一些实施例,如图2F-1和2F-2所示,在源极区/漏极区18围绕外延结构118形成第一接触结构122和在边界区10B中围绕外延结构118形成第二接触结构123。第一接触结构122和第二接触结构123可以在同一个工艺中形成。在一些实施例中,第一接触结构122填充外延结构118(位于源极区/漏极区18中的外延结构118)的竖直(或垂直方向)布置的外延层之间的空间。第二接触结构123填充外延结构118(位于边界区10B中的外延结构118)的竖直(或垂直方向)布置的外延层之间的空间。第一接触结构122和第二接触结构123为导电材料,外界的电源可以通过第一接触结构122和第二接触结构123传送到电源轨132(图2G-1所示),这样增加了电流可通过的面积,因此可以进一步减小电阻。
在一些实施例中,在层间电介质结构119中形成开口(图未示),并且在开口中填充导电材料以形成第一接触结构122和第二接触结构123。第一接触结构122和第二接触结构123可以由金属材料(例如,W,Al或Cu),金属合金,多晶硅,其他适用的导电材料,或它们的组合制成。第一接触结构122和第二接触结构123可以通过使用化学气相沉积工艺(CVD),物理气相沉积工艺(PVD,例如,蒸发或溅射),原子层沉积工艺(ALD),电镀工艺,另一种合适的工艺或者它们的组合来形成,以将第一接触结构122和第二接触结构123的导电材料沉积在开口中。然后可以可选地执行化学机械抛光(CMP)工艺或回蚀刻工艺以去除多余的导电材料以形成第一接触结构122和第二接触结构123。设置第一接触结构可以扩大导电信道,从而减小导电电阻。其中第一接触结构122可以位于栅极结构121的(下方)两侧,当然在栅极结构121的正下方也可以有;也即在俯视方向来看,栅极结构121与第一接触结构122的一部分重叠,另外还有超出栅极结构121的部分,并且超出的部分在栅极结构121的相对的两侧。
接下来,根据一些实施例,如图2G-1和2G-2所示,在ILD结构119上方形成介电层124,并且在介电层124中形成金属层126。在一些实施例中,金属层126与形成在源极区/漏极区18中的第一接触结构122和边界区10B中的第二接触结构123直接接触并电连接。介电层124可以由氧化硅制成。可以通过诸如常压CVD(APCVD,atmospheric pressure CVD),低压CVD(LPCVD,low-pressure CVD)和等离子体增强CVD(PECVD,plasma-enhanced CVD)的CVD工艺来沉积介电层124。
金属层126可包括Cu,W,Ag,Ag,Sn,Ni,Co,Cr,Ti,Pb,Au,Bi,Sb,Zn,Zr,Mg,In,Te,Ga,其他适用的金属材料,上述这些的合金或上述这些组合。在一些实施例中,金属层126包括TiN/AlCu/TiN的堆栈结构。可以通过物理气相沉积工艺(例如,蒸发或溅射),原子层沉积工艺(ALD),电镀工艺,其他适用工艺或其组合来沉积金属层126,然后进行化学机械抛光(CMP然后任选地进行处理或回蚀刻处理以去除多余的导电材料。本实施例中,位于源极区/漏极区18中的外延结构118可以通过第一接触结构122(当然还有金属层126,通孔130)电连接到电源轨132;位于边界区10B的外延结构118可以通过第二接触结构123(当然还有金属层126,通孔130)电连接到电源轨132。
接下来,根据一些实施例,如图2G-1所示,在介电层124上形成介电层128,并且在边界区10B中的介电层128中形成(导电)通孔130和电源导轨132。在一些实施例中,电源轨132直接形成在位于边界区10B中的外延结构118上方,并且电连接到位于边界区10B中的外延结构118,其中本实施例中直接并非指直接接触,而是可以认为是直接在外延结构118的正上方设置,不再设置其他结构(当然除了金属层126,介电层124,128等之外)。当然电源轨132直接形成在第二接触结构123的上方,并且电连接到第二接触结构123,其中本实施例中直接并非指直接接触,而是可以认为是直接在外延结构118的正上方设置,不再设置其他结构(当然除了金属层126,介电层124,128等之外)。当然在其他实施例中,电源轨132可以与第二接触结构123直接接触。通过将边界区10B中的外延结构118并联(与位于源极区/漏极区18的外延结构118一起并联)电连接到电源轨132,可以有效地降低电源轨电阻,并且可以抑制IR压降,并且可以改善电子迁移(本实施例中,第二接触结构123也通过金属层126,通孔130等电连接到电源轨132。当然本实施例中,位于源极区/漏极区18的外延结构118也通过通孔130,金属层126等与电源轨132电连接,同时第一接触结构122也通过通孔130,金属层126等与电源轨132电连接)。其中,更详细的说,将第一接触结构122和第二接触结构123并联(源极区/漏极区18的外延结构118和边界区10B中的外延结构118并联),从而降低了经过第一接触结构122和第二接触结构123(源极区/漏极区18的外延结构118和边界区10B中的外延结构118)时的电阻。具体来说,当外界的电压提供给电源轨时(其中电流的流动方向为垂直于荧幕,例如垂直向里或垂直向外),电流可以同时通过第一接触结构122和第二接触结构123(源极区/漏极区18的外延结构118和边界区10B中的外延结构118;当然还经由金属层126,通孔130)传送到电源轨132,从而增加了电流通过的横截面积,降低了传送过程中的电阻(为方便起见简称为降低电源轨电阻),从而抑制了IR压降,改善了电子迁移。更具体的,传统的结构中,仅设有位于源极区/漏极区的外延结构和第一接触结构,因此电流从外界(经过外延结构和第一接触结构)到达电源轨时,电阻较大。而本发明中在形成源极区/漏极区的外延结构和第一接触结构的同时,额外的形成位于边界区的外延结构和第二接触结构,这样在不增加额外的工艺步骤的情况下,显著的减小了电流经过外延结构和接触结构的电阻(即减小了连接到电源轨的电阻),从而抑制了IR压降,该少了电子迁移。因此本实施例中在几乎不增加成本或几乎不增加工艺步骤的情况下,显著的减小了电源轨的电阻。
用于形成通孔130的工艺可以与用于形成第一接触结构122和第二接触结构123的工艺相同或类似。用于形成电源轨132的工艺可以与用于形成金属层126的工艺相同或类似。为了简洁起见,这里不再重复描述这些工艺。在一些实施例中,通孔130和电源轨132分开形成。在一些实施例中,通孔130和电源轨132通过双镶嵌工艺同时形成。
接下来,根据一些实施例,如图2G-3所示,在栅极堆栈120上形成第三接触结构134。第三接触结构134可以用来提供栅极电压。第三接触结构134例如可以是图1中虚线3-3’上的靠近3的方块部分(栅极接触结构)。在一些实施例中,第三接触结构134电连接到栅极堆栈120,以提供栅极电压。用于形成第三接触结构134的工艺与用于形成第一接触结构122和第二接触结构123的工艺相同或类似。为了简洁起见,这里不再重复描述这些工艺。
在如图2G-1所示的一些实施例中,源极区/漏极区18中的外延结构118与边界区10B中的外延结构118之间的空间S(的宽度)处于在源极区/漏极区18中的外延结构118的宽度W1的约5%至约100%的范围内。在如图2G-1所示的一些其它优选实施例中,源极区/漏极区18中的外延结构118与边界区10B中的外延结构118之间的空间S(的宽度或距离)处于在源极区/漏极区18中的外延结构118的宽度W1的约10%至约70%的范围内(包括10%和70%)。如果空间S(的宽度或距离)太大,则电路面积可能太大。如果空间S(的宽度或距离)太小,则源极区/漏极区18中的外延结构118和边界区10B中的外延结构118可能短路,并且可能存在更多缺陷(例如可靠性下降,长时间使用引起短路等问题)。此外源极区/漏极区18中的外延结构118的宽度W1可以基本上等于第一接触结构122的宽度,或者略小于第一接触结构122的宽度。
在如图2G-1所示的一些实施例中,边界区10B中的外延结构118的宽度W2处于电源轨132的宽度WP的约10%至约150%的范围内。在如第2G-1图所示的一些其他优选实施例中,边界区10B中的外延结构118的宽度W2处于电源轨132的宽度WP的约25%至约100%的范围内(包括25%和100%),也就是说边界区10B中的外延结构118的宽度W2小于或等于电源轨132的宽度WP。如果宽度W2太宽,则源极区/漏极区18中的外延结构118和边界区10B中的外延结构118可能短路。如果宽度W2太窄,则电源轨电阻(经过第一接触结构122和第二接触结构123时的电阻)可能仍然很高,达不到降低电阻的效果。边界区10B中的外延结构118的宽度W2可以基本上等于第二接触结构123的宽度,或者略小于第二接触结构123的宽度。此外W1和W2可以相等或不等,可根据需要进行设置。
通过在边界区10B中的电源轨132下方形成额外的外延结构118并且将额外的外延结构118与电源轨132电连接,可以有效地降低电源轨电阻,可以抑制IR压降,并且可以改善电子迁移。此外,通过在竖直(或垂直方向)布置的外延结构118的外延层之间的空间中填充第一接触结构122和第二接触结构123,可以进一步减小电源轨电阻(降低经过第一接触结构122和第二接触结构123时的电阻)。本案中,外延结构一般为半导体材料,导电性能需要受到栅极堆栈的控制,例如在栅极堆栈控制截止时,外延结构的导电性能较差。因此在外延结构外设置第一接触结构和第二接触结构,这样可以方便导电。也就是说,本实施例中第一接触结构和第二接触结构是主要的电流路径。
可以对本发明的实施例进行许多变化和/或修改。第3A-3D图是根据本发明的一些其他实施例的形成纳米片场效应晶体管装置结构200的各个阶段的横截面图。一些工艺或装置与上述实施例中描述的工艺或装置相同或相似,因此这里不再重复描述这些工艺和装置。与上述实施例的不同之处在于,根据一些实施例,如图3B-3D所示,源极区/漏极区18和边界区10B中的外延结构218是单个外延块(single epitaxial block)。
根据一些实施例,如图3A中所示,在形成间隔物116(如图2E-2所示)之后(如图2E-2所示的步骤),通过蚀刻工艺去除源极区/漏极区18(如图2A-2所示)和边界区10B(如图2A-2所示)中的第一半导体层106(如图2A-2所示)和第二半导体层108(如图2A-2所示)。蚀刻工艺可以包括干蚀刻工艺,湿蚀刻工艺,反应离子蚀刻和/或其他合适的蚀刻工艺。干蚀刻工艺可以通过含氧气体,含氟气体(例如CF4,SF6,CH2F2,CHF3和/或C2F6),含氯气体(例如Cl2,CHCl3,CCl4,和/或BCl3),含溴气体(例如HBr和/或CHBR3),含碘气体,其他合适的气体和/或等离子体,或上述这些的组合执行。湿蚀刻工艺可以在湿蚀刻蚀刻剂中进行,湿蚀刻蚀刻剂包括稀释的氢氟酸(DHF),氢氧化钾(KOH),氨,氢氟酸(HF),硝酸(HNO3)和/或乙酸(CH3COOH),其他合适的湿蚀刻蚀刻剂或上述这些的组合。
接下来,根据一些实施例,如图3B所示,在源极区/漏极区18和边界区10B中形成作为单个外延块的外延结构218。形成外延结构218的工艺与用于形成前述实施例中描述的外延结构118(如图2E-1所示)的工艺(如图2E-1所示的步骤)相同或类似。为了简洁起见,这里不再重复描述这些工艺。与竖直(或垂直方向)布置的外延层(结构)的实施例相比,本实施例中外延结构218的单个外延块更容易形成,单个外延块的电阻更低,并且可以通过迁移率增强(mobility enhancement)来提高生产良率(production yield)和晶体管电流。
接下来,根据一些实施例,如图3C所示,围绕源极区/漏极区18中的外延结构218形成第一接触结构122和围绕边界区10B中的外延结构218形成第二接触结构123。在一些实施例中,如图3C所示,外延结构218与基板102间隔开,并且第一接触结构122和第二接触结构123环绕外延结构218以进一步减小电阻。这样可以通过迁移率增强来提高生产良率和晶体管电流。
然后,根据一些实施例,如图3D中所示,在形成于边界区10B中的外延结构218的上方直接形成电源轨132,并且电源轨132电连接到形成在边界区10B中的外延结构218。
通过在边界区10B中的电源轨132下方形成额外的外延结构218并且将该额外的外延结构218和电源轨132电连接,可以有效地降低电源轨电阻,可以抑制IR压降,并且可以改善电子迁移。此外,由于外延结构218是单个外延块,因此可以更容易形成环绕的第一接触结构122和第二接触结构123,并且可以通过迁移率增强来进一步提高生产良率和晶体管电流。具体来说,即降低了经过第一接触结构122和第二接触结构123时的电阻。
可以对本发明的实施例进行许多变化和/或修改。图4A-4E是根据本发明的一些其他实施例的改进的纳米片场效应晶体管装置结构300的各个阶段的横截面图。一些工艺或设备与上述实施例中描述的工艺或设备相同或相似,因此这里不再重复描述这些工艺和设备。与上述实施例的不同之处在于,根据一些实施例,如图4E所示,源极区/漏极区18中的外延结构318和边界区10B中的外延结构318包括不同数量的外延层,也即源极区/漏极区18中的外延结构318的数量与边界区10B中的外延结构318的数量不同。
根据一些实施例,如图4A所示,在回蚀刻隔离层110之后,从隔离层110暴露的源极区/漏极区18中的第一半导体层106和第二半导体层108的数量和从隔离层110暴露的边界区10B中的第一半导体层106和第二半导体层108的数量是不同的。在一些实施例中,边界区10B中的第一半导体层106和第二半导体层108的数量多于源极区/漏极区18中的第一半导体层106和第二半导体层108的数量。因此,根据一些实施例,如图4B所示,在去除从隔离层110暴露的第一半导体层106之后,从隔离层110暴露的源极区/漏极区18中剩下的第二半导体层108的数量和从隔离层110暴露的边界区10B中的左第二半导体层108的数量是不同的。
接下来,根据一些实施例,如图4C所示,在第二半导体层108从隔离层110暴露的位置处形成外延结构318。源极区/漏极区18中的外延结构318的外延层的数量和边界区10B中的外延结构318的外延层的数量可以不同。此外,如图4D和4E所示,围绕极区/漏极区18中的外延结构318形成第一接触结构322,围绕边界区10B中的外延结构318形成第二接触结构323。第二接触结构323大于第一接触结构322,例如第二接触结构323的横截面积(图4C中所能看到的面积即是)大于第一接触结构322的横截面积(图4C中所能看到的面积即是),或者第二接触结构323的体积大于第一接触结构322的体积。总之,第二接触结构323可通过电流的信道大于第一接触结构322可通过电流的通道。因此,第二接触结构323的电阻低于第一接触结构322的电阻。
应当注意,尽管在图4E所示的实施例中,在源极区/漏极区18中的外延结构318具有三个外延层,在边界区10B中的外延结构318具有五个外延层,然而,源极区/漏极区18中的外延结构318的外延层的数量和边界区10B中的外延结构318的外延层的数量不限于此。
通过在边界区10B中的电源轨132下方形成额外的外延结构318并且电连接额外的外延结构318和电源轨132,可以有效地降低电源轨电阻,可以抑制IR下降,并且可以改善电子迁移。此外,由于在电源轨132下方的外延结构318较大,因此可以进一步降低电源轨电阻。具体来说,即降低了经过第一接触结构322和第二接触结构323时的电阻。
可以对本发明的实施例进行许多变化和/或修改。图5是根据本发明的一些其他实施例的改性纳米片场效应晶体管装置结构400的横截面图。一些工艺或设备与上述实施例中描述的工艺或设备相同或相似,因此这里不再重复描述这些工艺和设备。与上述实施例的不同之处在于,如图5所示,根据一些实施例,源极区/漏极区18中的外延结构418包括单个外延块,并且边界区10B中的外延结构418包括竖直(或垂直方向)方向上排列的外延层。此外,本实施例中也可以是源极区/漏极区18中的外延结构418包括竖直(或垂直方向)方向上排列的外延层,并且边界区10B中的外延结构418包括单个外延块。
根据一些实施例,如图5中所示,在形成间隔物116之后,通过蚀刻工艺去除源极区/漏极区18中的第一半导体层106和第二半导体层108。同时,通过蚀刻工艺仅去除边界区10B中的第一半导体层106。因此,可以在源极区/漏极区18中形成单个外延块,并且可以在边界区10B中形成竖直(或垂直方向)布置的外延层。并且在围绕极区/漏极区18中的外延结构418形成第一接触结构422,围绕边界区10B中的外延结构418形成第二接触结构423。由于在边界区10B中的外延结构418的外延层竖直(或垂直方向)布置,所以第二接触结构423填充在竖直(或垂直方向)布置的外延结构418的外延层之间的空间中。而第一接触结构422仅围绕外延结构418的单个外延块。因此,第二接触结构423的横截面积可以大于第一接触结构422的横截面积(或第二接触结构423的体积可以大于第一接触结构422的体积),在边界区10B中的第二接触结构423的电阻可以比在源极区/漏极区18中的第一接触结构422的电阻更小,电源轨电阻可以进一步减小(第一接触结构422和第二接触结构423并联,降低了经过第一接触结构422和第二接触结构423时的电阻)。当然,也有可能第一接触结构422的横截面积可以大于第二接触结构423的横截面积(或第一接触结构422的体积可以大于第二接触结构423的体积),从而第一接触结构422的电阻可以小于第二接触结构423的电阻,这样也可以降低经过第一接触结构422和第二接触结构423时的电阻(第一接触结构422和第二接触结构423并联)。当然,本实施例中可以在源极区/漏极区18中形成竖直(或垂直方向)布置的外延层,并且可以在边界区10B中形成单个外延块;也即源极区/漏极区18中的外延结构包括竖直(或垂直方向)布置的外延层(两个或以上),边界区10B中的外延结构包括单个外延块。
通过在边界区10B中的电源轨132下方形成额外的外延结构418并且将该额外的外延结构418和电源轨132电连接,可以有效地降低电源轨电阻,可以抑制IR压降,并且可以改善电子迁移。由于源极区/漏极区18中的外延结构418是单个外延块,因此可以更容易环绕第一接触结构422,方便制造,并且可以通过迁移率增强来进一步提高生产良率和晶体管电流。此外,由于边界区10B中的外延结构418是竖直(或垂直方向)布置的外延层,所以可以进一步降低电源轨电阻(降低经过第一接触结构422和第二接触结构423时的电阻)。
可以对本发明的实施例进行许多变化和/或修改。图6是根据一些另外的实施例的改进的纳米片场效应晶体管装置结构500的透视图。图7是根据一些另外的实施例的改进的纳米片场效应晶体管装置结构500的俯视图。图8是根据一些其他实施例的改进的纳米片场效应晶体管装置结构500的横截面图。图8示出了沿图7中的虚线8-8'截取的横截面图。一些工艺或设备与上述实施例中描述的工艺或设备相同或相似,因此在此不再重复描述这些过程和设备。与上述实施例的不同之处在于,根据一些实施例,如图6-8所示,在(相邻的)栅极结构121之间(例如相邻的两个栅极结构121之间),一对接触结构522设置在外延结构518的相对侧上(分别设置在外延结构518的相对的两侧上)。接触结构522围绕外延结构518的一部分,并且该一对接触结构522通过外延结构518彼此间隔开。
在先前技术的传统的Hi-R(高阻值)电阻器会给屏蔽带来额外的成本并占用更多的晶圆面积,并且需要更多的工艺形成电阻器。根据一些实施例,如图6-8所示,接触结构522形成在外延结构518的相对侧上。因此,在接触结构522之间的外延结构518处形成电阻器536(例如可以直接)。与传统的电阻器设计相比,可以在没有额外屏蔽的情况下形成位于接触结构522之间的电阻器536,并且可以减小芯片面积。具体的,可以理解为,图3A-3D等所示的实施例中,接触结构(例如第一接触结构122和第二接触结构123)可以将外延结构(例如外延结构218)完全围绕(围绕一圈),而对于图6中的接触结构522,可以在需要形成电阻器的位置,进行处理,从而直接将接触结构522的一部分形成电阻器,这样就使得原本围绕外延结构518一圈的接触结构分为了两个(一对接触结构522),以及电阻器(电阻器536)。当然电阻器连接一对接触结构,电阻器与一对接触结构组合起来还是可以围绕外延结构518一圈。也就是说,在本实施例中,在形成上述实施例所述的接触结构(例如第一接触结构122,322,422,第二接触结构123,323,423)时,可以根据需要将其中一些接触结构形成为如图6所示的电阻器加上一对接触结构的结构(例如图6所示的电阻器536加上一段接触结构522的结构)。采用这种方式,就无需特别的为了形成电阻器而使用额外的屏蔽和额外的工艺步骤,从而减少了工艺步骤,降低了电阻器的制造成本。并且本实施例中可以根据需要调整形成的电阻器的数量和电阻器所在的位置,灵活度更高。
根据一些实施例,如图6和7所示,通过在栅极结构121和与栅极结构121平行的另一栅极结构121P之间形成另一对接触结构522P,在接触结构522P之间形成另一电阻器536P。此外,根据一些实施例,如图7所示,接触结构522在每一端均电连接到接触结构522P。因此,接触结构522和522P之间的电阻器536和536P并联连接。
应当注意,尽管在图6和7所示的实施例中存在三个栅极结构121和121P以及两对接触结构522和522P,但是栅极结构121和121P以及接触结构522和522P的数量不限于此。栅极结构121和121P以及接触结构522和522P的数量可以根据对电阻器的电阻的要求进行修改或更改。
在如图6所示的一些实施例中,外延结构518的宽度W与高度H的比率在约100%至约1000%的范围内(包括100%和1000%)。如果该比率太高,则可能不容易在栅极结构121之间形成外延结构518。如果该比率太低,则可能需要额外的芯片面积来满足电阻要求。根据对电阻器536的电阻的要求,可以适当地修改外延结构518的宽度W。
根据一些实施例,外延结构518可以包括如图8所示的竖直(或垂直方向)布置的外延层。因此,电阻器536的电阻是每个在接触结构522之间并联连接的外延层的并联电阻。通过在一对接触结构522和522P之间形成外延结构518,不使用额外的屏蔽来形成电阻器536。可以通过改变外延结构518的宽度W和并联连接的外延结构518的数量来修改电阻器536的电阻。
可以对本发明的实施例进行许多变化和/或修改。图9是根据一些另外的实施例的改进的纳米片场效应晶体管装置结构600的横截面图。一些工艺或设备与上述实施例中描述的工艺或设备相同或相似,因此这里不再重复对这些工艺和设备的描述。与上述实施例的不同之处在于,根据一些实施例,如图9所示,外延结构618包括单个外延块。
在一些实施例中,通过蚀刻工艺去除栅极结构121之间的第一半导体层106和第二半导体层108并在栅极结构121之间形成单个外延块来形成外延结构618。因此,可以更容易地形成外延结构618,并且可以通过迁移率增强来进一步提高生产良率和晶体管电流。
通过在一对接触结构522之间形成外延结构618,不使用额外的屏蔽来形成电阻器636。可以通过调整外延结构618的宽度W和并联连接的外延结构618的数量来修改电阻器636的电阻。此外,由于外延结构618包括单个外延块,因此可以更容易地形成外延结构618,并且可以通过迁移率增强来进一步提高生产良率和晶体管电流。
可以对本发明的实施例进行许多变化和/或修改。图10是根据一些其他实施例的改性纳米片场效应晶体管装置结构700的横截面图。一些工艺或设备与上述实施例中描述的工艺或设备相同或相似,因此这里不再重复描述这些工艺和设备。与上述实施例的不同之处在于,根据一些实施例,如图10所示,未形成外延结构,并且第二半导体层108留在栅极结构之间作为电阻器736的主体。
通过在一对接触结构522之间形成第二半导体层108,形成电阻器736而不使用额外的屏蔽。可以通过调整第二半导体层108的宽度W和并联连接的第二半导体层108的数量来修改电阻器736的电阻。而且,通过将第二半导体层108作为电阻器736的主体,可以节省生产成本和时间。
如上所述,在本发明中,提供了一种形成纳米片场效应晶体管装置结构的方法。利用在电源轨下方的额外外延结构(以及在外延结构外的接触结构,例如第二接触结构),可以降低电源轨电阻(具体来说,即降低了经过第一接触结构和第二接触结构时的电阻),可以抑制IR压降,并且可以改善电子迁移。利用竖直(或垂直方向)布置的外延层,可以进一步降低电源轨电阻。利用单个外延块,可以通过迁移率增强来提高生产良率并且可以提高晶体管电流。利用形成在外延结构的相对两侧上的接触结构,可以在不使用额外屏蔽的情况下形成电阻器。可以通过改变外延结构的尺寸或者并联连接相同的外延结构来微调电阻器的电阻。
应当注意,尽管在上述实施例中描述了一些益处和效果,但并非每个实施例都需要实现所有益处和效果。
本领域的技术人员将容易地观察到,在保持本发明教导的同时,可以做出许多该装置和方法的修改和改变。因此,上述公开内容应被解释为仅由所附权利要求书的界限和范围所限制。
Claims (11)
1.一种半导体装置结构,其特征在于,包括:
栅极结构,设置在基板上,沿第一方向延伸;
第一外延结构,设有第一接触结构围绕所述第一外延结构;所述第一接触结构与所述栅极结构在俯视方向上重叠;
电源轨,与所述栅极结构和所述第一外延结构间隔开,其中所述电源轨沿第二方向延伸,所述第二方向垂直于所述第一方向;以及
第二外延结构,由直接设置在所述电源轨的下方的第二接触结构围绕,所述第二外延结构与所述电源轨在俯视方向上重叠;
所述第一外延结构和所述第二外延结构之间间隔的距离在所述第一外延结构的宽度的10%至70%的范围内;
其中所述第二外延结构电连接到所述电源轨。
2.如权利要求1所述的半导体装置结构,其特征在于,所述第一外延结构或/和所述第二外延结构包括多个竖直排列的外延层。
3.如权利要求2所述的半导体装置结构,其特征在于,所述第一外延结构和所述第二外延结构包括数量不同或数量相同的外延层。
4.如权利要求1所述的半导体装置结构,其特征在于,所述第一外延结构或/和所述第二外延结构包括单个外延块。
5.如权利要求1所述的半导体装置结构,其特征在于,所述栅极结构包括由栅极堆栈围绕的多个竖直排列的第二半导体层。
6.如权利要求1所述的半导体装置结构,其特征在于,所述第二外延结构的宽度在所述电源轨的宽度的25%至100%的范围内。
7.一种半导体装置结构的形成方法,其特征在于,包括:
形成纳米片堆栈,所述纳米片堆栈包括在基板上垂直交替堆栈的第一半导体层和第二半导体层,其中所述基板包括装置区和边界区,并且所述装置区包括沟道区和源极区/漏极区;
去除所述纳米片堆栈并在所述源极区/漏极区和边界区形成外延结构;
去除所述沟道区中的所述纳米片堆栈的第一半导体层并形成围绕所述第二半导体层的栅极堆栈;
形成围绕所述源极区/漏极区的第一外延结构的第一接触结构和围绕所述边界区中的第二外延结构的第二接触结构;所述第一接触结构与所述栅极堆栈在俯视方向上重叠;以及
直接在位于所述边界区中的外延结构的正上方的形成位于所述边界区中的电源轨,其中所述电源轨与所述边界区中的外延结构电连接,所述边界区中的外延结构与所述电源轨在俯视方向上重叠,
所述第一外延结构和所述第二外延结构之间间隔的距离在所述第一外延结构的宽度的10%至70%的范围内;
其中,所述源极区/漏极区中的外延结构和所述边界区中的外延结构彼此间隔开。
8.如权利要求7所述的半导体装置结构的形成方法,其特征在于,还包括:
在所述源极区/漏极区和所述边界区中形成外延结构之前,形成覆盖沟道区中的纳米片堆栈的虚设栅极。
9.如权利要求8所述的半导体装置结构的形成方法,其特征在于,还包括:
在去除所述源极区/漏极区和所述边界区中的纳米片堆栈之前,在所述虚设栅极的侧壁上形成间隔物。
10.如权利要求8所述的半导体装置结构的形成方法,其特征在于,还包括:
在去除所述沟道区中的纳米片堆栈的第一半导体层之前,去除所述沟道区中的虚设栅极。
11.如权利要求7所述的半导体装置结构的形成方法,其特征在于,所述第一半导体层和所述第二半导体层由不同的材料制成。
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