CN110610903A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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Publication number
CN110610903A
CN110610903A CN201910043132.5A CN201910043132A CN110610903A CN 110610903 A CN110610903 A CN 110610903A CN 201910043132 A CN201910043132 A CN 201910043132A CN 110610903 A CN110610903 A CN 110610903A
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China
Prior art keywords
layer
silicon nitride
contact plug
semiconductor device
air gaps
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CN201910043132.5A
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English (en)
Inventor
江欣哲
黄如立
梁春昇
叶震亚
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN110610903A publication Critical patent/CN110610903A/zh
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Abstract

本公开实施例提供一种半导体装置的制造方法，包括：形成第一和第二氮化硅部件于一接触孔的侧壁表面上，所述接触孔设置于一介电层中和一源极/漏极(S/D)部件上方。此方法还包括形成一接触插塞于接触孔中，所述接触插塞与源极/漏极部件电耦合，移除接触插塞的一顶部以在接触孔中创造一凹部，形成一硬罩幕层于凹部中，以及通过选择性蚀刻移除第一和第二氮化硅部件以分别形成第一和第二气隙。

Description

半导体装置的制造方法
技术领域
本发明实施例涉及半导体装置及其制造方法，且特别涉及金属线之间气隙的形成。
背景技术
半导体工业已历经快速的发展。半导体材料及设计在技术上的进步使得每一代生产的半导体装置变得比先前生产的半导体装置更小且其电路也变得更复杂。在集成电路(integrated circuit；IC)发展的进程中，功能性密度(即，每一个芯片区域中内连接装置的数目)已经普遍增加，而几何尺寸(即，制程中所能创造出最小的元件或线路)则是普遍下降。这种微缩化的过程通常可通过增加生产效率及降低相关成本提供许多利益，但这种微缩化也增加了半导体装置加工和制造上的复杂度。
举例来说，随着装置几何微缩化，内连线(像是源极/漏极(S/D)接触插塞和附近的栅极)之间的寄生电容增加。增加的寄生电容会降低装置性能。为了降低寄生电容，已在源极/漏极(S/D)部件和附近的栅极之间使用具有相对低的介电常数(k)的绝缘材料，像是低介电常数(low-k)介电质和气隙。但是这些材料易碎、不稳定、难以沉积、或对于像是蚀刻、退火、及研磨等制程敏感，且气隙的形成难以控制。由于这些及其他的理由，期望改良内连线之间介电质的制造技术以在集成电路(IC)中维持高的整体晶体管密度的同时，降低寄生电容。
发明内容
根据本发明的一实施例，提供一种半导体装置的制造方法，包括：形成第一和第二氮化硅部件于一接触孔的侧壁表面上，所述接触孔设置于一介电层中和一源极/漏极(S/D)部件上方；形成一接触插塞于接触孔中，所述接触插塞与源极/漏极部件电耦合；移除接触插塞的一顶部以在接触孔中创造一凹部；形成一硬罩幕层于凹部中；以及通过选择性蚀刻移除第一和第二氮化硅部件以分别形成第一和第二气隙。
根据本发明的另一实施例，提供一种半导体装置的制造方法，包括：提供一半导体装置结构，所述半导体装置结构包括：一基板，第一和第二栅极堆叠位于基板上，第一和第二氮化硅部件位于第一和第二栅极堆叠之间，以及一接触插塞位于第一和第二氮化硅部件之间并与第一和第二氮化硅部件接触；蚀刻第一和第二氮化硅部件以分别形成第一和第二气隙，其中第一和第二气隙将接触插塞的侧壁暴露于第一和第二气隙内的空气；以及形成一密封层于接触插塞之上以覆盖第一和第二气隙。
又根据本发明的另一实施例，提供一种半导体装置，包括：一基板；一源极/漏极(S/D)部件，设置于基板上；一金属插塞，设置于源极/漏极部件之上；一栅极堆叠，设置为邻近于金属插塞；一气隙，设置于金属插塞和栅极堆叠之间，其中气隙至少部分地将金属插塞的一侧壁暴露于气隙内的空气中；以及一覆盖层，覆盖所述气隙。
附图说明
本发明实施例可配合以下附图及详细说明阅读以便了解。要强调的是，依照工业上的标准惯例，各个部件(feature)并未按照比例绘制。事实上，为了清楚的讨论，可能任意的放大或缩小各个部件的尺寸。
图1是根据本发明各实施例显示制造一半导体装置的第一方法的流程图。
图2A、图2B、图2C、图2D、图2E、图2F显示图1所示方法的各阶段期间的半导体装置的剖面示意图。
图3A、图3B、图3C图显示图1所示方法的更多阶段期间的半导体装置的剖面示意图。
图4是根据本发明各实施例显示制造一半导体装置的第二方法的流程图。
图5A、图5B、图5C、图5D、图5E显示图4所示方法的各阶段期间的半导体装置的剖面示意图。
图6是根据本发明各实施例显示一半导体装置的部分平面示意图。
附图标记说明：
10、40 方法
12～30、42～50 操作
100 半导体装置
102 基板
106a、106b 源极/漏极(S/D)部件
110、170 层间介电(ILD)层
112 栅极间隔物
116a、116b、116c 栅极堆叠
130a、130b 接触孔
132 侧壁表面
134 底表面
136a、136b 接触插塞
139 障壁层
141 金属填充层
142a、142b、142c、142d 氮化硅部件
150a、150b、150c、150d 气隙
152 密封层
154 金属氮化物层
156 蚀刻停止层
160 硬罩幕层
A’、B-B’ 线
具体实施方式
以下内容提供许多不同的实施例或是例子来实行本发明实施例的不同部件。以下描述具体的元件及其排列的例子以简化本发明实施例。当然这些仅是例子且不该以此限定本发明实施例的范围。例如，在描述中提及第一个部件形成于第二个部件“之上”或“上”时，其可能包括第一个部件与第二个部件直接接触的实施例，也可能包括两者之间有其他部件形成而没有直接接触的实施例。另外，本发明的不同实施例中可能重复使用参照符号及/或标记。这些重复是为了简化与清晰的目的，并非用以限定所讨论的不同实施例及/或结构之间有特定的关系。此外，为了简化与清晰的目的，可以不同比例任意绘制各个部件。
此外，其中用到与空间相关的用词，例如：“在……下方”、“下方”、“较低的”、“上方”、“较高的”、及其类似的用词是为了便于描述附图中所示的一个元件或部件与另一个元件或部件之间的关系。这些空间关系词是用以涵盖附图所描绘的方位之外的使用中或操作中的装置的不同方位。例如，如果将附图中的装置翻转，则被描述为在其他元件或部件“下方”或“在……下方”的元件将被转向为在其他元件或部件“上方”。因此，示例性用词“下方”可涵盖“上方”和“下方”两种方位。装置可能被转向不同方位(旋转90度或其他方位)，则其中使用的空间相关形容词也可相同地照着解释。
本发明实施例一般涉及半导体装置及其制造方法，且更特别涉及金属线(像是接触插塞和邻近栅极)之间气隙的形成。随着鳍状场效晶体管(FinFET)的技术不断朝向更小的技术节点进展(像是16纳米、10纳米、7纳米、5纳米、及以下)，缩小鳍片间距显着地限制了可用于栅极堆叠与连接至源极/漏极(S/D)部件的邻近接触插塞之间的材料。为了最小化栅极堆叠和接触插塞之间的寄生电容，气隙可提供帮助，因为空气比其他介电材料具有较低的介电常数(k＝1)。但是，当气隙在接触插塞的前形成时，气隙倾向于接近栅极堆叠且远离接触插塞。此外，后续形成接触插塞容易损坏气隙。例如，当形成一接触插塞时，如果用于图案化接触插塞的罩幕未与下层元件完美地对准，则可能发生重叠移位(overlay shift)。由于重叠移位，接触孔的位置可能非常接近邻近的栅极堆叠。在这种情况下，蚀刻接触孔将暴露出已被密封的气隙，且经暴露的气隙可能被接触插塞部分或完全地填充。如此一来，气隙将失去其降低寄生电容的目的。
本发明实施例通过在形成接触插塞之后(不在其之前或同时)再形成气隙来避免这些问题。例如，通过先在接触孔中沉积氮化硅部件，然后形成夹在氮化硅部件之间的接触插塞，并接着选择性蚀刻氮化硅部件以形成气隙。通过氮化硅部件材料与其他周围材料相较之下的蚀刻选择性来实现氮化硅部件的选择性移除。此处所公开的气隙的插塞后形成(post-plug formation)导致气隙延伸于邻近栅极堆叠的顶表面上方。其结果，可有效地降低栅极堆叠和接触插塞之间的寄生电容。此外，所公开的气隙与源极/漏极(S/D)部件上方的接触插塞直接接触，从而将接触插塞的侧壁暴露于空气。当接触插塞传导电流时，这种空气暴露有助于散热。
可使用各种制造方法来实现此处公开的气隙的插塞后形成。图1是根据本发明实施例各方面显示制造一半导体装置(或装置结构)100的第一方法10。方法10仅仅为示例，并且除了权利要求中明确记载的内容之外，方法10并不意图限定本发明实施例。可在方法10之前、期间、和之后提供额外的操作，且可在方法10的其他实施例中取代、删除、或移动所述的一些操作。在下述的讨论中，参照图2A～图2F和图3A～图3C，根据本发明不同实施例在各个制造阶段中半导体装置100的部分或整体的局部示意剖面图描述方法10。
半导体装置100可为或包括鳍状场效晶体管(FinFET)装置(鳍式(fin-based)晶体管)，其可包括在微处理器、存储器单元、及/或其他集成电路(IC)装置中。半导体装置100可为在集成电路(IC)芯片、系统单芯片(system on chip；SoC)、或前述的一部分的制程期间所制造的中间装置，其包括各种被动和主动微电子装置，像是电阻器、电容器、电感器、二极管、p-型场效晶体管(p-type field effect transistors；PFETs)、n-型场效晶体管(n-type field effect transistors；NFETs)、金属氧化物半导体场效晶体管(metal-oxidesemiconductor field effect transistors；MOSFET)、互补式金属氧化物半导体(complementary metal-oxide semiconductor；CMOS)晶体管、双极性晶体管(bipolartransistors)、高压晶体管、高频晶体管、其他合适的元件、或前述的组合。为了清晰以更易于理解本发明的发明概念的目的，已简化了图2A～图2F。可在半导体装置100中添加额外的部件，并且可在半导体装置100的其他实施例中取代、修饰、或删除以下描述的一些部件。
在操作12处，方法10提供或被提供起始半导体装置100。如图2A所示，起始半导体装置100包括元件像是基板102、源极或漏极(source or drain；S/D)部件106a和106b、层间介电(inter-layer dielectric；ILD)层110、栅极间隔物112、栅极堆叠116a、116b和116c、以及接触孔130a和130b。半导体装置100可包括此处附图中未显示的其他元件。以下将进一步描述半导体装置100的元件。
基板102是本实施例中的一半导体基板(例如，硅晶圆)。或者，基板102可包括另一种元素半导体，像是锗；化合物半导体，包括碳化硅、氮化镓、砷化镓、磷化镓、磷化铟、砷化铟、和锑化铟；合金半导体，包括硅锗(SiGe)、砷磷化镓(gallium arsenide phosphide)、磷化铝铟(aluminum indium phosphide)、砷化铝镓(aluminum gallium arsenide)、砷化镓铟(gallium indium arsenide)、磷化镓铟(gallium indium phosphide)、和砷磷化镓铟(gallium indium arsenide phosphide)；或前述的组合。基板102可为绝缘体上半导体(semiconductor-on-insulator)基板，例如绝缘体上硅(silicon-on-insulator；SOI)基板、绝缘体上硅锗(silicon germanium-on-insulator；SGOI)基板、或绝缘体上锗(germanium-on-insulator；GOI)基板。可利用氧殖入隔离(separation by implantationof oxygen；SIMOX)、晶圆接合、及/或其他合适的方法来制造绝缘体上半导体基板。取决于半导体装置100的设计需求，基板102可包括各种掺杂区域(未显示)。在一些实施方案中，基板102包括掺杂有像是硼、铟、其他p-型掺杂物、或前述组合的p-型掺杂物的p-型掺杂区域(例如，p-型阱)。在一些实施方案中，基板102包括掺杂有像是磷、砷、其他n-型掺杂物、或前述组合的n-型掺杂物的n-型掺杂区域(例如，n-型阱)。在一些实施方案中，基板102包括由p-型掺杂物和n-型掺杂物的组合所形成的掺杂区域。各个掺杂区域可直接形成在基板102上及/或基板102中，例如，提供p-阱结构、n-阱结构、双阱结构、凸起结构、或前述的组合。可进行离子植入(ion implantation)制程、扩散制程、及/或其他合适的掺杂制程以在基板102中形成各种掺杂区域。
源极/漏极(S/D)部件106a和106b设置于基板102上，并且可包括用于n-型场效晶体管(NFET)的n-型掺杂硅、用于p-型场效晶体管(PFET)的p-型掺杂硅锗、或其他合适的材料。可通过在邻近栅极堆叠116a～116c的主动区域中蚀刻出凹陷(depressions)，然后在凹陷中外延(磊晶)生长半导体材料来形成源极/漏极(S/D)部件106a和106b。外延生长的半导体材料可经原位(in-situ)掺杂或非原位(ex-situ)掺杂有适当的掺杂物。源极/漏极(S/D)部件106a和106b可具有任何合适的形状，并且可完全或部分地埋入(embedded)主动区域中。例如，取决于外延生长的量，源极/漏极(S/D)部件106a和106b可在鳍片的顶表面上方、上、或下方隆起(rise)。
层间介电(ILD)层110设置于基板102上。层间介电(ILD)层110可包括四乙氧基硅烷(tetraethylorthosilicate；TEOS)氧化物、未经掺杂的硅酸盐玻璃、或经掺杂的氧化硅像是硼磷硅酸盐玻璃(borophosphosilicate glass；BPSG)、熔融石英玻璃(fused silicaglass；FSG)、磷硅酸盐玻璃(phosphosilicate glass；PSG)、硼掺杂硅玻璃(boron dopedsilicon glass；BSG)、及/或其他合适的介电材料。可通过等离子体辅助化学气相沉积(plasma-enhanced CVD；PECVD)、流动式化学气相沉积(flowable CVD；FCVD)、或其他合适的方法来形成层间介电(ILD)层110。
栅极堆叠116a～116c可各自包括底部的栅极介电层和设置于栅极介电层上的栅极电极层。栅极介电层可包括SiO2或高介电常数(high-k)介电材料，像是氧化铪硅(HfSiO)、氧化铪(HfO2)、氧化铝(Al2O3)、氧化锆(ZrO2)、氧化镧(La2O3)、氧化钛(TiO2)、氧化钇(Y2O3)、钛酸锶(SrTiO3)、或前述的组合。可利用化学气相沉积(chemical vapordeposition；CVD)、物理气相沉积(physical vapor deposition；PVD)、原子层沉积(atomiclayer deposition；ALD)、及/或其他合适的方法来沉积栅极介电层。栅极堆叠116a、116b、或116c的栅极电极层可包括多晶硅及/或一个或多个金属层。例如，栅极电极层可包括功函数金属层、导电障壁层、和金属填充层。取决于装置类型，功函数金属层可为p-型或n-型功函数层。p-型功函数层可包括氮化铝钛(TiAlN)、氮化钛(TiN)、氮化钽(TaN)、钌(Ru)、钼(Mo)、钨(W)、铂(Pt)、另一种合适的金属、或前述的组合。n-型功函数层可包括钛(Ti)、铝(Al)、碳化钽(TaC)、碳氮化钽(TaCN)、氮化硅钽(TaSiN)、氮化钛铝(TiAlN)、氮化硅钛(TiSiN)、另一种合适的金属、或前述的组合。金属填充层可包括铝(Al)、钨(W)、钴(Co)、及/或其他合适的材料。可利用像是化学气相沉积(CVD)、物理气相沉积(PVD)、电镀、及/或其他合适制程来沉积栅极电极层。栅极堆叠116a、116b、或116c可还包括栅极介电层下方的界面层。界面层可包括像是SiO2或SiON的介电材料，并且可通过化学氧化、热氧化、原子层沉积(ALD)、化学气相沉积(CVD)、及/或其他合适的方法来形成。
每一个栅极堆叠可耦合至邻近的栅极间隔物112。在一些实施例中，栅极间隔物112被认为是其邻近栅极堆叠的侧壁。每一个栅极间隔物112可为单层或多层结构。例如，栅极间隔物112可包括介电材料，像是氧化硅、氮化硅、氮氧化硅、其他介电材料、或前述的组合。可通过沉积(例如，CVD或PVD)和蚀刻制程来形成栅极间隔物112。
可通过任何合适的制程来形成栅极堆叠116a～116c，例如先栅极(gate-first)制程和后栅极(gate-last)制程。在示例性的先栅极制程中，在形成源极/漏极(S/D)部件106a和106b之前，沉积并图案化各个材料层以成为栅极堆叠116a～116c。在示例性的后栅极制程(也称为栅极替换制程)中，首先形成暂时性栅极结构(有时称为“虚设”栅极)。然后，在形成晶体管源极/漏极(S/D)部件106a和106b之后，移除暂时性栅极结构并由栅极堆叠116a～116c取代。在图2A所示的实施例中，栅极堆叠116a、116b、或116c可设置于晶体管的通道区域之上，以做为栅极端子(gate terminal)。举例而言，尽管未显示于图2A中，但金属插塞可设置于这样的栅极堆叠上并与这样的栅极堆叠电耦合，以将可调节的电压施加于栅极堆叠。电压可控制源极/漏极(S/D)部件(像是106a和106b)之间的通道区域。
如图2A所示，接触孔130a位于栅极堆叠116a和116b之间，而接触孔130b位于栅极堆叠116b和116c之间。接触孔130a和130b分别暴露出源极/漏极(S/D)部件106a和106b的顶部。每一个接触孔包括侧壁表面132和底表面134，其中底表面134实际上与下方源极/漏极(S/D)部件的顶表面相同。
在操作14处，方法10(图1)形成氮化硅部件于接触孔的侧壁表面132上。依然参照图2A，氮化硅部件142a和142b形成于接触孔130a中，而氮化硅部件142c和142d形成于接触孔130b中。氮化硅部件的形成涉及多个步骤。在第一步骤中，形成氮化硅层于半导体装置100上，以例如至少覆盖接触孔130a和130b，但也可覆盖半导体装置100的最顶层表面。可通过一或多个方法像是等离子体辅助化学气相沉积(PECVD)、原子层沉积(ALD)、及/或其他合适的沉积或氮化制程来形成氮化硅层。例如，氮化硅层可为一薄层，其跨过半导体装置100的顶表面具有一般(generally)顺应性的厚度。除了氮化硅之外，该层还可包括其他合适的材料，像是掺杂碳。在一些实施例中，可以执行多个沉积循环以便达到氮化硅层的目标厚度。在第二步骤中，选择性蚀刻氮化硅层(例如，使用罩幕辅助的干蚀刻)以移除位于底表面134和层间介电(ILD)层110的最顶层表面上的部分。其结果，氮化硅部件142a～142d保留在侧壁表面132上。因为要暴露出源极/漏极(S/D)部件106a和106b的顶表面，所以进行选择性蚀刻制程以蚀刻氮化硅层位于底表面134上的部分。此外，选择性蚀刻制程也可“薄化”氮化硅部件142a～142d(移除厚度部分)以开拓更多的横向空间，用于后续接触插塞的沉积。在一些实施例中，控制操作14以实现氮化硅部件142a～142d的目标尺寸(例如，高度和宽度)。氮化硅部件142a～142d的尺寸可有效地控制气隙的尺寸，气隙的尺寸是通过移除氮化硅部件142a～142d而形成(于下文描述)。
应注意的是，由于半导体装置100是三维结构(在此显示出其剖面图)，氮化硅部件142a和142b实际上可代表相同的虚设部件，但为了清楚起见，故在剖面图中将它们分开标记。相同的考量适用于其他标号，像是氮化硅部件142c和142d(以及气隙150a～150b、与气隙150c和150d，这些全都将在下文中进一步描述)。
接着，方法10将一种或多种导电材料填充到接触孔130a和130b中以分别形成第一和第二接触插塞。接触插塞在图2F中标记为136a和136b，但是它们的形成经过图2C～图2F中所示的数个步骤，因为每一个接触插塞包括一障壁层139和位于障壁层139之上和其附近的金属填充层141，如图2F所示。
具体地，在操作16处，方法10形成障壁层139于半导体装置100之上(图2B)。障壁层139至少覆盖接触孔130a和130b，但是也可覆盖半导体装置100的最顶层表面，如图2B所示。障壁层139包括像是TaN或TiN的金属氮化物层。可通过物理气相沉积(PVD)、化学气相沉积(CVD)、原子层沉积(ALD)、电镀、或其他合适的方法来形成障壁层139。在一实施例中，原子层沉积(ALD)制程用以在半导体装置100之上均匀地沉积障壁层139。障壁层139可帮助避免待形成的金属填充层141穿透至周围的硅或氧化物区域中。在一些实施例中，障壁层139还包括位于金属氮化物层下方的金属硅化物层。例如，方法10首先沉积一金属层(使用与金属氮化物层相同的金属，像是Ta或Ti)，然后在升高的温度下进行退火制程。在退火期间，金属层与源极/漏极(S/D)部件106a和106b中的半导体材料(例如硅)反应，以形成金属硅化物层于其上。金属硅化物层可包括硅化钽、硅化钛、或其他合适的硅化物(silicidation)或锗硅化物(germanosilicidation)。金属硅化物层可覆盖源极/漏极(S/D)部件106a和106b的重掺杂区域，并且在一些情况下，金属硅化物层被视为源极/漏极(S/D)部件106a和106b的一部分。
在操作18处，方法10(图1)蚀刻或“拉回(pulls back)”障壁层139以部分地暴露出氮化硅部件142a～142d(图2C)。具体地，方法10选择性移除设置于层间介电(ILD)层110最顶层表面上以及接触孔130a和130b较高的侧壁部分上的部分障壁层139。可利用干蚀刻或湿蚀刻制程。移除足够的障壁层139，使得氮化硅部件142a～142d的顶部暴露于大气环境(ambient environment)。
在操作20处，方法10(图1)进行表面清洁和处理程序以清洁和处理障壁层139的表面以及氮化硅部件142a～142d露出的表面，以移除其上的化学物质和残留物(图2D)。可利用任何合适的方法及/或材料进行表面清洁和处理。在一实施例中，使用含有盐酸(HCl)和有机清洁剂的溶液进行深度清洁。如图2D所示，清洁和处理程序也可“薄化”障壁层139的较高部分，造成障壁层139的侧壁表面132上的锥形(tapered)厚度轮廓。障壁层139的锥形厚度轮廓使得其厚度从顶部到底部逐渐增加。例如，虽然障壁层139以一般(generally)均匀的厚度轮廓开始(图2C)，但是在清洁和处理程序之后，障壁层139的较高部分可明显地比其较低部分薄(图2D)。在一些实施例中，障壁层139的顶表面的厚度小于障壁层139的底部厚度(但仍然是底部厚度的50％或更多(例如，60％、70％))。
在操作22处，方法10(图1)形成金属填充层141于半导体装置100之上(图2E)。金属填充层141可包括钴(Co)、钨(W)、铂(Pt)、银(Ag)、镍(Ni)、铜(Cu)、钯(Pd)、前述的组合、或其他合适的材料。可通过物理气相沉积(PVD)、化学气相沉积(CVD)、原子层沉积(ALD)、电镀、或其他合适的方法来形成金属填充层141。在一些实施例中，在沉积金属填充层141时，利用物理气相沉积(PVD)和化学气相沉积(CVD)制程的组合。例如，可先利用物理气相沉积(PVD)制程来沉积薄钴层作为种子层(以较慢的沉积速率但具有较好的品质)，接着利用化学气相沉积(CVD)制程来沉积厚钴层做为块状层(bulk layer)(以较快的沉积速率但可能不具有与钴种子层相同的品质)。当沉积种子层时，控制其厚度使其不会阻挡弯曲轮廓区域中块状层的沉积。如图2E所示，金属填充层141通过障壁层139与源极/漏极(S/D)部件106a和106b电耦合。
在操作24处，方法10(图1)利用化学机械平坦化(chemical mechanicalplanarization；CMP)制程平坦化金属填充层141，其移除金属填充层141的顶部(图2F)。每一个接触插塞136a和136b包括障壁层139和金属填充层141，如图2F所示。接触插塞有时也称为导孔(via)、介层插塞(via plug)、金属接触(metal contact)、或金属插塞(metalplug)。为了促进后续气隙的形成，在一些实施例中，化学机械平坦化(CMP)制程足够长以确保氮化硅部件142a～142d的暴露。
在操作24之后，可利用各种方法形成气隙。图3A～图3C显示第一气隙形成方法，且图5A～图5E显示第二气隙形成方法。以下依序描述两种方法。
在操作26处，方法10(图1)移除氮化硅部件142a～142d以分别形成气隙150a～150d(图3A)。具体地，气隙150a形成于接触插塞136a和邻近的栅极堆叠116a之间以降低其间的第一电容，气隙150b形成于接触插塞136a和邻近的栅极堆叠116b之间以降低其间的第二电容，气隙150c形成于接触插塞136b和邻近的栅极堆叠116b之间以降低其间的第三电容，且气隙150d形成于接触插塞136b和邻近的栅极堆叠116c之间以降低其间的第四电容。电容降低是因为空气具有约1的介电常数(k)，其低于其他介电材料。在一些实施例中(例如，当没有重叠移位时)，气隙150a～150d具有大致相同的尺寸，且第一、第二、第三、和第四电容大致相等。但是如果存在重叠移位时，则气隙150a～150d可具有不同的尺寸，从而导致不同的相应电容。接触插塞136a两侧不相等的电容可能不均匀地影响相关的电路，但由于此处的第一和第二电容都降低了，所以它们对电路的整体影响也减少了。
应注意的是，此处所公开的方法10是在形成接触插塞136a和136b之后再形成气隙150a～150d。这不同于传统的气隙形成方法，传统的气隙形成方法在形成其相应的接触孔(和接触插塞)之前形成气隙。这种顺序变化是违反直觉的，举例而言，因为气隙的插塞后形成(post-plug formation)带来了独特的蚀刻选择性考量，且传统方法无法实现这样的蚀刻选择性。但是，如此处所公开的，气隙的插塞后形成带来各种益处，像是在存在重叠移位时降低了栅极堆叠与邻近的源极/漏极(S/D)部件之间短路的风险。这又提高了装置的可靠性并实现了更高的击穿电压(breakdown voltage)。此外，由于通过调节氮化硅部件142a～142d的高度及/或宽度而精确地控制气隙的体积，因此可有效地控制栅极堆叠和接触插塞之间的寄生电容。可在没有潜在气隙损坏的情况下实现最适化的交流/直流(AC/DC)增益。再者，与气隙的顶表面低于栅极堆叠的传统方法不同，此处公开的气隙150a～150d延伸于栅极堆叠116a～116c的顶表面上方。较高的气隙150a～150d有助于降低了构成寄生电容的一部分的边缘电容(fringe capacitance)。举例而言，气隙150a降低了接触插塞136a的较高部分和栅极堆叠116a的较高部分之间的边缘电容。其结果，邻近的栅极堆叠和接触插塞之间的整体寄生电容进一步降低。
在一实施例中，氮化硅部件142a～142d的材料相对于障壁层139、层间介电(ILD)层110、和金属填充层141具有高蚀刻选择性，使得氮化硅部件142a～142d可被完全移除而大致上(substantially)不影响其他周围的层。在一实施例中，氮化硅部件142a～142d在蚀刻过程中比起与氮化硅部件142a～142d接触的其他材料可以快至少10倍(或20倍、或50倍)的速率被移除。这种蚀刻选择性取决于氮化硅部件142a-142d、障壁层139、层间介电(ILD)层110、和金属填充层141的材料选择。因此，以组合的方式考量这些层的材料组成。在一实施例中，氮化硅部件142a～142d包括氮化硅；障壁层139包括Ti和TiN；层间介电(ILD)层110包括低介电常数(low-k)材料像是氧化硅(SiO2)、碳氮化硅(SiCN)、及/或碳氧化硅(SiCO)；而金属填充层141包括钴(Co)及/或钨(W)。蚀刻选择性是基于对相同蚀刻剂的不同反应性。
在操作26处的选择性蚀刻制程可包括干蚀刻、湿蚀刻、反应离子蚀刻(reactiveion etching；RIE)、及/或其他合适的制程。在一实施例中，干蚀刻与含氟气体一起使用，所述含氟气体包括六氟化硫(SF6)、四氟化碳(CF4)、三氟化氮(NF3)、氟化硒(SeF6)、全氟乙烷(perfluoroethane；C2F6)、全氟丙烷(perfluoropropane；C3F8)、或另一种可应用的气体、或前述的组合。可稀释氟自由基(例如，介于1～5％之间)以助于蚀刻选择性。在一些实施例中，含氟气体的流速在约10sccm至约500sccm的范围内。干蚀刻有效地到达位于气隙底部的氮化硅，这改善了气隙的深宽比。另外，湿蚀刻可与稀释的氢氟酸(DHF)；氢氧化钾(KOH)溶液；氨；含有氢氟酸(HF)、硝酸(HNO3)、及/或醋酸(CH3COOH)、或其它合适的湿蚀刻剂的溶液一起使用。
在操作28处，方法10(图1)通过形成覆盖气隙150a～150d的覆盖层或密封层152(图3B)来密封气隙150a～150d。在形成密封层152时，气隙150a～150d的体积被最终化。如图3B所示，密封层152在栅极堆叠116a～116c的顶表面上方的一高度处接合(interfaces)气隙150a～150d。界面可略低于层间介电(ILD)层110的顶表面，因为在其形成期间，密封层152稍微穿透到气隙150a～150d中(例如，不大于5纳米，像是1～5纳米)。在一些实施例中，气隙150a～150d具有非常小的宽度(例如，1～5纳米)以降低密封层152深入穿透至气隙150a～150d的风险。
可利用物理气相沉积(PVD)、化学气相沉积(CVD)、原子层沉积(ALD)、及/或其他合适的方法来沉积密封层152。在一实施例中，利用物理气相沉积(PVD)是因为它可以快速地沉积阻止其他材料进入气隙150a～150d的初始层。其结果，气隙150a～150d可变得更高。在另一实施例中，利用具有含碳前驱物的原子层沉积(ALD)。在一实施例中，密封层152的厚度介于2～7纳米之间。密封层152可使用任何合适的材料，只要其能够完全封闭气隙150a～150d以避免其他材料进入气隙150a～150d。在一实施例中，密封层152使用硅、氧化硅(SiO2)、氮化硅(SiN)、碳氮化硅(SiCN)、碳化硅(SiC)、或前述的组合。
在操作30处，方法10(图1)形成两个额外层-包括一金属氮化物层154和一蚀刻停止层(etch stop layer)156-于密封层152之上(图3C)。密封层152和蚀刻停止层156都可做为中间接触蚀刻停止层(middle contact etch stop layers；MCESLs)，且在这种情况下，金属氮化物层154夹在两个蚀刻停止层之间以创造一交错层结构。在一实施例中，金属氮化物层154包括氮化钛(TiN)，且蚀刻停止层156包括氮化硅(SiN)或另一种合适的材料。与金属相比，金属氮化物层154具有相对高的电阻率，且可用以在半导体装置100中形成电阻器。蚀刻停止层156促进此处未详细描述的方法10的进一步处理。例如，可形成另一个接触插塞于接触插塞136a和136b之上并与其电性连接。可形成金属线以内连接(interconnect)较高的插塞和其他的电路部件。
如上所述，图3A～图3C(对应于操作26、28、和30)显示第一气隙形成方法。相较之下，图5A～图5E显示出第二气隙形成方法，其对应于图4中所示的方法40。方法10和方法40在许多方面是相同的，包括操作12～24，为了简明起见，不再重复描述相同或相似的方面。以下的描述着重于方法40与方法10不同的方面。
方法40开始于已经过上述操作24的半导体装置100。然后，在操作42处，方法40(图4)移除接触插塞136a和136b的较高部分，以分别在接触孔130a和130b中创造出两个凹部(recesses)(图5A)。具体地，“回蚀刻”如图2F所示金属填充层141的剩余部分以创造凹部。也可以移除如图2F所示障壁层139较高的一小部分。通过选择性蚀刻制程形成凹部，其可利用干蚀刻、湿蚀刻、反应离子蚀刻(RIE)、及/或其他合适的制程。调整(tailored)蚀刻条件以保持接触插塞136a和136b的目标厚度，以便促进后续的操作44。在一实施例中，凹部位于栅极堆叠116a～116c的顶表面上方至少3纳米。
在操作44处，方法40(图4)沉积硬罩幕层160于半导体装置100的顶表面之上(图5B)。硬罩幕层160可包括任何合适的材料。在一实施例中，硬罩幕层160包括硅、碳氮化硅(SiCN)、氧化铪(HfO2)、氧化铝(Al2O3)、氧化锆(ZrO2)、或前述的组合、或另一种隔离材料。可通过物理气相沉积(PVD)、化学气相沉积(CVD)、原子层沉积(ALD)、电镀、或其他合适的方法来形成硬罩幕层160。
在操作46处，方法40(图4)使用化学机械平坦化(CMP)制程平坦化硬罩幕层160(图5C)，其移除硬罩幕层160的顶部。为了促进后续气隙的形成，在一些实施例中，化学机械平坦化(CMP)制程足够长以确保氮化硅部件142a～142d的暴露。例如，化学机械平坦化(CMP)制程也可移除层间介电(ILD)层110的顶部以暴露出氮化硅部件142a～142d的顶表面。在一实施例中，在化学机械平坦化(CMP)之后保留了2～5纳米的硬罩幕层160。操作44和46共同形成硬罩幕层160，其填充了接触孔130a和130b中由操作42创造的两个凹部。硬罩幕层160使氮化硅部件142a～142d的顶表面暴露。
在操作48处，方法40(图4)移除氮化硅部件142a～142d以分别形成气隙150a～150d(图5D)。关于方法10的上述气隙150a～150d的特点同样适用于此。然而，在方法40中，如果在操作46的化学机械平坦化(CMP)制程中移除层间介电(ILD)层110的顶部，则气隙150a～150d的高度可能相对较小。此外，相较于障壁层139、层间介电(ILD)层110、和硬罩幕层160，操作48处的选择性蚀刻制程对氮化硅部件142a～142d具有高蚀刻选择性，使得氮化硅部件142a～142d可被完全移除而大致上(substantially)不影响其他周围的层。这样的蚀刻选择性现在额外取决于硬罩幕层160的材料选择。
在操作50处，方法40(图4)通过沉积覆盖气隙150a～150d的第二层间介电(ILD)层170来密封气隙150a～150d(图5E)。层间介电(ILD)层170也是密封层或覆盖层。在形成层间介电(ILD)层170时，最终化气隙150a～150d的体积。如图5E所示，层间介电(ILD)层170在栅极堆叠116a～116c的顶表面上方的一高度处接合(interfaces)气隙150a～150d。界面可略低于层间介电(ILD)层110的顶表面，因为在其形成期间，层间介电(ILD)层170稍微穿透到气隙150a～150d中(例如，1～5纳米)。但是界面仍然高于硬罩幕层160的底表面(其对应于接触插塞136a和136b的顶表面，如图5E所示)。在一些实施例中，气隙150a～150d具有非常小的宽度(例如，1～5纳米或甚至更小，例如0.5纳米)以降低层间介电(ILD)层170深入穿透至气隙150a～150d的风险。
可利用物理气相沉积(PVD)、化学气相沉积(CVD)、原子层沉积(ALD)、及/或其他合适的方法来沉积层间介电(ILD)层170。在一实施例中，利用物理气相沉积(PVD)是因为它可以快速地沉积阻止其他材料进入气隙150a～150d的初始层。其结果，气隙150a～150d可变得更高。在另一实施例中，利用具有含碳前驱物的原子层沉积(ALD)。层间介电(ILD)层170可使用任何合适的材料，只要其能够完全封闭气隙150a～150d以避免其他材料进入气隙150a～150d。在一实施例中，层间介电(ILD)层170包括氧化硅(SiO2)。
需注意的是，尽管方法10和方法40在半导体装置100上造成了不同的结构，但是那些结构在许多方面可以是相似或相同的。例如，在栅极堆叠116a～116c下方一高度处的半导体装置100的一部分平面图将是相同的。图6显示由图3C中线A-A’和图5E中线B-B’标记的高度处的半导体装置100的部分平面图。图6显示图3C和图5E的相同局部视图。值得注意的是，设置于接触插塞136a和栅极堆叠116b之间的气隙150b靠近接触插塞136a并与接触插塞136a对齐。实际上，气隙150b将接触插塞136a的侧壁直接暴露于气隙150b内的空气。当接触插塞136a传导电流时，这种空气暴露有助于散热，因为空气具有比接触插塞136a旁边的其他材料更高的导热性。需注意的是，气隙150b内的空气可以是大气空气或填充到气隙150b中的其他合适的气体(例如，惰性气体)以促进热传导。另一方面，气隙150b相对地远离栅极堆叠116b，因为气隙150b通过层间介电(ILD)层110与栅极堆叠116b分离(且当间隔物112不被视为栅极堆叠116b的一部分时通过间隔物112而分离)。
在方法10和方法40中，可形成具有合适的尺寸(例如，厚度、高度、深度、或宽度)的每一个部件。例如，在一实施例中，如图6所示，接触插塞136a的宽度介于20～50纳米之间；在接触插塞136a任一侧上的障壁层139的宽度介于1～2纳米之间；每一个气隙150a和150b的宽度介于1～5纳米之间。
尽管不旨在限制，但是本发明的一个或多个实施例为半导体装置及其形成提供了许多益处。具体地，形成气隙的时间改变导致各种元件的结构和位置产生变化。例如，此处公开的气隙形成技术实现了延伸于邻近栅极堆叠的顶表面上方的气隙。因此，可有效地降低栅极堆叠和接触插塞之间的寄生电容。此外，气隙与接触插塞对齐而不是与栅极堆叠对齐。气隙将接触插塞的侧壁直接暴露在空气中，这在接触插塞传导电流时有助于散热。所公开方法的实施例可轻易地整合至现有的制造制程和技术中，像是产线中段(middle end ofline；MEoL)和产线后段(back end of line；BEoL)制程。
在一示例方面，本发明实施例提供一种半导体装置的制造方法，包括：形成第一和第二氮化硅部件于一接触孔的侧壁表面上，其中所述接触孔设置于一介电层中和一源极/漏极(S/D)部件上方。所述方法还包括形成一接触插塞于接触孔中，所述接触插塞与源极/漏极(S/D)部件电耦合；移除接触插塞的一顶部以在接触孔中创造一凹部；形成一硬罩幕层于凹部中；以及通过选择性蚀刻移除第一和第二氮化硅部件以分别形成第一和第二气隙。在一实施例中，第一气隙形成于接触插塞和介电层之间以降低接触插塞和第一邻近栅极堆叠之间的一第一电容。第二气隙形成于接触插塞和介电层之间以降低接触插塞和第二邻近栅极堆叠之间的一第二电容。在一实施例中，第一和第二气隙的形成使得接触插塞直接暴露于第一和第二气隙。在一实施例中，介电层为一第一层间介电(ILD)层，且所述方法还包括形成一第二层间介电层于接触插塞之上，其中所述第二层间介电层覆盖第一和第二气隙。在一实施例中，第二层间介电层在第一和第二邻近栅极堆叠的顶表面上方的一高度处接合(interfaces)第一和第二气隙。在一实施例中，第一和第二气隙至少由第一层间介电层分别与第一和第二邻近栅极堆叠分离，其中所述第一层间介电层包括一低介电常数(low-k)材料。在一实施例中，形成所述硬罩幕层于凹部中包括：沉积硬罩幕层，以及利用一化学机械平坦化(CMP)制程移除所述硬罩幕层的一顶部。所述化学机械平坦化制程(CMP)暴露出第一和第二氮化硅部件的顶表面以促进第一和第二氮化硅部件的移除。在一实施例中，在化学机械平坦化(CMP)制程之后，凹部中的硬罩幕层的剩余厚度为2～5纳米，且凹部位于接触插塞的一邻近栅极堆叠上方至少3纳米。在一实施例中，接触插塞包括一障壁层和一金属填充层。此处，形成接触插塞包括：形成障壁层于第一和第二氮化硅部件之间；沉积金属填充层，覆盖障壁层和介电层；以及利用一化学机械平坦化(CMP)制程移除金属填充层的一顶部。在一实施例中，第一和第二氮化硅部件具有蚀刻选择性，使得第一和第二氮化硅部件比起与第一和第二氮化硅部件接触的其他材料可以快至少10倍的速率被移除。
在另一方面，本发明实施例提供一种半导体装置的制造方法，包括提供一半导体装置结构，所述半导体装置结构包括：一基板；第一和第二栅极堆叠，位于基板上；第一和第二氮化硅部件，位于第一和第二栅极堆叠之间；以及一接触插塞，位于第一和第二氮化硅部件之间并与第一和第二氮化硅部件接触。所述方法还包括蚀刻第一和第二氮化硅部件以分别形成第一和第二气隙，其中第一和第二气隙将接触插塞的侧壁暴露于第一和第二气隙内的空气。所述方法还包括形成一密封层于接触插塞之上以覆盖第一和第二气隙。在一实施例中，密封层在第一和第二栅极堆叠的顶表面上方的一高度处接合(interfaces)第一和第二气隙。在一实施例中，利用一物理气相沉积(PVD)制程形成密封层，使得密封层在接触插塞的一顶表面下方不超过5纳米的一高度处接合(interfaces)第一和第二气隙。在一实施例中，第一和第二气隙的宽度都介于1～5纳米之间。第一和第二气隙通过至少一层间介电(ILD)层分别与第一和第二栅极堆叠分离，其中所述层间介电层(ILD)包括一低介电常数(low-k)材料。
又在另一方面，本发明实施例提供一种半导体装置，包括：一基板；一源极/漏极(S/D)部件，设置于基板上；一金属插塞，设置于源极/漏极(S/D)部件之上；一栅极堆叠，设置为邻近于金属插塞；一气隙，设置于金属插塞和栅极堆叠之间；以及一覆盖层，覆盖所述气隙。所述气隙至少部分地将金属插塞的一侧壁暴露于气隙内的空气中。在一实施例中，覆盖层和气隙之间的一界面高于栅极堆叠的一顶表面。在一实施例中，金属插塞包括一障壁层，所述障壁层包括一锥形(tapered)厚度轮廓。在一实施例中，金属插塞还包括一金属填充层，设置于障壁层上方并邻近所述障壁层，其中所述障壁层包括氮化钛(TiN)，且其中所述金属填充层包括钨(W)或钴(Co)。在一实施例中，所述半导体装置还包括与气隙直接接触的一层间介电(ILD)层，其中所述层间介电层包括氧化硅(SiO2)、碳氮化硅(SiCN)、碳氧化硅(SiCO)、或前述的组合。在一实施例中，所述半导体装置还包括一硬罩幕层，设置于金属插塞和覆盖层之间，且在覆盖层下方，其中所述硬罩幕层的一底表面高于该栅极堆叠的一顶表面。
前述内文概述了许多实施例的部件，以使本技术领域中技术人员可以从各个方面更佳地了解本发明实施例。本技术领域中技术人员应可理解，且可轻易地以本发明实施例为基础来设计或修饰其他制程及结构，并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中技术人员也应了解这些相等的结构并未背离本发明的精神与范围。在不背离本发明的精神与范围的前提下，可对本发明实施例进行各种改变、置换或修改。

Claims (1)

1.一种半导体装置的制造方法，包括：
形成一第一氮化硅部件和一第二氮化硅部件于一接触孔的侧壁表面上，该接触孔设置于一介电层中和一源极/漏极部件上方；
形成一接触插塞于该接触孔中，该接触插塞与该源极/漏极部件电耦合；
移除该接触插塞的一顶部以在该接触孔中创造一凹部；
形成一硬罩幕层于该凹部中；以及
通过选择性蚀刻移除该第一氮化硅部件和该第二氮化硅部件以分别形成一第一气隙和一第二气隙。
CN201910043132.5A 2018-06-15 2019-01-17 半导体装置的制造方法 Pending CN110610903A (zh)

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