CN110391224A - 具有双向开关和放电电路的半导体器件 - Google Patents

具有双向开关和放电电路的半导体器件 Download PDF

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CN110391224A
CN110391224A CN201910328003.0A CN201910328003A CN110391224A CN 110391224 A CN110391224 A CN 110391224A CN 201910328003 A CN201910328003 A CN 201910328003A CN 110391224 A CN110391224 A CN 110391224A
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diode
main
way switch
grid
electrode
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CN110391224B (zh
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M.伊马姆
H.金
K.K.梁
B.潘地亚
G.普雷赫特尔
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Infineon Technologies Austria AG
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    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6874—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor in a symmetrical configuration
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Abstract

具有双向开关和放电电路的半导体器件。一种半导体器件包括主双向开关，其形成在半导体衬底上并具有第一和第二栅极，电连接到第一电压端的第一源极，电连接到第二电压端的第二源极，以及公共漏极。该半导体器件还包括放电电路，其具有与主双向开关单片集成的并以公共源极配置连接到半导体衬底的辅助双向开关或多个单独的晶体管。多个单独的晶体管或辅助双向开关包括连接到主双向开关的第一源极的第一漏极，连接到主双向开关的第二源极的第二漏极，第一和第二栅极，其中每个与栅极驱动电路解耦合,使得至少无源地并且基于主双向开关的状态控制第一和第二栅极。

Description

具有双向开关和放电电路的半导体器件
背景技术
在单片器件中具有公共漏极的两个单独的栅极是用于实现双向开关的流行配置。单片器件通常在公共衬底中实现，其中两个开关中的每一个都具有其自己的栅极驱动器。公共漏极配置在单片器件的任一端处具有源极，意味着到衬底的源极连接不是用于双向开关的选项。如果衬底保持浮置并且两个源极中的一个被偏置在高电压处，则该源极连同相邻栅极充当延伸的漏极并因此跟随高电位。在导通状态期间，为了稳定的双向器件操作，衬底必须尽可能地保持接近地电位。常规地，集成两个背对背二极管，其中它们的阳极连接到衬底并且每个阴极连接到源极的任一端。然而，这种背对背二极管实现在双向开关的导通状态期间不将衬底电压保持到期望的（接近0V）电压，并且因此使器件性能降级。代之以，衬底经历大的负电位，因为在双向开关的断开状态期间存储在衬底中的负电荷被限制在背对背二极管的中点中的衬底。该限制是由在双向开关的断开状态期间最初被正向偏置但是当双向器件从断开状态切换到导通状态时改变为阻塞模式的背对背二极管中的任一二极管引起的。由此，存在对于用于在双向开关的断开到导通切换期间为衬底提供放电路径的更有效的单片解决方案的需要。
发明内容
根据半导体器件的一个实施例，半导体器件包括主双向开关和放电电路。主双向开关形成在半导体衬底上并包括第一和第二栅极，电连接到第一电压端的第一源极，电连接到第二电压端的第二源极，以及公共漏极。放电电路包括与主双向开关单片集成的并以公共源极配置连接到半导体衬底的辅助双向开关或多个单独的晶体管。多个单独的晶体管或辅助双向开关包括连接到主双向开关的第一源极的第一电极，连接到主双向开关的第二源极的第二电极，以及第一和第二栅极，其中每个栅极与栅极驱动电路解耦合，使得至少无源地（passively）并且基于主双向开关的状态控制第一和第二栅极。
本领域的技术人员在阅读下面的详细描述时并且在查看附图时将认识到附加特征和优势。
附图说明
附图的元素不一定相对于彼此按比例。相同的附图标记表示相应的类似部分。可以组合各种示出的实施例的特征，除非它们彼此排斥。在附图中描绘并且在以下描述中详述实施例。
图1和2示出半导体器件的实施例的相应电路示意图，该半导体器件包括主双向开关和放电电路，用于在双向开关的断开到导通切换期间提供衬底放电路径。
图3示出用于图1和2中所示的放电电路栅极配置的主双向开关的半导体衬底的动态行为。
图4示出半导体器件的一个实施例的电路示意图，该半导体器件包括主双向开关和放电电路，用于在双向开关的断开到导通切换期间提供衬底放电路径。
图5示出用于图4中所示的放电电路栅极配置的主双向开关的半导体衬底的动态行为。
图6和7示出半导体器件的实施例的相应电路示意图，该半导体器件包括主双向开关和放电电路，用于在双向开关的断开到导通切换期间提供衬底放电路径。
图8示出用于图6和7中所示的放电电路栅极配置的主双向开关的半导体衬底的动态行为。
图9，10A-10B，11A-11B，12，13A-13B，14A-14B，15，16，17A-17B，18，19和20示出在以III族氮化物技术实现的化合物半导体器件的不同实施例的相应横截面图，并且化合物半导体器件包括主双向开关和放电电路，用于在双向开关的断开到导通切换期间提供衬底放电路径。
图21示出以III族氮化物技术实现的化合物半导体器件的另一实施例的横截面图，并且该化合物半导体器件包括主双向开关和放电电路，用于在双向开关的断开到导通切换期间提供衬底放电路径。
图22示出图21中所示的化合物半导体器件的俯视图。
图23示出以III族氮化物技术实现的化合物半导体器件的另一实施例的横截面图，并且该化合物半导体器件包括主双向开关和放电电路，用于在双向开关的断开到导通切换期间提供衬底放电路径。
图24示出图23中所示的化合物半导体器件的俯视图。
具体实施方式
这里描述的实施例提供以公共电极（例如源极）配置连接的或者实现为与主双向开关单片集成的公共电极（例如源极）双向开关的控制晶体管。单片集成的控制晶体管被配置为在双向开关的导通状态期间将双向开关的半导体衬底保持在期望电压处，作为为半导体衬底提供放电路径的放电电路运转。单片集成的控制晶体管的栅极可以连接在一起并浮置，彼此断开并且每个浮置，连接在一起并通过相应的二极管连接到双向开关的源极，或者彼此断开连接并通过相应的二极管连接到双向开关的源极。在每种情况下，不需要附加的栅极驱动器，辅助供应或控制部件来确保单片集成的控制晶体管的正确操作，因此提供了一种用于在双向开关的导通状态期间将双向开关的半导体衬底保持在所需电压处的基本上无源的解决方案。
尽管这里描述的放电电路可以与主双向开关单片地集成，但是放电电路替代地可以在主双向开关的外部（即不与其集成）。在该情况下，放电电路和主双向开关之间的这里描述的电连接可以通过包括放电电路和主双向开关的分开的管芯和/或封装的相应端来形成。管芯到管芯，管芯到封装和封装到封装的端连接在半导体器件领域中是众所周知的，并且可以例如通过引线接合，金属夹（metal clip），金属带（metal ribbon），焊料凸块，管芯堆叠，封装堆叠等来实现，并且因此在此不给出对这种端连接的进一步说明。
图1示出了半导体器件的一个实施例的电路示意图，该半导体器件包括主双向开关100和放电电路102，用于在双向开关100的断开到导通切换期间提供衬底放电路径。主双向开关100形成在半导体衬底上，该半导体衬底在图1中由标记为“SUB”的节点示意性地表示。主双向开关100具有第一和第二栅极G1，G2，第一和第二源极S1，S2，以及共同的漏极。主双向开关100的第一源极S1电连接到第一电压端Vss1。主双向开关100的第二源极S2电连接到第二电压端Vss2。
主双向开关100具有四个主要工作状态：断开/断开，其中主双向开关100的两个栅极G1，G2两者都断开；导通/导通，其中主双向开关100的栅极G1，G2两者都导通；导通/断开，其中主双向开关100的第一栅极G1导通并且主双向开关100的第二栅极G2断开；和断开/导通，其中主双向开关100的第一栅极G1断开并且主双向开关100的第二栅极G2导通。双向开关的典型操作包括从导通/断开转变到导通/导通，以及从断开/导通转变到导通/导通。电流流动方向取决于跨第一和第二电压端Vss1，Vss2的极性。通过改变极性可以反转电流流动方向。
主双向开关100示意性地由图1中的主晶体管Q1和Q2来表示。主晶体管Q1和Q2共享公共漏极，并且在横向器件的情况下在主双向开关100的相对端部处具有源极S1，S2。根据图1中所示的实施例，第一和第二衬底二极管Sb1和Sb2与主双向开关100单片地集成。第一衬底二极管Sb1的阳极和第二衬底二极管Sb2的阳极连接到半导体衬底。第一衬底二极管Sb1的阴极连接到主双向开关100的第一源极S1，并且第二衬底二极管Sb2的阴极连接到主双向开关100的第二源极S2。
在主双向开关100的断开到导通切换期间为半导体衬底提供了放电路径的放电电路102包括与主双向开关100单片集成的辅助双向开关或多个单独的晶体管。例如，单独的晶体管或辅助双向开关的对由图1中的控制晶体管Q3和Q4示意性地表示。控制晶体管Q3和Q4以公共电极（例如源极）配置连接到半导体衬底。更具体地，由图1中的控制晶体管Q3和Q4表示的单独晶体管或辅助双向开关包括连接到主双向开关100的第一源极S1的第一电极（例如漏极）D3，连接到主双向开关100的第二源极S2的第二电极（例如漏极）D4，连接到半导体衬底的公共电极（例如源极）S3/S4，以及每个从栅极驱动电路解耦合的第一和第二栅极G3，G4。栅极G3和G4系连（tie）在一起并浮置。由于控制晶体管Q3和Q4的第一和第二栅极G3，G4中的每个与栅极驱动电路解耦合，所以放电电路102的第一和第二栅极G3，G4至少无源地并且基于主双向开关100的状态被控制。
在断开状态（导通/断开或断开/导通）中，主双向开关100的栅极G1和G2分别导通和断开，并且主双向开关100处于阻塞状态。在该情况下，在第一电压端Vss1处施加相对高的电压，控制晶体管Q3和Q4不导通，并且大部分源极电压跨主晶体管Q2和控制晶体管Q3出现。如果代之以在第二电压端Vss2处施加源极电压，则控制晶体管Q3和Q4仍然不导通并且大部分源极电压跨主晶体管Q1和控制晶体管Q4出现。
当主双向开关100从断开状态（导通/断开或断开/导通）转变到导通状态（导通/导通）时，电流通道形成在主双向开关100中并且跨开关100实际上不发生电压降。在主晶体管Q1和Q2以及控制晶体管Q3或Q4中的一些存储的电荷通过主晶体管Q1和Q2排放。另外，其他存储的电荷通过控制晶体管Q3和Q4排放，因为两者在断开到导通切换期间瞬时或几乎瞬时导通。例如，当第一电压端Vss1的源极电压从高正电压改变到低正电压时，换句话说，当Q2从断开切换到导通并且Q1保持导通时，控制晶体管Q3和Q4的栅极G3，G4相对于使控制晶体管Q3和Q4打开的它们的公共源极端S3/S4变得更加正向（more positive），由此为半导体衬底中的存储的电荷提供放电路径并将衬底解偏置到0V或接近0V。
如前所述，控制晶体管Q3，Q4的栅极G3，G4可以连接在一起并且浮置或彼此断开并且每个都浮置。控制晶体管Q3，Q4的栅极G3，G4的状态基于主双向开关100的状态。图1示出了其中控制晶体管Q3，Q4的栅极G3，G4连接在一起并浮置的实施例。
图2示出了半导体器件的另一个实施例的电路示意图，其中形成放电电路102的单独晶体管或辅助双向开关的控制晶体管Q3，Q4的栅极G3，G4彼此断开并且每个浮置。
图3示出了用于图1和2中所示的放电电路栅极配置的主双向开关100 的半导体衬底电位（V_SUB）的动态行为。没有放电电路102，衬底电位将摆动到高负电压，从断开/导通状态（或导通/断开-G1或G2导通并且另一个栅极断开）去往导通/导通状态（G1和G2两者均导通）。图1和2中所示的放电电路102具有到半导体衬底的公共电极（例如源极）连接，其在主双向开关的操作期间与背对背二极管一起可靠地控制衬底上的电压。在栅极G1导通并且栅极G2断开的情况下，在衬底二极管Sb1和控制晶体管Q3之间共享施加在第一电压端Vss1处的高电压（例如200V），具有跨衬底二极管Sb2的非常小的降低（drop），这使半导体衬底保持在较低电压处。当栅极G2切换到导通同时保持栅极G1导通时，图1和图2中的控制晶体管Q3和Q4中的每个变为导通，因为公共电极（例如源极）的电压与其栅极的电压相比是足够高的负，以使控制晶体管Q3和Q4导通，从而将半导体衬底下拉到第一和/或第二源极S1，S2的较低源极电位，因为存储在衬底中的负电荷通过控制晶体管Q3，Q4排放。
在控制晶体管Q3和Q4从断开切换到导通的纳秒间隔期间，半导体衬底电位试图变为负，但是通过控制晶体管Q3和/或Q4的放电路径快速恢复到期望电压或接近0V。虽然半导体衬底在该短间隔期间（例如约100 ns或更少）经历负电压，但是如果省略放电电路102，则负电压偏移（excursion）显著短于衬底否则将经历的。在没有放电电路的情况下，衬底将被负偏置在约一半完全源极电压，并且衬底二极管Sb1和Sb2将保持在阻塞状态，从而防止衬底完全放电，因为不存在放电路径。
在放电电路102与主双向开关100单片地集成的情况下，控制晶体管Q3和Q4两者在断开状态（断开/断开，断开/导通和导通/断开）期间像二极管那样动作。当双向开关100从导通/断开状态或断开/导通状态转变到导通/导通时，用于公共漏极主双向开关100的半导体衬底的电位试图变为负，但是放电电路102的控制晶体管Q3和Q4几乎立即响应并通过控制晶体管Q3和/或Q4将存储在衬底中的电荷排放。
在主双向开关100和放电电路102以GaN技术单片地集成的一些实施例中，控制晶体管Q3和Q4切换到导通和通过控制晶体管Q3和Q4将存储在衬底中的电荷排放大概花费约90 ns（约11MHz）或更少。一个电压端（例如Vss1）相对于另一端（例如Vss2）可以是更高的电位，反之亦然。在每种情况下，放电电路102被配置为响应于主双向开关100从导通/断开状态或断开/导通状态转变到导通/导通状态，将存储在半导体衬底处的电荷自动排放到源极S1和S2。
在图1和2中所示的实施例中，形成放电电路102的单独晶体管或辅助双向开关的控制晶体管Q3，Q4的栅极G3，G4基于衬底和控制晶体管栅极的浮置电位是浮置和自定义的。
图4示出了包括主双向开关100和放电电路102的半导体器件的又一个实施例的电路示意图。图4中所示的实施例类似于图1和2中所示的实施例。然而，不同的是，第一辅助二极管GD1和第二辅助二极管GD2也与主双向开关100单片地集成。第一辅助二极管GD1的阳极连接到放电电路102的控制晶体管Q3的栅极G3。第一辅助二极管GD1的阴极连接到主双向开关100的第一源极S1。第二辅助二极管GD2的阳极类似地连接到放电电路102的控制晶体管Q4的栅极G4。第二辅助二极管GD2的阴极连接到主双向开关100的第二源极S2。
此外，根据该实施例，放电电路102的控制晶体管Q3的栅极G3插入在放电电路102的第一漏极D3和公共源极S3/S4之间。放电电路102的控制晶体管Q4的栅极G4插入在放电电路102的公共源极S3/S4和第二漏极D4之间。利用图4中所示的配置，控制晶体管Q3，Q4的栅极G3，G4通过相应的辅助二极管GD1和GD2分别连接到第一和第二电压端Vss1和Vss2。辅助二极管GD1和GD2可以是以二极管模式（栅极-源极短路在一起）连接的简单二极管或FET，如本文后面更详细地解释的那样。类似于图1和2中所示的实施例，图4中所示的实施例不需要附加的栅极驱动器，辅助供应或控制部件。
图5示出了用于图4中所示的放电电路栅极配置的主双向开关100的半导体衬底电位（V_SUB）的动态行为。当栅极G1导通时，栅极G2断开并将相对高的电压施加在第一电压端Vss1处，高压在衬底二极管Sb1，控制晶体管Q3和辅助二极管GD1之间共享。跨控制晶体管Q4，衬底二极管Sb2和辅助二极管GD2发生非常低的电压。当栅极G2导通时，具有辅助二极管GD1和GD2的控制晶体管Q3和Q4确保半导体衬底和第二源极S2之间的瞬时或几乎瞬时短路或接近短路，因此导致放电并将衬底保持稳定在接近0V的较低电位处。在断开到导通切换期间，图1，图2和图4中所示的配置中的每个具有如图3和5中所示的在半导体衬底处的短暂负电压尖峰的特性标记（signature），其在主双向开关100的半导体衬底电位稳定到小值之前片刻发生。如上所述，如果省略放电电路102，则半导体衬底所经历的负电压偏移显著短于衬底否则将经历的。
图6示出了包括主双向开关100和放电电路102的半导体器件的又一实施例的电路示意图。图6中所示的实施例类似于图4中所示的实施例。然而，不同的是，辅助二极管GD1，GD2的阳极连接是相反的。也就是说，第一辅助二极管GD1的阳极连接到放电电路102的控制晶体管Q4的栅极G4而不是控制晶体管Q3的栅极G3。第二辅助二极管GD2的阳极连接到放电电路102的控制晶体管Q3的栅极G3，而不是控制晶体管Q4的栅极G4。据信，在主双向开关100的半导体衬底稳定到小值之前，图6中所示的辅助二极管配置消除或显著减小了半导体衬底处的短暂负电压尖峰的特性标记。
图7示出了包括主双向开关100和放电电路102的半导体器件的另一实施例的电路示意图。图7中所示的实施例类似于图6中所示的实施例。然而，不同的是，省略了衬底二极管Sb1和Sb2。根据该实施例，包括与主双向开关100单片集成的放电电路102的半导体器件在主双向开关100的第一源极S1和半导体衬底之间以及在主双向开关100的第二源极S2和半导体衬底之间没有二极管连接。
图8示出了用于图6和7中所示的放电电路栅极配置的主双向开关100的半导体衬底电位（V_SUB）的动态行为。具有放电电路控制晶体管Q3，Q4的半导体衬底的动态特性行为可以被抑制而不影响半导体衬底的稳定性。当电压端Vss1处于高电压时，辅助二极管GD1与控制晶体管Q4串联，并且辅助二极管GD2与控制晶体管Q3串联。控制晶体管Q3和/或Q4在断开到导通切换期间短时间导通。利用该配置，有效地消除了在主双向开关100的导通的开始时在半导体衬底处的负电压尖峰。
在图1，2，4，6和7中所示的每个电路配置中，放电电路102与半导体器件的主双向开关100单片地集成。放电电路102以共源极配置连接到主双向开关100的半导体衬底。单片集成的控制晶体管Q3，Q4的栅极G3，G4可以连接在一起并浮置，彼此断开并每个浮置，连接在一起并通过各自的二极管连接到主双向开关100的源极，或者彼此断开并通过各自的二极管连接到主双向开关100的源极。接下来描述主双向开关100和单片集成的放电电路102的各种器件实施例。
图9示出了主双向开关100的实施例的横截面图，以例如GaN高电子迁移率晶体管（HEMT）之类的III族氮化物技术将该主双向开关100实现为化合物半导体器件的部分。主双向开关100形成在诸如Si衬底之类的半导体衬底200上或Si衬底上的一个或多个外延生长或注入的Si层上。在半导体衬底200之上形成的III族氮化物缓冲区202（例如GaN），在III族氮化物缓冲区202之上形成III族氮化物沟道区203（例如GaN），以及在III族氮化物沟道区203之上形成III族氮化物势垒区204（例如AlGaN）。HEMT可以是常导通（normally-on）器件，其中沟道在没有栅极电压的情况下沿着栅极不中断，或者是常断开（normally-off）器件，其中沟道在没有栅极电压的情况下沿栅极中断。例如，在常断开器件的情况下，HEMT可以包括在栅极G1，G2和下面的III族氮化物势垒区204之间的p掺杂的III族氮化物层205。在常导通器件的情况下，可以省略栅极G1，G2和下面的III族氮化物势垒区204之间的p掺杂的III族氮化物层205。
由于自发和压电极化在基于GaN的异质结构体（heterostructure body）中的极化电荷的出现和应变效应（strain effect）产生了由非常高的载流子密度和载流子迁移率表征的异质结构体中的二维电荷载流子气（charge carrier gas）。诸如2DEG（二维电子气）或2DHG（二维空穴气（hole gas））之类的该二维电荷载流子气在例如诸如 AlGaN，InAlGaN，InAlN等之类的GaN合金势垒的III族氮化物势垒204和III族氮化物沟道区203（例如GaN沟道层）之间的界面附近形成主双向开关100的导电沟道。可以在III族氮化物沟道区203和GaN合金势垒204之间提供例如1-2nm的薄的AlN层，以最小化合金散射并增强2DEG迁移率。III族氮化物缓冲，沟道和势垒区202，203，204可以在诸如Si，SiC或蓝宝石衬底之类的半导体衬底200上制造，在其上可以形成诸如AlN层之类的成核（nucleation）（种子）层用于提供与III族氮化物缓冲区202和/或III族氮化物沟道区203的热和晶格匹配。化合物半导体器件还可以具有AlInN/AlN/GaN势垒/间隔物/沟道层/缓冲层结构。通常，可以使用诸如GaN之类的任何合适的III族氮化物技术来实现化合物半导体器件，诸如GaN之类的任何合适的III族氮化物技术允许由于压电效应而形成相反极性反转区。
在图1，2，4，6和7中标记为Q1和Q2的晶体管代表主双向开关100。晶体管Q1和Q2可以被实现为在III族氮化物异质结构体202/203/204中形成的第一和第二栅极G1，G2，第一和第二源极S1，S2，以及公共漏极。公共漏极位于栅极G1，G2之间。当高电压施加到源极S1时，主双向开关100的漏极由栅极G1和源极S1形成。相反，当高电压施加到源极S2时，主双向开关100的漏极由栅极G2和源极S2形成。通过将源极S1与栅极G1隔开与源极S2同栅极G2隔开的相同的距离，主双向开关100是对称的。图9还示意性地示出了图1，2，4和6中所示的衬底二极管Sb1，Sb2。可以提供诸如背面金属化层之类的衬底电极206以与衬底200的背面形成欧姆连接。
图10A和10B示出了图1，2，4和6中所示的衬底二极管Sb1，Sb2的实施例的相应横截面图。衬底二极管Sb1，Sb2与主双向开关100单片地集成，这是在图10A和10B中看不见的。每个衬底二极管Sb1，Sb2可以是GaN二极管，其包括p掺杂区（例如pGaN），其具有诸如阳极（A）之类的电极208，二维电子气（2DEG）和诸如阴极（K）之类的另一电极210。2DEG可以通过器件的二极管区中的III族氮化物沟道区203和III族氮化物势垒区204之间的自发和压电极化来形成。可以以诸如镁之类的适当的掺杂剂种类掺杂或生长III族氮化物沟道区203来形成III族氮化物势垒区204上的p掺杂区。由于衬底二极管Sb1，Sb2的阳极如图1，2，4和6所示（电）连接到半导体衬底200，所以具有它们的电极的p掺杂区可以形成为电连接在一起的分开的区域或形成为具有其单个电极的单个p掺杂区。由于两个阳极电极208电连接在一起，所以可以如图10B中所示的那样使用单个公共电极208'，而不是如图10A中所示的两个分开的电极208。
图11A和11B示出了图1，2，4和6中所示的衬底二极管Sb1，Sb2 的实施例的相应横截面图。根据图11A和11B中所示的实施例，衬底二极管Sb1，Sb2中个每个被实现为GaN晶体管，其具有连接到其功率电极（power electrode）214之一（例如源极）的其栅电极212。连接到栅极的电极214充当阳极，并且另一个电极216被定义为阴极。衬底二极管Sb1，Sb2的阳极（A）和栅极（G）（电）连接到半导体衬底200，并且p掺杂的阳极区可以形成为电连接在一起的分开的区域。衬底二极管Sb1，Sb2的每个阴极（K）分别连接到Vss1或Vss2。由于系连到衬底二极管Sb1和Sb2中的栅极（G）的两个电极214电连接，所以可以如图11B中所示的使用单个公共电极214'，而不是如图11A中所示的两个分开的电极214。
图12示出在图7中所示的电路实施例的横截面图，该电路实施例被以诸如GaN之类的III族氮化物技术实现为化合物半导体器件的一部分。类似于图9，主双向开关100形成在诸如Si衬底之类的半导体衬底200上，或是在Si衬底上的一个或多个外延生长或注入的Si层。III族氮化物缓冲区202在半导体衬底200之上形成，III族氮化物沟道区203（例如GaN）在III族氮化物缓冲区202之上形成，并且III族氮化物势垒区204在III族氮化物沟道区203之上形成。图7中所示的晶体管Q1和Q2可以被实现为第一和第二栅极G1，G2，第一和第二源极S1，S2以及公共漏极。公共漏极位于栅极G1，G2之间。通过将源极S1与栅极G1隔开与源极S2同栅极G2隔开的相同的距离，主双向开关100是对称的。图12还示意性地示出了图7中所示的放电电路102和相应的辅助二极管GD1，GD2。
图13A和13B示出了在图4中所示的辅助二极管GD1，GD2的实施例的相应的横截面图。辅助二极管GD1，GD2与主双向开关100和放电电路102单片地集成，这在图13A和13B中是看不见的。每个辅助二极管GD1，GD2可以是GaN二极管，其包括p掺杂区205（例如pGaN），具有作为阳极（A）的一个电极218和作为阴极（K）的在III族氮化物势垒204（即AlGaN）上的另一个电极220。可以通过在器件的二极管区中的III族氮化物沟道区203和III族氮化物势垒区204之间的自发和压电极化来形成二维电子气（2DEG）。可以通过以诸如镁之类的适当的掺杂剂种类掺杂或生长III族氮化物层来形成III族氮化物势垒区204上的p掺杂的阳极区205。由于每个辅助二极管GD1，GD2的阳极（A）（电）连接到如图4中所示的控制晶体管Q3，Q4的栅极G3/G4之一，所以每个辅助二极管GD1，GD2的p掺杂的阳极区205可以形成为如图13A中所示的具有电连接在一起的两个分开的电极218的两个分开的区域，或者代之形成为如图13B中所示的单个p掺杂区205'和相应的单个电极218'。
图14A和14B示出了如图4中所示的辅助二极管GD1，GD2的实施例的相应的横截面图。根据图14A和14B中所示的实施例，辅助二极管GD1，GD2中的每一个被实现为GaN晶体管，其具有连接到第一电极222（例如源极）的栅极（G）电极220。每个GaN晶体管的另一个电极224被定义为阴极（K）。每个辅助二极管GD1，GD2的源极区可以如图14A中所示的形成为电连接在一起的分开的电极222，或者代之以如图14B中所示的形成为单个电极222'。类似地，每个辅助二极管GD1，GD2的p掺杂区205和栅电极220可以形成为电连接在一起的分开的栅极区或形成为单个栅极区。
图15示出在图4，6，7和12中所示的辅助二极管GD1，GD2的实施例的横截面图。辅助二极管GD1，GD2与主双向开关100和放电电路102单片地集成，这是在图15中看不到的。每个辅助二极管GD1，GD2可以是GaN二极管，其包括p掺杂区205（例如pGaN），具有作为阳极（A）的一个电极226和作为阴极（K）的在III族氮化物势垒区204（例如AlGaN）上的另一电极228。可以通过在器件的二极管区域中的III族氮化物沟道区203和III族氮化物势垒区204之间的自发和压电极化来形成二维电子气（2DEG）。可以通过以诸如镁之类的合适的掺杂剂种类生长III族氮化物层来形成在III族氮化物势垒区204上的p掺杂的阳极区205。
图16示出在图4，6，7和12中所示的辅助二极管GD1，GD2的另一实施例的横截面图。根据该实施例，辅助二极管GD1，GD2中的每一个被实现为GaN晶体管，其具有连接到一个电极232（例如源极）的栅极（G）电极230。每个GaN晶体管的另一个电极234 被定义为阴极（K）。
图17A和17B示出了形成在图1，2，4，6，7和12中所示的单片集成的放电电路102的控制晶体管Q3，Q4的实施例的相应的横截面图。根据在图17A和17B中示出的实施例，控制晶体管Q3，Q4被实现为单独的GaN晶体管或被实现为在图17中看不见的与主双向开关100单片集成的辅助双向GaN开关。栅极G3和G4两者在图1中连接在一起并浮置，并且在图2中分开并浮置。栅极G3和G4在图4中分别连接到辅助二极管GD1和GD2的相应阳极，并且在图6，7和12中分别与辅助二极管GD1和GD2的相应阳极断开。
放电电路102的晶体管Q3和Q4可以被实现为形成在III族氮化物异质结构体202/203/204中的第一和第二栅极G3，G4，第一和第二漏极D3，D4，以及公共源极S3/S4。公共源极S3/S4位于栅极G3，G4之间。如前所述，控制晶体管Q3，Q4的栅极G3，G4中的每个与栅极驱动电路解耦合。因此，放电电路102的栅极G3，G4至少无源地（并且可能是有源地）并且基于主双向开关100的状态而被控制。公共源极区S3/S4可以形成为如图17A中所示的电连接在一起的分开的电极236，或者代之以形成为如图17B中所示的单个电极236'。
图18示出在图6所示的以诸如GaN之类的III族氮化物技术实现为化合物半导体器件的一部分的电路实施例的横截面图。类似于图9，主双向开关100形成在诸如Si衬底之类的半导体衬底200和一个或多个可选的缓冲层上。在半导体衬底200之上形成III族氮化物缓冲区202，在III族氮化物缓冲区202之上形成III族氮化物沟道区203（例如GaN），并且在III族氮化物沟道区203之上形成III族氮化物势垒区204。图6中所示的主晶体管Q1和Q2可以被实现为第一和第二栅极G1，G2，第一和第二源极S1，S2和公共漏极。公共漏极位于栅极G1，G2之间。图18还示意性地示出了图6中所示的具有辅助二极管GD1，GD2和衬底二极管Sb1，Sb2的放电电路102。
如前所解释的那样，图6和18中所示的衬底二极管Sb1，Sb2和辅助二极管GD1，GD2中的每个可以与主双向开关100和放电电路102单片地集成，例如，如在图13A至16中所示的那样。例如，图6和18中所示的每个衬底二极管Sb1和Sb2可以是GaN二极管，其包括具有电极（阳极，A）的p掺杂区（例如pGaN）和具有另一电极（阴极，K）的二维电子空穴气（2DEG）。可以通过器件的二极管区域中的III族氮化物沟道区203和III族氮化物势垒区204之间的自发和压电极化来形成2DEG。可以通过以诸如镁之类的适当的掺杂剂种类掺杂III族氮化物层203来形成III族氮化物势垒区204上的p掺杂区205。由于衬底二极管Sb1，Sb2的阳极如图6和18中所示的（电）连接到半导体衬底200，所以具有其电极的p掺杂区可以被形成为电连接在一起的分开的区域或被形成为具有其单个电极的单个p掺杂区。在另一实施例中，衬底二极管Sb1，Sb2中的每个被实现为GaN晶体管，其具有连接到其电极之一的其栅极（G）。连接到栅极的电极充当阳极并且另一个电极被定义为阴极。两个阳极彼此电连接，而每个阴极连接到Vss1或Vss2，例如，如图6中所示。由于系连到衬底栅极二极管Sb1和Sb2中的栅极的两个电极电连接，所以可以使用单个公共电极而不是两个分开的电极。每个辅助二极管GD1，GD2可以包括p掺杂区205（例如pGaN），具有作为阳极的其电极和作为阴极的III族氮化物势垒区204（例如AlGaN）上的另一电极。可以通过在器件的二极管区域中的III族氮化物沟道区203和III族氮化物势垒区204之间的自发和压电极化来形成二维电子气（2DEG）。可以通过以诸如镁之类的合适的掺杂剂种类生长III族氮化物层来形成在III族氮化物势垒区204上的p掺杂的阳极区205。在又一个实施例中，辅助二极管GD1，GD2中的每个可以被实现为GaN晶体管，其具有连接到其电极（例如源极）的栅极（G）。由于每个辅助二极管GD1，GD2的阳极（电）连接到控制晶体管Q3，Q4的栅极G3/G4之一，例如如图6和18中所示，所以每个辅助二极管GD1，GD2的p掺杂的阳极区205可以被形成为两个分开的区域。
类似于在图6和18中所示的形成单片集成的放电电路102的控制晶体管Q3，Q4，控制晶体管Q3，Q4可以例如如图17A和17B中所示的那样被实现为一对单独的GaN晶体管或与主双向开关100单片集成的辅助双向GaN开关。例如，放电电路102的控制晶体管Q3和Q4可以被实现为形成在III族氮化物异质结构体202/203/204中的第一和第二栅极G3，G4，第一和第二漏极D3，D4，以及公共源极S3/S4。公共源极S3/S4位于栅极G3，G4之间。如前所述，控制晶体管Q3，Q4的栅极G3，G4中的每个与栅极驱动电路解耦合。因此，放电电路102的栅极G3，G4至少无源地（并且可能是有源地）并且基于主双向开关100的状态而被控制。公共源极区S3/S4可以被形成为电连接在一起的分开的电极或被形成为单个电极。
图19示出在图1所示的电路实施例的横截面图，以诸如GaN之类的III族氮化物技术将电路实施例实现为化合物半导体器件的部分。类似于图9，主双向开关100形成在诸如Si衬底之类的半导体衬底200上，或是在Si衬底上的一个或多个外延生长或注入的Si层。III族氮化物缓冲区202在半导体衬底200之上形成，III族氮化物沟道区203（例如GaN）在III族氮化物缓冲区202之上形成，并且III族氮化物势垒区204在III族氮化物沟道区203之上形成。图1中所示的主晶体管Q1和Q2可以被实现为第一和第二栅极G1，G2，第一和第二源极S1，S2以及公共漏极。公共漏极位于栅极G1，G2之间。图19还示意性地示出了图1中所示的放电电路102和衬底二极管Sb1，Sb2。
如本文先前所解释的，在图1和19中示出的衬底二极管Sb1，Sb2可以是GaN二极管，其包括具有电极（阳极，A）的p掺杂区205（例如pGaN）和具有另一电极（阴极，K）的二维电子空穴气（2DEG），例如如图10A和10B中所示。可以通过器件的二极管区域中的III族氮化物沟道区203和III族氮化物势垒区204之间的自发和压电极化来形成2DEG。可以通过以诸如镁之类的适当的掺杂剂种类掺杂III族氮化物层203形成III族氮化物势垒区204上的p掺杂区205 。由于衬底二极管Sb1，Sb2的阳极（电）连接到半导体衬底200，如图1中所示，所以p掺杂的阳极区可以被形成为例如如图10A中所示的电连接在一起的分开的区域，或者被形成为例如如图10B中所示的单个p掺杂区。
衬底二极管Sb1，Sb2可以被代之以实现为相应的GaN晶体管，其中每个具有连接到其源极（S）的其栅极（G），例如，如图11A和11B中所示。由于衬底二极管Sb1，Sb2的阳极和栅极（电）连接到半导体衬底200，所以p掺杂的阳极区205可以被形成为电连接在一起的分开的区域或者被形成为单个p掺杂区。
类似地，图1和图24中所示的形成单片集成的放电电路102的控制晶体管Q3，Q4可以例如如图17A和17B中所示的那样被实现为在III族氮化物异质结构体202/203/204中的第一和第二栅极G3，G4，第一和第二漏极D3，D4和公共源极S3/S4。公共源极S3/S4位于栅极G3，G4之间。控制晶体管Q3和Q4的栅极G3，G4中的每个如前所述的那样与栅极驱动电路解耦合。因此，放电电路102的栅极G3，G4至少无源地（并且可能是有源地）并且基于主双向开关100的状态而被控制。公共源极区S3/S4可以被形成为电连接在一起的分开的电极或被形成为单个电极。单片集成的控制晶体管Q3，Q4的栅极G3，G4连接在一起并且可以是浮置的。例如，该连接可以由金属线形成。可以省略连接，使得单片集成的控制晶体管Q3，Q4的栅极G3，G4彼此断开并且每个都浮置，例如如图2中所示。
图20示出在图4所示的电路实施例的横截面图，以诸如GaN之类的III族氮化物技术将电路实施例实现为化合物半导体器件的部分。类似于图9，主双向开关100形成在诸如Si衬底之类的半导体衬底200和一个或多个可选的缓冲层上。III族氮化物缓冲区202在半导体衬底200之上形成，III族氮化物沟道区203（例如GaN）在III族氮化物缓冲区202之上形成，并且III族氮化物势垒区204在III族氮化物沟道区203之上形成。图4中所示的晶体管Q1和Q2可以被实现为第一和第二栅极G1，G2，第一和第二源极S1，S2以及公共漏极。公共漏极位于栅极G1，G2之间。图20还示意性地示出了图4中所示的放电电路102，衬底二极管Sb1，Sb2和辅助二极管GD1，GD2。
每个二极管Sb1，Sb2，GD1，GD2与主双向开关100和放电电路102单片地集成，并且可以是例如如针对衬底二极管Sb1和Sb2在图10A和10B中以及针对辅助二极管GD1，GD2在图13A和13B中所示的具有电极（阳极，A）的p掺杂区205（例如pGaN）和具有另一电极（阴极，K）的二维电子气（2DEG）。可以通过器件的二极管区域中的III族氮化物沟道区203和III族氮化物势垒区204之间的自发和压电极化来形成2DEG。可以通过也诸如镁之类的适当的掺杂剂种类掺杂III族氮化物层203来形成 III族氮化物势垒区204上的p掺杂区205。每个辅助二极管GD1，GD2的阳极（电）连接到控制晶体管Q3，Q4的栅极G3/G4之一，如图4和20中所示。每个辅助二极管GD1，GD2的p掺杂的阳极区可以被形成为电连接在一起的两个分开的区或被形成为单个p掺杂区。在衬底二极管Sb1，Sb2的情况下，如图4中所示，阳极（电）连接到半导体衬底200，并且可以被形成为电连接在一起的分开的p掺杂区或被形成为单个p掺杂区。
每个二极管Sb1，Sb2，GD1，GD2可以例如如针对衬底二极管Sb1，Sb2在图11A和11B中以及针对辅助二极管GD1，GD2在图14A和14B中所示的被实现为GaN晶体管，其具有连接到其源极（S）的其栅极（G）。衬底二极管Sb1，Sb2和辅助二极管GD1，GD2的阳极（电）连接到半导体衬底200。衬底二极管Sb1，Sb2和辅助二极管GD1，GD2的栅极区被形成为电连接在一起的分开的区域。
图4和20中所示的形成单片集成的放电电路102的控制晶体管Q3，Q4可以被实现为在III族氮化物异质结构体202/203/204中形成的第一和第二栅极G3，G4，第一和第二漏极D3，D4，以及公共源极S3/S4，例如如图17A和17B中所示。公共源极S3/S4位于栅极G3，G4之间。控制晶体管Q3和Q4的栅极G3，G4中的每个与栅极驱动电路解耦合，如前所述的那样。因此，放电电路102的栅极G3，G4至少无源地（并且可能是有源地）并且基于主双向开关100的状态而被控制。公共源极区S3/S4可以被形成为电连接在一起的分开的电极或被形成为单个电极。
单片集成的放电电路102 的控制晶体管Q3和Q4可以是高欧姆器件，即具有比主双向开关100的晶体管Q1，Q2 更高的Rdson（导通状态电阻）的器件。通过使用高欧姆器件，不需要显著有源区或对整体设计的改变来将放电电路102与主双向开关100单片集成。例如，放电电路102的控制晶体管Q3和Q4可以具有大于1 Ohm的Rdson，和/或控制晶体管Q3和Q4的大小可以在主双向开关100的大小的1/50到1/100之间。
主双向开关100和单片集成的放电电路102可以形成功率电路的部分，其中，主双向开关100使能功率电路内的双向电流流动。例如，功率电路可以是无桥PFC（功率因数校正）级，太阳能微逆变器（solar microinverter），AC-DC转换器，AC-AC转换器，AC反激转换器（flyback converter）等。还有其他类型具有双向电流流动的功率电路可以使用主双向开关100和单片集成的放电电路102。
图21示出了主双向开关100的实施例的横截面图，以诸如GaN高电子迁移率晶体管（HEMT）之类的III族氮化物技术将该主双向开关100实现为化合物半导体器件的部分。图21中所示的实施例类似于图9中所示的实施例。此外，还示出了衬底控制电路300，其电连接到衬底200。
图22示出了包括图21中所示的化合物半导体器件的半导体管芯（芯片）400的俯视图。半导体管芯400还包括相应的栅极电极402，404，用于提供到主双向开关100的晶体管Q1，Q2的栅极（G1，G2）的外部电连接的点，以及相应的源极电极406，408，用于提供到主双向开关100的晶体管Q1，Q2的源极（S1，S2）的外部电连接的点。主双向开关100的晶体管Q1，Q2在半导体管芯400的有源器件区410中实现。半导体管芯400还包括用于提供到半导体衬底200的外部电连接的点的衬底电极206。电极206，402，404，406，408可以被提供作为半导体管芯400的一个或多个图案化金属化层。
图23示出了主双向开关100的另一个实施例的横截面图，以诸如GaN高电子迁移率晶体管（HEMT）之类的III族氮化物技术将主双向开关100实现为化合物半导体器件的部分。图23中所示的实施例类似于图21中所示的实施例。然而，不同的是，省略了衬底二极管Sb1和Sb2。
图24示出了半导体管芯（芯片）500的俯视图，其包括图23中所示的化合物半导体器件。如上所述，半导体管芯500还包括相应的栅极电极402，404，用于提供到主双向开关100的晶体管Q1，Q2的栅极（G1，G2）的外部电连接的点，以及相应的源极电极406，408，用于提供到主双向开关100的晶体管Q1，Q2的源极（S1，S2）的外部电连接的点。如上所述，半导体管芯400还包括衬底电极206，用于提供到半导体衬底200的外部电连接的点。
空间相对术语，诸如“之下”，“下方”，“下部”，“之上”，“上部”以及诸如此类被用于简化描述，以解释一个元素相对于第二元素的定位。除了与图中所示的朝向不同的朝向之外，这些术语旨在包括设备的不同朝向。此外，诸如“第一”，“第二”以及诸如此类的术语也用于描述各种元素，区域，部分等，并且也没有旨在进行限制。贯穿说明书，相同的术语指代相同的元素。
如本文中所用，“具有”，“含有”，“包括”，“包含”以及诸如此类的术语是开放式术语，其指示所陈述的元素或特征的存在，但是也不排除附加的元素或特征。除非上下文另有明确指示，否则冠词“一”，“一个”和“该”旨在包括复数以及单数。
在记着变化和应用的上述范围的情况下，应当理解，本发明并不受前面描述的限制，也不受附图的限制。相反，本发明仅受以下权利要求书及其合法等同物的限制。

Claims (20)

1. 一种半导体器件，包括：
主双向开关，其形成在半导体衬底上并且包括第一和第二栅极，电连接到第一电压端的第一源极，电连接到第二电压端的第二源极，以及公共漏极；以及
放电电路，其包括与主双向开关单片集成的并且以公共源极配置连接到半导体衬底的辅助双向开关或多个单独的晶体管，多个单独的晶体管或辅助双向开关包括连接到主双向开关的第一源极的第一漏极，连接到主双向开关的第二源极的第二漏极，以及第一和第二栅极，第一和第二栅极中的每个与栅极驱动电路解耦合,使得至少无源地并且基于主双向开关的状态控制第一和第二栅极。
2.根据权利要求1所述的半导体器件，
其中主双向开关具有四个主要操作状态：断开/断开，其中主双向开关的两个栅极都断开；导通/导通，其中主双向开关的两个栅极都导通；导通/断开，其中主双向开关的第一栅极导通并且主双向开关的第二栅极断开；以及断开/导通，其中主双向开关的第一栅极断开并且主双向开关的第二栅极导通，
其中放电电路被配置为响应于主双向开关从导通/断开状态或断开/导通状态转变到导通/导通状态而自动地使半导体衬底放电到第一电压端和/或第二电压端。
3.根据权利要求1所述的半导体器件，还包括：
与主双向开关单片集成的第一二极管和第二二极管，
其中第一二极管的阳极和第二二极管的阳极连接到半导体衬底，
其中第一二极管的阴极连接到主双向开关的第一源极，
其中第二二极管的阴极连接到主双向开关的第二源极。
4.根据权利要求3所述的半导体器件，其中放电电路的辅助双向开关或多个单独的晶体管的第一和第二栅极连接在一起并且浮置。
5.根据权利要求3所述的半导体器件，其中放电电路的辅助双向开关或多个单独的晶体管的第一和第二栅极彼此断开并且每个都浮置。
6.根据权利要求3所述的半导体器件，其中第一二极管和第二二极管中的每个都是GaN二极管，所述GaN二极管包括p掺杂区和作为阳极的第一电极，以及二维电子气和作为阴极的第二电极。
7.根据权利要求3所述的半导体器件，其中第一二极管和第二二极管中的每个都是GaN晶体管，所述GaN晶体管具有连接到源极或漏极的栅极。
8.根据权利要求1所述的半导体器件，还包括：
与主双向开关单片集成的第一二极管和第二二极管，
其中第一二极管的阳极连接到放电电路的辅助双向开关或多个单独的晶体管的第一栅极，
其中第一二极管的阴极连接到主双向开关的第一源极，
其中第二二极管的阳极连接到放电电路的辅助双向开关或多个单独的晶体管的第二栅极，
其中第二二极管的阴极连接到主双向开关的第二源极。
9.根据权利要求8所述的半导体器件，其中第一二极管和第二二极管中的每个都是GaN二极管，所述GaN二极管包括p掺杂区和作为阳极的第一电极，以及二维电子气和作为阴极的第二电极。
10.根据权利要求8所述的半导体器件，其中第一二极管和第二二极管中的每个都是GaN晶体管，所述GaN晶体管具有连接到源极或漏极的栅极。
11.根据权利要求8所述的半导体器件，还包括：
与主双向开关单片集成的第三二极管和第四二极管，
其中第三二极管的阳极和第四二极管的阳极连接到半导体衬底，
其中第三二极管的阴极连接到主双向开关的第一源极，
其中第四二极管的阴极连接到主双向开关的第二源极。
12.根据权利要求1所述的半导体器件，还包括：
与主双向开关单片集成的第一二极管和第二二极管，
其中第一二极管的阳极连接到放电电路的辅助双向开关或多个单独的晶体管的第二栅极，
其中第一二极管的阴极连接到主双向开关的第一源极，
其中第二二极管的阳极连接到放电电路的辅助双向开关或多个单独的晶体管的第一栅极，
其中第二二极管的阴极连接到主双向开关的第二源极。
13.根据权利要求12所述的半导体器件，其中第一二极管和第二二极管中的每个都是GaN二极管，所述GaN二极管包括p掺杂区和作为阳极的第一电极，以及二维电子气和作为阴极的第二电极。
14.根据权利要求12所述的半导体器件，其中第一二极管和第二二极管中的每个都是GaN晶体管，所述GaN晶体管具有连接到源极或漏极的栅极。
15.根据权利要求12所述的半导体器件，还包括：
与主双向开关单片集成的第三二极管和第四二极管，
其中第三二极管的阳极和第四二极管的阳极连接到半导体衬底，
其中第三二极管的阴极连接到主双向开关的第一源极，
其中第四二极管的阴极连接到主双向开关的第二源极。
16.根据权利要求12所述的半导体器件，其中半导体器件在主双向开关的第一源极与半导体衬底之间，以及在主双向开关的第二源极与半导体衬底之间没有二极管连接。
17.根据权利要求1所述的半导体器件，其中主双向开关和多个单独的晶体管或辅助双向开关中的每个都是GaN器件。
18. 根据权利要求1所述的半导体器件，其中多个单独的晶体管或辅助双向开关具有大于1 Ohm的Rdson，和/或其中多个单独的晶体管或辅助双向开关在主双向开关的大小的1/50和1/100之间。
19.根据权利要求1所述的半导体器件，其中多个单独的晶体管包括以公共源极配置连接的多个单独的HEMT器件，使得第一漏极在第一方向上功能性地提供源极，并且第二漏极在与第一个方向相反的第二方向上提供源极功能性。
20.一种功率电路，其包括根据权利要求1所述的半导体器件，其中主双向开关被配置为使能功率电路内的双向电流流动。
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