WO2024167620A1

WO2024167620A1 - Configurations for four quadrant iii-nitride switches

Info

Publication number: WO2024167620A1
Application number: PCT/US2024/011458
Authority: WO
Inventors: Carl Joseph Neufeld; David Michael Rhodes; Davide BISI; Geetak GUPTA; Rakesh K. Lal
Original assignee: Transphorm Technology, Inc.
Priority date: 2023-02-10
Filing date: 2024-01-12
Publication date: 2024-08-15

Abstract

An electronic component comprises semiconductor devices including a four-quadrant switch (FQS), a first enhancement-mode transistor, and a second enhancement-mode transistor. The FQS is a depletion-mode III-N device including a first power electrode, a second power electrode, and a second gate. The FQS further comprises a III-N material structure, where a compositional difference in the III-N material structure forms a 2DEG channel therein, and a first internal resistor formed of a first portion of the 2DEG channel, and a second internal resistor formed of a second portion of the 2DEG channel. A first drain of the first enhancement-mode transistor is electrically connected and physically mounted to the first power electrode, and a second drain of the second enhancement-mode transistor is electrically connected and physically mounted to the second power electrode.

Description

CONFIGURATIONS FOR FOUR QUADRANT III-NITRIDE SWITCHES

TECHNICAL FIELD

[0001] The disclosed technologies relate to semiconductor devices and modules designed to achieve increased performance and reliability.

BACKGROUND

[0002] Currently, typical power semiconductor devices, including devices such as transistors, diodes, power MOSFETs, bi-directional switches, and insulated gate bipolar transistors (IGBTs), are fabricated with silicon (Si) semiconductor material. More recently, wide-bandgap materials (SiC, III-N, ni-O, diamond) have been considered for power devices due to their superior properties. Ill-Nitride or III-N semiconductor devices, such as gallium nitride (GaN) devices, are now emerging as attractive candidates to carry large currents, support high voltages, and provide very low on-resistance with fast switching times.

[0003] One type of semiconductor device which is gaining interest is a device that can block positive and negative voltage and can modulate positive and negative current. This device is commonly referred to as a four-quadrant switch (i.e., FQS). This device is of interest for high frequency operation in extremely low loss resonant mode topologies, bi-directional converters, solar inverters & microinverters, high performance adapters & LED drivers, battery /ultracapacitor power management systems, current-source inverters or matrix inverters for motor drives. If well designed, such devices can demonstrate low loss, low on-resistance, fast switching times, and can often be able to withstand large voltages, typically 600- 1200V

[0004] For some applications, the FQS device is an enhancement-mode (i.e., E-mode) device, which is normally-off and has a positive threshold voltage. The use of E-mode devices can prevent damage to the device or other circuit components and in case of circuit failure can prevent any accidental turn-on of the device. A FQS device is superior to a traditional III-N HEMT transistor for some applications because it can allow substantial current to flow in both directions as well as block substantial voltage in both directions (e.g., voltages similar to the highest rating of the device in both directions). [0005] Figure 1 shows a circuit schematic of an enhancement-mode FQS switch 100, of the prior art, which includes transistor 110. The switch includes a first electrode 123 which can alternate between a drain electrode or a source electrode (e.g., a D/S electrode) depending on the voltage polarity of the circuit. The switch further includes a second electrode 133 which can alternate between a source electrode or a drain electrode (e.g., a S/D electrode), whichever the first electrode is not, depending on the voltage polarity of the circuit. Switch 100 includes a first gate electrode 122 and a second gate electrode 132. Switch 100 also includes node 111 which can represent the substrate of transistor 110. Applying a voltage bias to node 111 will bias the voltage of the substate of transistor 110.

[0006] One type of device which is showing promising benefits when used as the enhancement-mode FQS switch 100 of Figure 1, is the III-N high electron mobility transistor (HEMT). However, reliable design, fabrication and operation of high-voltage normally-off III-N bi-directional switches has thus far proven to be very difficult. The main challenges are (1) back-gating cross-talk between the two sides of each FQS and (2) assembly complexity. As such, alternative configurations are needed to accelerate the market adaptation of III-N FQS switches.

SUMMARY

[0007] Described herein are four quadrant III-N switches and corresponding modules, any of which is suitable for operation as a four quadrant switch (i.e., a FQS). These devices or modules can be incorporated to form an electronic component package. The design of the modules, coupled with the design of the III-N devices used in the modules, can result in reduced inductances as well as other parasitics, thereby allowing for higher circuit stability and improved performance. The electronic modules can also have a reduced size and can be easier to assemble than conventional FQS switches, such as silicon IGBTs, thereby allowing for lower production costs and higher reliability. The term “device” will be used in general for any transistor or switch or diode when there is no need to distinguish between them.

[0008] In a first aspect, an electronic component is described. The component includes a four-quadrant switch (FQS), a first enhancement-mode transistor, and a second enhancement-mode transistor. The FQS is a depletion-mode III-N device including a first power electrode, a second power electrode, and a second gate. The FQS further comprises a III-N material structure, where a compositional difference in the III-N material structure forms a 2DEG channel therein, and a first internal resistor formed of a first portion of the 2DEG channel, and a second internal resistor formed of a second portion of the 2DEG channel. A first drain of the first enhancement-mode transistor is electrically connected and physically mounted to the first power electrode, and a second drain of the second enhancement-mode transistor is electrically connected and physically mounted to the second power electrode, where a first terminal of the first internal resistor is connected to the first gate of the III-N device, and a second terminal of the first internal resistor is electrically connected to the first drain of the enhancement-mode transistor, and a first terminal of the second internal resistor is connected to the second gate of the III-N device, and a second terminal of the second internal resistor is electrically connected to the second drain of the second enhancement-mode transistor.

[0009] In a second aspect, an electronic component is described. The electronic component includes a package, a first terminal, a second terminal, a third terminal, a fourth terminal, a structural package base, an insulating shim, and a hybrid enhancementmode four-quadrant switch. The four-quadrant switch includes a III-N depletion-mode device, a first enhancement-mode transistor, and a second enhancement-mode transistor. The depletion-mode III-N device includes a substrate, a first power electrode, a second power electrode, a first gate, a second gate, and a III-N material structure, where a compositional difference in the III-N material structure forms a 2DEG channel therein. The first enhancement-mode transistor includes a first drain, a first source, and a third gate. The second enhancement-mode transistor includes a second drain, a second source, and a fourth gate. The first drain of the first enhancement-mode transistor is electrically connected and physically mounted to the first power electrode, and the second drain of the second enhancement-mode transistor is electrically connected and physically mounted to the second power electrode. The insulating shim includes an insulating layer, a first metal layer and a second metal lay on a side of the insulating layer opposite the first metal layer, and the second meatal layer is physically mounted to the structural package base. The first metal layer includes at least five portions, each electrically isolated from the other by a trench formed through the first metal layer. The substrate of the III-N depletion-mode device is attached to the first portion of the first metal layer, and the third gate of the first enhancement-mode transistor is electrically connected to the second portion of the first metal layer, the third portion of the first metal layer is electrically connected to the first terminal of the electronic package, and a first ferrite bead is connected between the second portion and the third portion of the first metal layer, and the fourth gate of the second enhancement-mode transistor is electrically connected to the fourth portion of the first metal layer, the fifth portion of the first metal layer is electrically connected to the second terminal, and a second ferrite bead is connected between the fourth portion and the fifth portion of the first metal layer.

[0010] In a third aspect, and electronic circuit is described. The electronic circuit includes a high-voltage node, a ground node, a first resistor, a second resistor, a four- quadrant switch (FQS), a first enhancement-mode transistor, and a second enhancementmode transistor. The FQS is a depletion-mode III-N device including a first power electrode, a second power electrode, a first gate, and a second gate. The first enhancement-mode transistor includes a first drain, a first source, and a third gate. The second enhancement-mode transistor includes a second drain, a second source, and a fourth gate. The first drain of the first enhancement-mode transistor is electrically connected to the first power electrode, and the second drain of the second enhancementmode transistor is electrically connected to the second power electrode. The first gate of the depletion-mode III-N device and the first source of the first enhancement-mode transistor are electrically connected to the high-voltage node. The second gate of the depletion-mode III-N device and the second source of the second enhancement-mode transistor are electrically connected to the ground node, where the first terminal of the first resistor is connected to the first gate of the III-N device, and a second terminal of the first internal resistor is electrically connected to the first drain of the first enhancementmode transistor, and the first terminal of the second resistor is connected to the second gate of the III-N device, and a second terminal of the second resistor is electrically connected to the second drain of the second enhancement-mode transistor.

[0011] Each of the electronic modules and/or transistors described herein can include one or more of the following features. The first internal resistor and the second internal resistor can have a resistance between IMohm-lOOMohm. The resistance of the first internal resistor and the second internal resistor can be formed using a portion of the 2DEG channel charge. The electronic package can be a TO-type package. The first ferrite bead can be connected between the first gate of the first enhancement-mode transistor and the first terminal, and a second ferrite bead can be connected between the second gate of the second enhancement-mode transistor and the fourth terminal. The first ferrite bead and the second ferrite bead can form a low pass filter configured to reduce oscillations having frequencies above 100 MHz. The first gate of the depletion-mode III- N device and the first source of the first enhancement-mode device can be electrically connected to the third terminal of the electronic package. The second gate of the depletion-mode III-N device and the second source of the second enhancement-mode device can be electrically connected to the fourth terminal of the electronic package. The substrate of the depletion-mode device and the first portion of the first metal layer can be electrically isolated from the first, second, third, and fourth terminals of the electronic package. The substrate of the depletion-mode device can be maintained at a floating potential. The high-voltage node can be greater than 600V. When the first gate is biased below a first threshold voltage and the second gate is biased above a second threshold voltage, substantial current can flow through a channel of the depletion-mode III-N device in a first direction. When the first gate is biased above the first threshold voltage and the second gate is biased below the second threshold voltage, substantial current can flow through the channel of the depletion-mode III-N device in a second direction. When the first gate is biased below the first threshold voltage and the second gate is biased below the second threshold voltage, substantial current can be blocked through the channel of the depletion-mode III-N device in both the first and second directions. The depletion-mode III-N device can be an AlGaN/GaN HEMT.

[0012] As used herein, a “hybrid enhancement-mode electronic device or component”, or simply a “hybrid device or component”, is an electronic device or component formed of a depletion-mode transistor and an enhancement-mode transistor, where the depletion-mode transistor is capable of a higher operating and/or breakdown voltage as compared to the enhancement-mode transistor, and the hybrid device or component is configured to operate similarly to a single enhancement-mode transistor with a breakdown and/or operating voltage about as high as that of the depletion-mode transistor. That is, a hybrid enhancement-mode device or component includes at least 3 nodes having the following properties. When the first node (source node) and second node (gate node) are held at the same voltage, the hybrid enhancement-mode device or component can block a positive high voltage (i.e., a voltage larger than the maximum voltage that the enhancement-mode transistor is capable of blocking) applied to the third node (drain node) relative to the source node. When the gate node is held at a sufficiently positive voltage (i.e., greater than the threshold voltage of the enhancement-mode transistor) relative to the source node, current passes from the source node to the drain node or from the drain node to the source node when a sufficiently positive voltage is applied to the drain node relative to the source node. When the enhancement-mode transistor is a low-voltage device and the depletion-mode transistor is a high-voltage device, the hybrid component can operate similarly to a single high-voltage enhancement-mode transistor. The depletion-mode transistor can have a breakdown and/or maximum operating voltage that is at least two times, at least three times, at least five times, at least ten times, or at least twenty times that of the enhancement-mode transistor.

[0013] As used herein, the terms III-Nitride or III-N materials, layers, devices, etc., refer to a material or device comprised of a compound semiconductor material according to the stoichiometric formula BwAl_xIn_yGa_zN, where w+x+y+z is about 1 with 0 < w < l, 0 < x < l, 0 < y < 1, and 0 < z < 1. III-N materials, layers, or devices, can be formed or prepared by either directly growing on a suitable substrate (e.g., by metal organic chemical vapor deposition), or growing on a suitable substrate, detaching from the original substrate, and bonding to other substrates.

[0014] As used herein, two or more contacts or other items such as conductive channels or components are said to be “electrically connected” if they are connected by a material which is sufficiently conducting to ensure that the electric potential at each of the contacts or other items is intended to be the same, e.g., is about the same, at all times under any bias conditions.

[0015] As used herein, “blocking a voltage” refers to the ability of a transistor, device, or component to prevent significant current, such as current that is greater than 0.001 times the operating current during regular conduction, from flowing through the transistor, device, or component when a voltage is applied across the transistor, device, or component. In other words, while a transistor, device, or component is blocking a voltage that is applied across it, the total current passing through the transistor, device, or component will not be greater than 0.001 times the operating current during regular conduction. Devices with off-state currents which are larger than this value exhibit high loss and low efficiency, and are typically not suitable for many applications, especially power switching applications.

[0016] As used herein, a “high-voltage device”, e.g., a high-voltage switching transistor, HEMT, bidirectional switch, or four-quadrant switch (FQS), is an electronic device which is optimized for high-voltage applications. That is, when the device is off, it is capable of blocking high voltages, such as about 300V or higher, about 600V or higher, or about 1200V or higher, and when the device is on, it has a sufficiently low on- resistance (RON) for the application in which it is used, e.g., it experiences sufficiently low conduction loss when a substantial current passes through the device. A high-voltage device can at least be capable of blocking a voltage equal to the high-voltage supply or the maximum voltage in the circuit for which it is used. A high-voltage device may be capable of blocking 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltage required by the application. In other words, a high-voltage device can block all voltages between 0V and at least Vmax, where Vmax is the maximum voltage that can be supplied by the circuit or power supply, and Vmax can for example be 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltage required by the application. For a bidirectional or four quadrant switch, the blocked voltage could be of any polarity less a certain maximum when the switch is OFF (±V_max such as +300V or +600V, +1200V and so on), and the current can be in either direction when the switch is ON.

[0017] As used herein, a “III-N device” is a device having a conductive channel formed in a ni-N material. A III-N device can be designed to operate as a transistor or switch in which the state of the device is controlled by a gate terminal or as a two terminal device that blocks current flow in one direction and conducts in another direction without a gate terminal. The III-N device can be a high-voltage device suitable for high voltage applications. In such a high-voltage device, when the device is biased off (e.g., the voltage on the gate relative to the source is less than the device threshold voltage), it is at least capable of supporting all source-drain voltages less than or equal to the high-voltage in the application in which the device is used, which for example may be 100V, 300V, 600V, 1200V, 1700V, 2500V, or higher. When the high voltage device is biased on (e.g., the voltage on the gate relative to the source or associated power terminal is greater than the device threshold voltage), it is able to conduct substantial current with a low on-voltage (i.e., a low voltage between the source and drain terminals or between opposite power terminals). The maximum allowable on-voltage is the maximum on-state voltage that can be sustained in the application in which the device is used.

[0018] The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one layer with respect to other layers. As such, for example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in contact with that second layer. Additionally, the relative position of one layer with respect to other layers is provided assuming operations are performed relative to a substrate without consideration of the absolute orientation of the substrate.

[0019] In typical power switching applications in which high-voltage switching transistors are used, the transistor is during the majority of time in one of two states. In the first state, which is commonly referred to as the “ON state”, the voltage at the gate electrode relative to the source electrode is higher than the transistor threshold voltage, and substantial current flows through the transistor. In this state, the voltage difference between the source and drain is typically low, usually no more than a few volts, such as about 0.1-5 volts. In the second state, which is commonly referred to as the “OFF state”, the voltage at the gate electrode relative to the source electrode is lower than the transistor threshold voltage, and no substantial current, apart from off-state leakage current, flows through the transistor. In this second state, the voltage between the source and drain can range anywhere from about 0V to the value of the circuit high voltage supply, which in some cases can be as high as 100V, 300V, 600V, 1200V, 1700V, or higher, but can be less than the breakdown voltage of the transistor. In some applications, inductive elements in the circuit cause the voltage between the source and drain to be even higher than the circuit high voltage supply. Additionally, there are short times immediately after the gate has been switched on or off during which the transistor is in a transition mode between the two states described above. When the transistor is in the off state, it is said to be “blocking a voltage” between the source and drain.

[0020] As used herein, an “electrode” refers to the metal layers within a device or transistor which are connected to either the source, gate or drain region of the semiconductor material of the device. A “pad” such as a “source pad, drain pad, or gate pad” refer to the uppermost un-passivated portion of the electrode which is used to electrically connect the device or transistor to the package e.g., with solder, epoxy, wirebonds and/or metal clips.

[0021] The details of one or more disclosed implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Additional features and variations may be included in the implementations as well. Other features, aspects, and advantages will become apparent from the description, the drawings and the claims.

DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a circuit schematic of an enhancement-mode FQS switch of the prior art.

[0023] Figures 2A and 2B are circuit schematics of FQS switches using a high- voltage depletion-mode III-N device and low voltage enhancement-mode devices.

[0024] Figure 3A is a cross -sectional view of a hybrid III-N FQS device.

[0025] Figures 3B and 3C are plan views of the hybrid III-N bidirectional device of Figure 3 A.

[0026] Figures 3D and 3E show a plan view and cross-sectional view, respectively, of an electronic component package.

[0027] Figure 3F shows a plan view of an electronic component package.

[0028] Figure 4A is a cross-sectional view of a hybrid FQS III-N device using an insulating substrate. [0029] Figures 4B and 4C show a plan view and cross-sectional view, respectively, of an electronic component package.

[0030] Figures 5A and 5B show a cross-sectional view and plan view, respectively, of a hybrid FQS III-N device.

[0031] Figures 5C and 5D show a plan view and cross-sectional view, respectively, of an electronic component package.

[0032] Figures 6A and 6B show a cross-sectional view and plan view, respectively, of an enhancement-mode FQS III-N device.

[0033] Figures 6C and 6D show a plan view and cross-sectional view, respectively, of an electronic component package.

[0034] Figure 7 shows a plan view of an electronic component package.

[0035] Figure 8A shows a circuit schematic of a hybrid FQS III-N switch using a common-source topology.

[0036] Figures 8B and 8C show a plan view and cross-sectional view, respectively, of an electronic component package using a common-source topology.

[0037] Figures 9A and 9B show a plan view and cross-sectional view, respectively, of an electronic component package using a common-source topology.

[0038] Figure 9C shows a cross-sectional view of an integrated enhancementmode silicon FET device.

[0039] Figure 10A shows a circuit schematic of a hybrid FQS III-N switch using an integrated driver circuit.

[0040] Figure 10B is a plan view of an electronic component package using a common-source topology and an integrated drive circuit.

[0041] Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

[0042] Described herein are III-N devices and corresponding modules, any of which is suitable for operation as a Four Quadrant Switch (i.e., a FQS). These devices or modules can be incorporated to form an electronic component package. The design of the modules, coupled with the design of the III-N devices used in the modules, can result in reduced inductances as well as other parasitics, thereby allowing for higher circuit stability and improved performance. The electronic modules can also have a reduced size and can be easier to assemble than conventional FQS switches, such as silicon IGBTs, thereby allowing for lower production costs and higher reliability.

[0043] As previously stated, reliable design, fabrication and operation of high- voltage normally-offFQS III-N devices has thus far proven to be very difficult. The main challenges are (1) back-gating cross-talk between the two sides of the FQS and (2) assembly complexity. Back-gating cross talk can happen when FQS are implemented on conductive substrates, such as silicon. The device designer must decide to what potential to connect the silicon substrate. The silicon substrate can be connected to the same potential as Terminal 1. However, in this configuration, the device operates reliably only when Terminal 1 is biased at ground potential, such as 0V (equivalent of the Source Terminal in a conventional 3-terminal device) and Terminal 2 is biased high positive voltage, such as 400 V or 800 V (equivalent of the Drain Terminal of a conventional 3- terminal device). But when the FQS is operated in the opposite direction, i.e., Terminal 1 is biased at high positive voltage and Terminal 2 is biased at ground potential, the silicon substrate, which is connected to Terminal 1, will also be biased at high-voltage such as 400 V and 800 V. When the silicon substrate is biased at high positive voltage, it will create a strong vertical field under the Terminal 2 and Gate 2, attracting electrons from the 2DEG towards the substrate. This will lead not only parasitic leakage current, but also severe electron trapping in the buffer layers. This will in turn generate severe positive threshold voltage shift of Gate 2 by several volts and severe dynamic on- resistance increase, compromising switching performance and reliability of the device. Vice versa, if the substrate is electrically connected to Terminal 2, the device will operate reliably only if Terminal 2 is biased at ground potential and Terminal 1 is biased at high voltage.

[0044] To prevent this situation, device and circuit designers have invented complex substrate switching schemes, where the substrate is switched to being connected to Terminal 1 to Terminal 2 depending on the bias conditions of the FQS. However, this solution introduced significant device and circuit complexity and suboptimal switching efficiency. Another option is to leave the substrate connection floating, i.e., not electrically connected to any terminal. In this case, when Terminal 1 is biased at 0 V and Terminal 2 is biased at high-voltage, for example 400 V, the substrate will be capacitively coupled to both Terminal 1 and Terminal 2, acquiring an intermediate potential, for example 200 V. This situation is less severe than the case previously described, but it will still cause buffer injection and threshold voltage shift of several volts under Gate 1 or Gate 2. This is not allowed in E-mode devices, where the threshold must be precisely controlled to ensure proper operations. A few volt shift in either direction (positive or negative), would make an E-mode device not usable.

[0045] One alternative to a single high-voltage E-mode FQS device is to combine a high-voltage depletion-mode (i.e., D-mode) III-N device with a first and a second low- voltage silicon enhancement-mode (i.e., E-mode) FET in a cascode type configuration. In this configuration, the substrate terminal can be left floating without affecting the threshold voltage of Gate 1 and Gate 2. In fact, Gate 1 and Gate 2 are implemented on a silicon FET separated from the GaN HEMT, therefore not affected by back-gating crosstalk. The back-gating cross-talk will still affect the gate of the GaN HEMT, causing dynamic Ron increase, for example 20-30%, but not preventing the device operations as it would on E-mode devices.

[0046] Figure 2A shows circuit schematic of a FQS switch 200 which includes a high-voltage D-mode III-N device 210. Switch 200 includes a first low-voltage E-mode transistor 220 coupled to the first power electrode of device 210 at node 224. Switch 200 includes a second low-voltage E-mode transistor 230 coupled to the second power electrode of device 210 at node 234. Switch 200 includes a first terminal 223 coupled to the source of the first E-mode transistor 220 and the first gate of the D-mode III-N device 210 through connector 225. Switch 200 includes a second terminal 233 coupled to the source of the second E-mode transistor 230 and the second gate of the D-mode III-N device 210 through connector 235. Switch 200 further includes a third terminal 222 connected to the gate of the first transistor 220 and a fourth terminal 232 connected to the gate of the second transistor 230. Optionally, switch 200 can include a first Kelvin connection 212 configured to the source of the first transistor 220, a second Kelvin connection 213 configured to the source of the second transistor 230, and a substrate connection 211 configured to be electrically connected to the substrate of III-N device 210. [0047] However, when switch 200 is operated under certain bias conditions, such as fast switching with high di/dt or dv/dt values, the first or the second transistors 220 or 230 can enter avalanche mode and the switch 200 can fail. In order to improve the reliability of switch 200, bleed resistors can be incorporated. As seen in Figure 2B, switch 202 includes a first resistor 226 (i.e., first bleed resistor) and a second resistor 236 (i.e., second bleed resistor), but is otherwise the same as switch 200 of Figure 2A. Resistor 226 can have a first terminal connected between the first power electrode of the III-N device 210 and the drain of the first E-mode transistor 220, and a second terminal connected between the first gate of device 210 and the source of the first E-mode transistor 220. The second resistor 236 can have a first terminal connected between the second power electrode of the ni-N device 210 and the drain of the second E-mode transistor 230, and a second terminal connected between the second gate of device 210 and the source of the second E-mode transistor 220. These first and/or second bleed resistors can allow leakage current to bi-pass the first and/or second E-mode transistors to prevent avalanche breakdown, resulting in improved reliability.

[0048] Figures 3A, 3B and 3C show a cross-sectional view, a first plan view, and a second plan view, respectively, of a cascode FQS switch 300 which can be used in the circuits of Figures 2A or 2B. The cascode FQS switch 300 includes a first low-voltage E-mode transistor 20 (e.g., a Silicon FET) mounted directly to the first power electrode 18A of high-voltage D-mode III-N device 10, with the drain pad 21 of the first E-mode transistor 20 directly bonded to the first electrode 18A of the D-mode III-N device 10. Switch 300 further includes a second low-voltage E-mode transistor 30 (e g., a Silicon FET) mounted directly to the second power electrode 18B of high-voltage D-mode III-N device 10, with the drain pad 31 of the second E-mode transistor 30 directly bonded to the second electrode 18B. The FQS switch 300 can be operated in the same way as a single high-voltage E-mode FQS switch and in many cases achieves the same or similar output characteristics as a single high-voltage E-mode FQS switch. The D-mode III-N device 10 has a larger breakdown voltage than the first and second E-mode transistor 20 and 30, respectively (e.g., at least three times larger). The maximum voltage that can be blocked by the FQS switch 300 while it is biased in the OFF state is at least as large as the maximum blocking or breakdown voltage of the D-mode FQS III-N device 10. [0049] Referring to Figure 3A, the first E-mode transistor 20 includes a semiconductor body layer 24. Transistor 20 further includes a first source electrode 23 and a first gate electrode 22 on a first side of a semiconductor body layer 24, and a first drain electrode 21 on a second side of the semiconductor body layer 24 opposite the first source electrode 23.

[0050] The second E-mode transistor 30 includes a semiconductor body layer 34. Transistor 30 further includes a second source electrode 33 and a second gate electrode 32 on a first side of a semiconductor body layer 34, and a second drain electrode 31 on a second side of the semiconductor body layer 34 opposite the second source electrode 33. [0051] The D-mode III-N device 10 includes a ni-N material structure 40, for example a combination of GaN and AlGaN, grown on a suitable substrate 11, which can be an electrically conductive semiconductor such as silicon (e.g., p-type or n-type doped Si), GaN (e.g., p-type or n-type GaN), or any other sufficiently electrically conductive substrate, or semi-insulating (e.g., semi-insulating silicon carbide or silicon) substrate. A back-metal layer 25 can be formed on a side of the substrate opposite the III-N material structure 40. Back-metal layer 25 can be Ti/Ni/Ag or another suitable material, which can be used as an adhesion layer to physically and/or electrically connect the substrate to a package a shim.

[0052] The III-N material structure 40 can include a III-N buffer layer 12, for example GaN or AlGaN, grown over the substrate 11. The buffer layer 12 can be rendered insulating or substantially free of unintentional n-type carriers. The buffer layer 12 can have a substantially uniform composition throughout, or the composition can vary. The thickness and composition of the buffer layer 12 can be optimized for high-voltage applications. That is, the buffer layer can be capable of blocking a voltage equal to the high-voltage supply or the maximum voltage in the circuit for which it is used. For example the buffer layer 12 may be capable of blocking greater than 600V, or greater than 900V. The thickness of the buffer layer 12 can be greater than 2pm. For example, the III-N buffer layer can have a thickness between 5pm and 10pm. For the purpose of this application, if the buffer layer is rated to block a particular voltage, then the buffer layer is considered to be electrically insulating when the device is operated at voltage less than the rated blocking voltage. [0053] The III-N material structure 40 can further include a III-N channel layer 13 (e.g., GaN) over the III-N buffer layer 12, and a III-N barrier layer 14 (e.g., AlGaN, AllnN, or AlGalnN) over the III-N channel layer 13. The bandgap of the III-N barrier layer 14 is greater than that of the III-N channel layer 13. The III-N channel layer 13 has a different composition than the III-N barrier layer 14, and the thickness and composition of the III-N barrier layer 14 is selected such that a two-dimensional electron gas (2DEG) channel 19 (indicated by the dashed line in Figure 3 A) is induced in the III-N channel layer 13 adjacent the interface between layers 14 and 13. The III-N channel layer 13 is considered to be electrically isolated from the substrate by the insulating III-N buffer layer 12 when the device is operated below the rated blocking voltage of the device. Additionally, the bleed resistors 226 and 235 shown in Figure 2B can be internal resistors integrated into the III-N material structure using the 2DEG channel charge (described in more detail in Figure 3F). The length and width of the bleed resistor can be determined based on the channel charge to get the appropriate resistor values.

[0054] Typically, III-N high electron mobility transistors (HEMTs) are formed from epitaxial (i.e., epi) III-N material structures grown by molecular beam epitaxy (MBE) or metalorganic chemical vapor deposition (MOCVD) in a reactor. The III-N material structures can be grown in a group-III polar (e.g., Ga-polar) orientation, such as the [ 0 0 0 1 ] (C-plane) orientation, as in the device shown in Figure 3A. Alternatively, III-N HEMTs can be formed on III-N material structures grown in an N-Polar (i.e., N- face) orientation, such as the [ 0 0 0 -1 ] orientation (not shown). In an N-polar device, the III-N barrier layer can be over the III-N buffer layer, and the III-N channel layer can be over the III-N barrier layer. N-polar III-N materials have polarization fields in the opposite direction to those of group-III polar III-N materials, thus enabling the implementation of III-N device structures which cannot be formed using group-III polar structures.

[0055] An insulator layer 15 (e.g., a dielectric layer) is grown or deposited over the top surface of the III-N material structure 40. The insulator layer 15 can, for example, be formed of or include Aluminum Oxide (AI2O3), Silicon Dioxide (SiO ), Si_xNy, Ali._xSi_xN, Ali-xSixO, Ali-_xSixON or any other wide bandgap insulator. Although the insulator layer 15 is shown as a single layer, it can alternatively be formed of several layers and/or materials deposited during different processing steps to form a single combined insulator layer.

[0056] A first power electrode 18A and a second power electrode 18B are formed on a side of the III-N material structure 40 opposite the substrate 11, such that the device 10 is characterized as a lateral III-N device (i.e., the first and second power electrodes are on the same side of the device and current flows through the device laterally between the first electrode 18A and the second electrode 18B when the device is biased ON). The first and second power electrode can include a portion exposed on the top surface of the device which is not encapsulated by the insulator layer 15. This portion can be used as a bonding pad to mount the first and second E-mode transistors 20 and 30. The first power electrode 18A and the second power electrode 18B can have a separation 41 along the top surface of device 10 which is at least large enough to prevent breakdown voltages or arching during operation of the device. The first power electrode 18A can alternate between a drain electrode or a source electrode (e.g., a D/S electrode) depending on the voltage polarity of the circuit. The second power electrode 18B can alternate between a source electrode or a drain electrode (e.g., a S/D electrode) depending on the voltage polarity of the circuit. The first electrode 18A and the second electrode 18B are in ohmic contact and electrically connected to the device 2DEG channel 19 that is formed in layer 13. The first and second electrodes 18A and 18B can each be formed of a stack of multiple metal layers. Each metal stack can, for example, be Ti/Al/Ni/Au, Ti/Al, or another suitable stack of metal layers.

[0057] The D-mode III-N device 10 further includes a first D-mode gate electrode 16 and a second D-mode gate electrode 17. The first and second D-mode gate electrodes 16 and 17 can be formed such that the insulator layer 15 extends between and separates the gate electrodes from the III-N material structure 40, as shown in Figure 3 A. Alternatively, the first and second D-mode gate electrodes 16 and 17 can be formed such that they are in contact with the III-N material structure 40 (not shown). The first D- mode gate 16 can include portion 16’ which extends towards the second power electrode 18B and can function as an electric field plate. The second D-mode gate 17 can include portion 17’ which extends towards the first power electrode 18A an can function as an electric field plate. The first and second D-mode gates 16 and 17 are separated by a minimum distance which is shown as separation 42 in Figure 3A. Separation 42 is large enough to support reliable device operation and support large voltages. For example, separation 42 can be between 5-50um. The first and second D-mode gate electrodes 16 and 17 can be formed of suitable conducting materials such as metal stacks, e.g., titanium/aluminum (Ti/Al) or nickel/gold (Ni/Au). The gate electrodes may alternatively be another conductive material or material stack including one or more materials having a large work function, such as a semiconductor material having a large work function (e.g., p-type poly-silicon, indium tin oxide, tungsten nitride, indium nitride, or titanium nitride). [0058] The first E-mode transistor 20 is electrically connected to the first power electrode 18A of the high-voltage D-mode III-N device 10 and the second E-mode transistor 30 is electrically connected to the second power electrode 18B to form the cascode FQS switch 300, which can be a normally-off hybrid III-N FQS device. Here, the first drain electrode 21 of the first E-mode transistor 20 is directly contacting (e.g., mounted on) and electrically connected to the first power electrode 18A of the III-N devicelO and the second drain electrode 31 of the second E-mode transistor is directly contacting (e.g., mounted on) and electrically connected to the second power electrode 18B. The first and second drain electrodes 21 and 31 of the first and second E-mode transistors 20 and 30, respectively, can be connected to the first and second power electrodesl8A and 18B of the D-mode III-N devicelO, for example, with solder, solder paste, conductive epoxy, conductive tape or other suitable attachment methods which allow for a high quality mechanical, thermal, and electrical connection between the E- mode FETs drain electrodes 21 and 3 land the D-mode III-N devices first and second power electrodesl8A and 18B. The E-mode transistors 20 and/or 30 can be mounted over the 2DEG channel 19, as shown in Figure 3A, or transistors 20 and/or 30 can be partially or fully mounted in an area outside the active area of the device such E-mode transistors are not over the 2DEG channel layer.

[0059] The first gate electrode 22 of the first E-mode transistor 20 can be configured to be connected to a first gate terminal of an electronic package, and the second gate electrode 32 of the second E-mode transistor 30 can be configured to be connected to a second gate terminal of an electronic package. The D-mode device and E- mode transistors of conventional cascode FQS switches are typically co-packed side-by- side on a ceramic insulating substrate, such as an AIN shim, and require an external wire connectors to make the E-mode drain to ni-N device power electrode connection required in a cascode FQS configuration. However, directly mounting the E-mode transistors 20 and 30 on the D-mode III-N device 10, as shown in Figures 3A, 3B, and 3C, can eliminate the need for an external wire connector and a ceramic isolating shim. This can drastically reduce the parasitic inductance of the switching circuit, allowing for higher current ratings, faster switching speeds and a lower assembly related costs.

[0060] Although the first and second gate electrode 16 and 17 of the D-mode devicelO are not shown in Figure 3A, 3B or 3C to be connected to the first and second source electrodes 23 and 33 of the first and second E-mode transistor 20 and 30, respectively (as required for a cascode FQS as shown in schematic figures 2A and 2B), these electrodes are in fact electrically connected once the cascode FQS switch 300 is mounted into a module or electronic component package, such as the packages shown in Figures 3D and 3E, since these respective electrodes are wire bonded to a common metal layer as later shown in Figures 3D.

[0061] Figure 3B is a top-down plan view of hybrid FQS switch 300. As seen in Figure 3B, cross-section A-AA (represented by the dotted line) shows an example location of a device cross-section which corresponds to the cross-sectional view shown in Figure 3A. The first gate electrode 16 of D-mode III-N device 10 includes a first gate pad 16A and (optionally) a second gate pad 16B, which can be used to wire-bond external connecting wires to the first gate electrode 16. The second gate electrode 17 of the D- mode III-N device 10 includes a third gate pad 17A and (optionally) a fourth gate pad 17B, which can be used to wire-bond external connecting wires to the second gate electrode 17.

[0062] Depletion-mode III-N devices commonly exhibit switching problems due to high GaN HEMT gate resistance and/or GaN HEMT gate inductance. If the depletionmode device’s gate width is larger than a certain size (e.g., Wg is greater than 100 mm) device performance can be negatively affected. One solution to reduce the HEMT gate resistance and gate inductance and overcome these switching issues is to have multiple gate pads on the device to allow for gate wire connections on opposite sides of the gate electrode width. When the depletion mode III-N device is a bidirectional device, four external gate connecting pads can be used. For example in switch 300, the first gate electrode 16 can have a first end connected to the first gate pad 16A, a second end connected to the second gate pad 16B, and a first gate width Wg between the first end and second end. Furthermore, the second gate electrode 17 can have a third end connected to the third gate pad 17A, a fourth end connected to the fourth gate pad 17B, and second gate width Wg between the third end and fourth end. As seen in Figure 3B, the plan view of switch 300 includes a left-side, a right-side, a top-side, and a bottom side. The first gate pad 16A and the second gate pad 16B are arranged between the leftside of switch 300 and the first E-mode transistor 20. The third gate pad 17A and the fourth gate pad 17B are arranged between the right-side of switch 300 and the second E-mode transistor 30.

[0063] An alternative embodiment switch 302 is shown in Figure 3C. Switch 302 is similar to switch 300 of Figure 3B, except that the locations of the gate pads have an alternate arrangement to allow for different packaging. As seen in Figure 3C, the first gate pad 16A and third gate pad 17A are arranged on the bottom-side of switch 302 such that the first gate pad 16A is between the bottom-side of switch 302 and the first E-mode transistor 20, and the third gate pad 17A is between the bottom-side of switch 302 and the second E-mode transistor 30. The second gate pad 16B and the fourth gate pad 17B are arranged on the top-side of switch 302 such that the second gate pad 16B is between the top-side of switch 302 and the first E-mode transistor 20 and the fourth gate pad 17B is between the top-side of switch 302 and the second E-mode transistor 30. Allowing for multiple gate pad locations as shown in Figures 3B and 3C give the designer greater freedom when designing and choose an electronic component package. This can help reduce gate wire-bond wire lengths or prevent wire-bonds from crossing over one- another when limited design freedom is allowed.

[0064] Figures 3D and 3E show a plan view and cross-sectional view, respectively, of an electronic component package 304. Package 304 includes a package case 308. Package 304 further includes a direct bonded copper (DBC) substrate 310 (best seen in Figure 3E), which can be a base substrate for the package. A DBC substrate is formed by direct bonding of pure copper in a high temperature melting and diffusion process to a ceramic insulator such as AIN or AI2O3. As seen in Figure 3E, the DBC substrate 310 includes an insulating (e.g., ceramic or AIN) substrate 315, on which a top metal layer (e.g., copper or nickel) is patterned into at least a first portion that functions as a first power plate 311, a second portion that functions as a floating plate 312, and a third portion which functions as a second power plate 313. Portions 311, 312, and 313 are each electrically isolated from one another by a trench 314 formed through the top metal layer. The DBC substrate can included a back metal layer 316 (e.g., copper or nickel) on an opposite side of the insulating substrate 315 from the top metal layer (311/312/313) which can be used to physically mount the DBC to the conductive structural package base (i.e., the lead frame 323) using solder or other methods. A heat sink 332 is mounted and thermally connected to the lead frame 323. The lead frame 323 can be configured to be connected to circuit ground, however, to mitigate back-gating cross talk as described above, the circuit can be simplified by leaving the lead frame 323 disconnected from the circuit at a “floating” voltage potential. The substrate 11 of the III- N FQS III-N device 300 is attached to the floating plate 312. The backmetal layer 25 (not shown) is attached to the floating plate 312 using solder, epoxy or another appropriate adhesive material.

[0065] Electronic component package 304 can be different types of industry standard packages. Figure 3D shows a “SO-Type” package (sometimes referred to as a SOP or SOIC type package) which includes first power terminal 322 and a second power terminal 321. The first and second power terminals 321 and 322 can switch between source terminals and drain terminals depending on the polarity of the FQS switch during operation. The source electrode 33 of the second low-voltage FET 30 is electrically connected to the first power plate 311 with wirebond 46 (which can be multiple wire bonds). The second gate electrode pads 17A and 17B are electrically connected to the first power plate 311 with wirebonds 45 A and 45B, respectively. The first power plate 311 is electrically connected to the first power terminal 322 with wirebond 58. The source electrode 23 of the first low-voltage FET 20 is electrically connected to the second power plate 313 with wirebond 41 (which can be multiple wire bonds). The first gate electrode pads 16A and 16B are electrically connected to the second power plate 313 with wirebonds 42A and 42B, respectively. The second power plate 313 is electrically connected to the second power terminal 321 with wirebond 57. [0066] Electronic component package 304 of Figure 3D further includes a first gate terminal 326 and a second gate terminal 327. The first gate terminal 326 is electrically connected to the gate electrode 22 of the first low-voltage FET 20 with wirebond 53 and the second gate terminal 327 is electrically connected to the gate electrode 32 of the second low-voltage FET 30 with wirebond 54. Optionally, the electronic component package 304 can further include a first Kelvin terminal 325 and a second Kelvin terminal 328. The first Kelvin terminal 325 is electrically connected to the source electrode 23 of the first low-voltage FET 20 with wirebond 52 and the second Kelvin terminal 327 is electrically connected to the source electrode 33 of the second low-voltage FET 30 with wirebond 55. Although the electrical connections of component package 304 have been described using wirebonds, other appropriate methods can be used such as copper clips or wire ribbons, etc.

[0067] When device 300 is used in the component package 304 (and the device is directly mounted to the DBC substrate 310) the device substrate 11 is floating and electrically isolated from the power input signals of the electronic component. Therefore, the substrate 11 does not need to be switched to match the input power voltage of either the first power terminal 322 or the second power terminal 321 during operation, as would be required if a similar silicon enhancement-mode device substrate is electrically connected and directly mounted to the package lead frame. This benefit greatly reduces circuit complexity and increases switching efficiency, allowing for faster switching speeds as well as other benefits.

[0068] Figure 3F is a plan view of a III-N device 305 which is similar to the device 300 of Figure 3D, except that III-N device 305 includes a first internal resistor terminal 28 and a second internal bleed resistor terminal 29. The first internal resistor terminal 28 at least extends below a portion of the first E-mode transistor 20 and is electrically connected to the drain of E-mode transistor 20. The second internal resistor terminal 29 at least extends below a portion of the second E-mode transistor 30 and is electrically connected to the drain of E-mode transistor 30. Referring back to Figure 2B, switch 202 shows a first bleed resistor 226 and a second bleed resistor 236. Resistor 226 has a terminal connected between the first power electrode of device 210 and the drain of transistor 220. Resistor 236 has a terminal connected between the second power electrode of device 210 and the drain of transistor 230.

[0069] Referring back to Figure 3F, the switch 305 can have a first internal bleed resistor with a first resistor terminal 28 connection electrically connected to the drain of transistor 20, and the second terminal of the first internal bleed resistor is internally connected (not shown) to the first gate of the III-N device 10. Switch 205 can have a second internal bleed resistor with a first resistor terminal 29 connection electrically connected to the drain of transistor 30, and the second terminal of the second bleed resistor is internally connected (not shown) to the second gate of the III-N device 10. The resistance of the first and second internal bleed resistors can be formed using the 2DEG channel of III-N device 10. The first and second bleed resistors can have a value between 1 Mohm to 100 Mohm, but typically between 5 Mohm to 20 Mohm.

[0070] Figure 4A shows a cross-sectional view of a hybrid cascode FQS switch 400 which can be used in the circuits of Figures 2A or 2B. Switch 400 of Figure 4 is similar to switch 300 of Figure 3A except D-mode III-N 410 in switch 400 is fabricated on an insulating substrate 411 (e.g., a sapphire substrate) instead of the conductive or semi -conductive substrate (e.g., silicon or silicon carbide) of switch 300. Fabrication of switch 400 with a sapphire substrate can have several advantages when integrating the switch into the electronic component package such as eliminating the need for an insulating DBC substrate between the switch 400 and the package base (i.e., lead frame), as further shown in Figures 4B and 4C. Insulating substrate like sapphire will also eliminate back-gating cross-talk issues. In fact, being insulating and not conductive, the electric potential in the substrate will vary across the length of the device and it will not be capacitively coupled with Terminal 1 and Terminal 2. This will prevent from high potential to be transmitted from one terminal to the other causing Vth shift and dynamic Ron issues.

[0071] Figures 4B and 4C show a plan view and cross-sectional view, respectively, of an electronic component package 402. Package 402 includes a package case 408. Package 402 further includes a direct bonded copper (DBC) substrate 410 (best seen in Figure 4C). DBC substrate 410 is similar to the DBC substrate 310 of Figure 3E, expect that the second portion of the DBC (floating plate 312) is eliminated and the substrate 411 of switch 400 is directly mounted and thermally connected to the lead frame 323. The first power plate 311 remains on a first DBC portion 410’ and the second power plate 313 remains on a third DBC portion 410” (the second DBC portion has been removed in electronic component package 402). Other features of package 402 seen in Figures 4B/4C are similar to the features of package 304 seen in Figures 3D/3E.

[0072] Similarly as described in package 304, when device 400 is used in the component package 402 (and the device is directly mounted to the lead frame 323) the device substrate 411 does not need to be switched to match the input power voltage of either the first power terminal 322 or the second power terminal 321 during operation, as would be required if a silicon enhancement-mode device substrate is electrically connected and directly mounted to the package lead frame. This benefit greatly reduces circuit complexity and increases switching efficiency, allowing for faster switching speeds as well as other benefits.

[0073] Figures 5A and Figure 5B show a cross-sectional view and plan view, respectively, of hybrid cascode FQS IILN switch 500. Switch 500 of Figure 5A is similar to switch 300 of Figure 3A, however switch 500 uses through-epi-vias (i.e., TEVs) to connect the first and second gate electrodes 16 and 17 of the D-mode III-N 520, respectively, to an electrically conductive substrate, such as a highly doped silicon substrate. A portion 512 of the conductive substrate is fully removed below the III-N material structure 40 in order to create a first substrate portion 511 A which is electrically connected to the first gate electrode 16 and a second substrate portion 51 IB which is electrically connected to the second gate electrode 17. Multiple TEVs are formed by etching a recess (or trench) through the entire thickness of the III-N material structure 40 in a region outside the active region of the device (i.e., the active region being the region between the first and second power electrodes 18 A and 18B) and exposing a surface of the conductive substrate. A portion of metal layer 516 is formed inside the TEVs and electrically connects the first gate electrode 16 to the substrate. Similarly, metal layer 517 is at least partially formed inside ta portion of the TEVs and electrically connects the second gate electrode 17 to the substrate. Next, the portion 512 of the substrate can be removed (e.g., by dry or wet etching) to electrically isolate the first substrate portion 511 A and the second substate portion 51 IB. [0074] Figure 5B shows a top-side plan view of switch 500. Cross-section B-BB (indicated by the dotted line) shows an example cross-section location depicted in Figure 5A. As seen in Figure 5B, there are no external gate pads located on the top-side of the device, such as gate pads 16A/16B and 17A/17B as shown in Figure 3B or 3C. Eliminating the need for top-side gate pads can greatly reduce the complexity of mounting switch 500 into an electronic component package, as further shown in Figures 5C and 5D.

[0075] Figures 5C and 5D show a plan view and cross-sectional view, respectively, of an electronic component package 502 which includes the FQS III-N switch 500 of Figure 5A. Electronic component package 502 is similar to the electronic component package 304 of Figure 3D, with the following differences. Package 502 includes a direct bonded copper (DBC) substrate 510 (best seen in Figure 5D), which can be a base substrate for the package. The DBC substrate 510 includes an insulating (e.g., ceramic or AIN) substrate 315, on which a top metal layer (e.g., copper or nickel) is patterned into at least a first portion that functions as a first power plate 511, a second portion that functions a second power plate 513. Portions 511 and 513 are electrically isolated from one another by a trench 514 formed through the top metal layer. The second substrate portion 51 IB of the ni-N FQS III-N switch 500 is electrically connected and physically mounted to the first power plate 511. The first substrate portion 511A of the III-N FQS III-N switch 500 is electrically connected and physically mounted to the second power plate 513. Abackmetal layer 25 (not shown in Figure 5D for simplicity) is attached to the first and second power plates 511/513 using solder, epoxy or another appropriate adhesive material.

[0076] As seen in Figure 5D, the first gate electrode 16 is electrically connected to the second power plate 513 through the first substrate portion 511 A and the second gate electrode 17 is electrically connected to the first power plate 511 through the second substrate portion 51 IB, thereby eliminating the need for the external gate wirebonds 42A/B and 45A/B as shown in the package 304 of Figure 3D. This reduces the switching inductance of the package 504 and reduces assembly costs associated with component package complexity. [0077] Figures 6A and 6B show a cross-sectional view and a plan view of an enhancement-mode III-N FQS switch 600 which can be used in the circuit of Figure 1. FQS switch 600 includes an insulating substrate 411 (e.g., a sapphire substrate) which can be similar to the substrate 411 described in switch 400 of Figure 4A. Switch 600 further includes a III-N buffer layer 612 formed over the substrate 411. AIII-N channel layer 613 and a III-N barrier layer 614 are formed over the III-N buffer layer 612 and a compositional difference between the barrier layer 614 and the channel layer 613 cause a 2DEG channel 19 to be formed therein. The III-N buffer layer 612, the III-N channel layer 613 and the III-N barrier layer 614 form a III-N material stack 640. An insulating layer 615 is formed over the III-N material stack 640. Afirst power electrode 618 and a second power electrode 620 are electrically connected to the 2DEG channel 19. Afirst gate electrode 616 and a second gate electrode 617 are used to modulate the charge in the 2DEG channel 19. The first gate electrode 616 and the second gate electrode 617 are configured such that the III-N switch 600 is an enhancement-mode device, that is, that the 2DEG channel 19 is discontinuous between the first power electrode 618 and the second power electrode 620 when first gate electrode 616 is biased at 0V relevant to the first power electrode and/or the second gate electrode 617 is biased at 0V relevant to the second power electrode 620. The first and/or second gate electrodes 616 and 617 can be partially or fully recessed into the III-N barrier layer 614. A gate dielectric layer (not shown), such as oxide or nitride layer, can be formed between the gate electrodes and the III-N material structure layers. The gate electrodes 616 and 617 are separated by a distance 42 in order to ensure high-voltage operation of switch 600. Enhancement-mode operation of the III-N FQS switch can be accomplished by any number of appropriate methods already known in the art and related to enhancement-mode III-N transistors which are not explicitly described herein (e.g., using a vertical gate module as described in US. Patent No.: 10,756,207).

[0078] As seen in Figure 6A, a backmetal layer is formed on a side of the insulating substrate 411 opposite the III-N material structure. The portion 625 of the backmetal layer is etch away leaving a first backmetal portion 25 A and a second backmetal portion 25B. A Through- Substrate Via (TSV) 626 and TSV 627 are formed through the III-N material structure 640 and the insulating substrate 411. A portion of a metal routing layer 628 is formed in the TSV 626 and electrically connects the first power electrode 618 to the first backmetal portion 25 A. A metal routing layer 629 is at least partially formed in the TSV 627 and electrically connects the second power electrode 620 to the second backmetal portion 25B.

[0079] Figure 6B is a top-down plan view the enhancements-mode (E-mode) FQS switch 600. As seen in Figure 3B, cross-section C-CC (represented by the dotted line) shows an example location of a device cross-section which corresponds to the cross- sectional view shown in Figure 6A. The first gate electrode 616 of E-mode III-N switch 600 includes a first gate pad 616A and (optionally) a second gate pad 617A, which can be used to wire-bond external connecting wires a component package terminal.

[0080] Figure 6C and 6D show a plan view and cross-sectional view, respectively, of an electronic component package 604 which includes the enhancement-mode FQS III- N switch 600 of Figure 6A. Electronic component package 604 is similar to the electronic component package 504 of Figure 5C. Package 604 includes a package case 608. Package 604 includes the DBC substrate 510, as described in package 504, which can be used to physically mount the DBC to the conductive structural package base (i.e., the lead frame 323) using solder or other methods. The second backmetal portion 25B of the III-N FQS switch 600 is electrically connected and physically mounted to the first power plate 511. The first backmetal portion 25A of the III-N FQS switch 600 is electrically connected and physically mounted to the second power plate 513. The backmetal layers is attached to the first and second power plates 511/513 using solder, epoxy or another appropriate adhesive material. As seen in Figure 6C, the package complexity and component count can be reduced compared to the electronic component package 304 shown in Figure 3D.

[0081] Figure 7 is a plan view of an electronic component package 700 which includes a III-N FQS switch, such as switch 300 described in Figures 3A and 3B. Package 700 further includes a package case 702 which can be formed of a molding compound. Component package 700 further includes a direct bonded copper (DBC) substrate 710, which can be similar to DBC substrate 310 described in Figure 3D. The DBC substrate 710 includes an insulating (e.g., ceramic or AIN) substrate on which a top metal layer is patterned into several portions that functions as metal routing layers. The top metal layer portions include at least portions one through seven, each number sequentially labeled as 711-717. Portions 711-717 are each electrically isolated from one another by a trench formed through the top metal layer. The DBC substrate 710 is physically mounted to a structural package base 704 which can be formed out of a conductive material such as Copper or Nickel (i.e., the lead frame) using solder or other methods. A heat sink (not shown) can be mounted and thermally connected to the reverse side of the package base 704. The substrate of the III-N FQS III-N device 300 is attached to the first portion 711 of the top metal layer using solder, epoxy or another appropriate adhesive material.

[0082] Electronic component package 700 in Figure 7 shows a “TO-Type” package (e.g., TO-220, TO-247, TO-263, etc). The package base 704 can include a thru- hole 705 formed through the package base which can be used to mount the electronic component with a screw. Component package 700 further includes a first power terminal 727 and a second power terminal 723. Component package 700 includes a first gate terminal 726 and a second gate terminal 725. The first and second power terminals 727 and 723 can switch between source terminals and drain terminals depending on the polarity of the FQS switch 300 during operation. The TO-type package shown in Figure 7 has four terminal leads extending from the package, however, the package type could include more leads as required, for example, to include kelvin connection terminals. The substrate of device 300 and the first portion 711 are electrically isolated from all four terminal leads. Therefore, the substrate of device 300 is left at a floating potential compared to the first and/or second power terminals 727 and 723.

[0083] The second gate electrode 32 of switch 300 is connected to the second top metal layer portion 712 with wirebond 61. The third top metal portion 713 is electrically connected to the first gate terminal 726 with wirebond 65. A ferrite bead 720 is formed between the second portion 712 and the third portion 713, such that the ferrite bead 720 is electrically connected between the gate electrode 32 of switch 300 and the first gate terminal 726 of the component 700. A ferrite bead is a passive electric component and typically is a hollow bead or cylinder made of ferrite, a semi-magnetic substance made from iron oxide alloyed with other metals. A ferrite bead can be used to suppress noise from electromagnetic interference (EMI) in a circuit. The first gate electrode 22 of switch 300 is connected to the fifth top metal portion 715 with wirebond 71. The sixth top metal portion 716 is electrically connected to the second gate terminal 725 with wirebond 75. A ferrite bead 721 (which can be similar to ferrite bead 720) is formed between the fifth portion 715 and the sixth portion 716, such that the ferrite bead 721 is electrically connected between the gate electrode 22 of switch 300 and the second gate terminal 725 of the component 700. The ferrite beads 720 and 721 can be selected to form a passive low pass filter configured to reduce oscillations having frequencies above about 100 MHz or 300MHz and to pass switching frequencies, e.g., in the tens or hundreds of kHz or the 1 MHz range. Alternatively, the ferrite beads 720 and 721 can be a hybrid type device which include a resistive component and a capacitive component. This can lead to improved switching performance, which would otherwise be degraded due to intrinsic inductances of the connecting wires.

[0084] The first and second gate pads 16A and 16B of switch 300 are electrically connected to the seventh top metal portion 717 with wirebonds 72 and 74, respectively. The third and fourth gate pads 17A and 17B of switch 300 are electrically connected to the fourth top metal portion 714 with wirebonds 62 and 64, respectively. The second source electrode 33 of switch 300 is electrically connected to the fourth top metal portion 714 with wirebond 63 and the fourth top metal portion 714 is electrically connected to the first power electrode 727 with wirebonds 66. The first source electrode 22 of switch 300 is electrically connected to the seventh top metal portion 717 and the seventh top metal portion 717 is electrically connected to the second power terminal 723 with wirebonds 76. As seen in Figure 7, the fourth and seventh portions 714 and 717 can be formed along two adjacent sides of switch 300 to allow for improved wirebond connections. When FQS switch 300 is configured as described above in the electronic component 700, package complexity can be reduced and device efficiency can be improved.

[0085] Figure 8A is a circuit schematic of hybrid III-N FQS switch 800 which incorporates a cascode common-source topology. FQS switch 800 includes a first cascode hybrid III-N device 801 and a second cascode hybrid III-N device 804 (indicated in the dashed areas). The first cascode hybrid III-N device 801 includes a first high- voltage depletion-mode III-N HEMT device 802 in a cascode configuration with a first low-voltage enhancement-mode device 803, where the source of device 802 is electrically connected to the drain of device 803. The second cascode hybrid III-N device 804 includes a second high-voltage depletion-mode III-N HEMT device 805 in a cascode configuration with a second low-voltage enhancement-mode device 808, where the source of device 805 is electrically connected to the drain of device 808. The drain of the first III-N device 802 is connected to a first power terminal Tl, and the drain of the second III-N device 805 is connected to a second power terminal T2. The gate of the first enhancement-mode device 803 is connected to a first gate terminal Gl, and the gate of the second enhancement-mode device 808 is connected to a second gate terminal G2. [0086] The source of the first enhancement-mode device 803 and the source of the second enhancement-mode device 808 are both electrically connected to a commonsource terminal CS. Furthermore, the gate of the first III-N device 802 and the gate of the second III-N device 804 are both electrically connected to the common-source terminal CS. In this configuration, the source of both the enhancement-mode transistors can be connected to a shared terminal. Furthermore, the first III-N device 802 and the second III-N device 804 can be formed on a common substrate using shared III-N material structure layers. This allows for reduced complexity when integrating the components of FQS switch 800 into a common package. Further details of the integration will be described.

[0087] Figures 8B and 8C show a plan view and a cross-sectional view, respectively, of an electronic component package 810 which includes a hybrid III-N FQS switch, which can be similar to the switch 800 schematically shown in Figure 8A, which is formed using a common-source topology. Component 810 further includes a package lead frame 814, which can be conductive structural package base, and serve as the common-source (CS) terminal. Component 810 includes an integrated III-N device 812. III-N device 812 includes a first depletion-mode III-N device 802 and a second III-N depletion-mode III-N device 805 (separated by dashed line 813 in Figure 8B), where the first device 802 and the second device 805 are formed on a common substrate and share III-N material structure layers within the integrated III-N device 812. The component 810 further includes a first enhancement-mode device 803, where the drain of device 803 is physically mounted and electrically connected to the drain 815 of the first depletionmode III-N device 802, and a second enhancement-mode device 808, where the drain of device 808 is physically mounted and electrically connected to the drain 816 of the second depletion-mode III-N device 805.

[0088] The hybrid III-N bidirectional switch is configured in the electronic component 810 as follows: the drain of first III-N device 802 is electrically connected to the first terminal T1 with one (not shown) or multiple wirebonds 821. The drain of the second III-N device 805 is electrically connected to the second terminal T2 with one (not shown) or multiple wirebonds 822. The gate of the first enhancement-mode device 803 is connected to the first gate terminal G1 using wirebond 823. The gate of the second enhancement-mode device 808 is connected to the second gate terminal G2 using wire bond 824. The source 817 of the first enhancement-mode device 803 is connected to the CS terminal 814 with wirebond 825, and the source 818 of the second enhancementmode device 808 is connected to the CS terminal 814 with wirebond 826. Although wirebond have been described above, the electronic component can also be configured using metal clips, metal ribbons or other appropriate methods.

[0089] The gate of the first III-N device 802 is electrically connected to the CS terminal 814 using a Through-Epi-Via (TEV) 831 and the gate of the second III-N device 805 is electrically connected to the CS terminal 814 using a TEV 832. The TEVs 831 and 832 are formed in a similar manner as the TEVs 516 and 517 shown in Figure 5A. [0090] Figures 9A and 9B shows a plan view and a cross-sectional view, respectively, of an electronic component 900, which includes a hybrid III-N bidirectional switch, which is similar to the electronic component 810 described in Figure 8A. However, component 900 differs from component 810 in that component 900 is configured using an integrated low-voltage enhancement mode device 910 (e.g., a dual integrated Si-FET). The integrated device 910 combines the functionality of the first and second enhancement-mode devices 803 and 808 of component 810 into a single integrated silicon device formed on a common substrate.

[0091] Figure 9C shows a detailed cross-section of the integrated enhancementmode device 910. As seen in Figure 9C, device 910 includes a semiconductor body 911 (e.g., silicon) and a common source electrode or pad 930 formed on a first side of the semiconductor body 911, which can function as the common-source of the first and second enhancement-mode devices integrated into device 910. Device 910 includes a first gate 921 which can be configured to be connected to the first gate terminal G1 of component 900, and a second gate 923 which can be configured to be connected to the second gate terminal G2 of component 900, also formed on the first side of the semiconductor body. Integrated device 910 includes a first drain 925 which is connected to a first drain pad 925a on second side of the semiconductor body 911 (where the second side is opposite the first side) using a first through substrate via (TSV) 931. Device 910 further includes a second drain 926 which is connected to a second drain pad 926a on the second side of the semiconductor body 911 using a second TSV 932. The first drain pad 925a and the second drain pad 926a are electrically isolated from one another.

[0092] The integrated low-voltage enhancement-mode device 910 can be fabricated using methods and material structures which are similar to those used to form a LDMOS Si-FET transistor. The device 910 can be a lateral device, that is to say, the drain, gate, and source of the device 910 are all formed on the same side of the semiconductor body 911, and then, subsequently, the drain electrodes are formed on the reverse side of the semiconductor body 911 using vias formed through the substrate of device 910 to allow for an electrical drain connection to external circuitry on a side opposite of the source and gate connections.

[0093] Referring back to Figure 9B, the integrated enhancement-mode device 910 is mounted and physically attached to the hybrid III-N device 812. The first drain pad 925a of device 910 is electrically connected and physically attached to the first source 815 of III-N device 812. The second drain pad 926a of device 910 is electrically connected and physically attached to the second source 816 of the III-N device 812.

[0094] Referring to Figure 9A, the first gate 921 of integrated device 910 is electrically connected to the first gate terminal G1 using wirebond 823, and the second gate 923 of integrated device 910 is electrically connected to the second gate terminal G2 using wirebond 824. The common source pad 930 of integrated device 910 is electrically connected to the common-source (CS) terminal 814 using wirebond 935. Using the integrated enhancement-mode device 910 in the electronic component 900 can reduce package complexity and improve switching performance compared to the electronic component 810 of Figure 8B which uses two discrete enhancement-mode devices 803 and 808. [0095] Figure 10A is a circuit schematic of a hybrid integrated III-N bidirectional switch 1000. FQS switch 1000 includes the hybrid III-N FQS similar to switch 800 of Figure 8 A, which incorporates a cascode common-source topology. The switch 1000 further includes a first gate driver 1002 and a second gate driver 1004. The first gate driver 1002 is used to drive the gate of enhancement-mode device 803 and the second gate driver 1004 is used to drive the gate of enhancement-mode device 808. The components of the first and second gate drivers 1002/1004 (shown in the dashed areas) as well as the first and second enhancement-mode devices 803/808 can be integrated into a single silicon IC, as further shown in Figure 10B.

[0096] Figure 10B shows a plan view of an electronic component 1010 which forms a hybrid integrated III-N FQS switch. Component 101 includes a silicon IC 1020 which includes the first gate driver 1002, the second gate driver 1004, the first enhancement-mode device 803, and the second enhancement-mode device 808 shown in Figure 10A all integrated into a single discrete silicon semiconductor component. Electronic component also includes the III-N device 812, where the silicon IC 1020 is mounted and physically attached to the III-N device 812.

[0097] The gate controller input 961 of the first gate driver 1004 is connected to the G1 logic input 970 using wirebond 946, and the gate controller input 963 of the second gate driver 1006 is connected to the G2 logic input 971 using wirebond 947. The voltage input VDD 940 can be connected to a single or multiple VDD input terminals. For example, Figure 10B shows a first VDD input terminal 942a connected to the voltage input VDD 940 using wirebond 941a and a second VDD input terminal 942b connected to the voltage input VDD 940 using wirebond 941b. The silicon IC 1020 includes a common-source pad 960 which is electrically connected to the common-source CS terminal 814 using wirebond 965. The common-source pad 960 of IC 1020 is electrically connected to the source of the first enhancement-mode device 803, the source of the second enhancement-mode device 804, and the ground connections of the first and second gate drivers 1002 and 1004 (as shown on the circuit schematic 1000 in Figure 10A).

[0098] Using the silicon IC 1020 of Figure 10B to integrate the driving components of the hybrid III-N FQS switch of electronic component 1010 can reduce circuit complexity and improve switching performance compared to alternative configurations previously described.

[0099] A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the techniques and devices described herein. Accordingly, other implementations are within the scope of the following claim.

Claims

WHAT IS CLAIMED IS:

1. An electronic component, comprising: a four-quadrant switch (FQS) that is a depletion-mode III-N device comprising a first power electrode, a second power electrode, a first gate, and a second gate, wherein the FQS comprises a III-N material structure and a compositional difference in the III-N material structure forms a 2DEG channel therein; a first internal resistor formed of a first portion of the 2DEG channel, wherein a first terminal of the first internal resistor is connected to the first gate of the III-N device; a second internal resistor formed of a second portion of the 2DEG channel, wherein a first terminal of the second internal resistor is connected to the second gate of the III-N device; a first enhancement-mode transistor that has a first drain electrically connected and physically mounted to the first power electrode, wherein a second terminal of the first internal resistor is electrically connected to the first drain of the first enhancementmode transistor; and a second enhancement-mode transistor that has a second drain electrically connected and physically mounted to the second power electrode, wherein a second terminal of the second internal resistor is electrically connected to the second drain of the second enhancement-mode transistor.

2. The electronic component of claim 1, wherein the first internal resistor and the second internal resistor have a resistance between IMohm-lOOMohm.

3. The electronic component of claim 2, wherein the wherein the resistance of the first internal resistor and the second internal resistor are formed using a portion of the 2DEG channel charge.

4. The electronic component of claim 1, further comprising an electronic package with a first terminal, a second terminal, a third terminal and a fourth terminal; and a first gate of the first enhancement-mode transistor is electrically connected to the first terminal, a first source of the first enhancement-mode transistor and the first gate of the depletion-mode III-N device are electrically connected to the second terminal, a second source of the second enhancement-mode transistor and the second gate of the depletion-mode III-N device are electrically connected to the third terminal, and a second gate of the second enhancement-mode transistor is electrically connected to the fourth terminal.

5. The electronic component of claim 4, wherein the electronic package is a TO-type package.

6. The electronic component of claim 4, wherein a first ferrite bead is connected between the first gate of the first enhancement-mode transistor and the first terminal, and a second ferrite bead is connected between the second gate of the second enhancementmode transistor and the fourth terminal.

7. The electronic component of claim 6, wherein the first ferrite bead and the second ferrite bead form a low pass filter configured to reduce oscillations having frequencies above 100 MHz.

8. An electronic package, comprising: a first terminal, a second terminal, a third terminal, a fourth terminal, and a structural package base; a hybrid enhancement-mode four-quadrant switch that comprises a III-N depletion-mode device that comprises a substrate, a first power electrode, a second power electrode, a first gate, a second gate and a III-N material structure, wherein the depletion-mode III-N device wherein a compositional difference in the III-N material structures forms a 2DEG channel therein, a first enhancement-mode transistor that comprises a first drain, a first source, and a third gate, wherein the first drain of the first enhancement-mode transistor is electrically connected and physically mounted to the first power electrode, and a second enhancement-mode transistor that comprises a second drain, a second source, and a fourth gate, wherein the second drain of the second enhancementmode transistor is electrically connected and physically mounted to the second power electrode; an insulating shim that comprises an insulating layer, first metal layer and a second metal layer on a side of the insulating layer opposite the first metal layer, and the second metal layer is physically mounted to the structural package base, wherein the first metal layer comprises at least five portions each electrically isolated from the other by a trench formed through the metal layer, the substrate of the III-N depletion-mode device is attached to the first portion of the first metal layer, the third gate of the first enhancement-mode transistor is electrically connected to the second portion of the first metal layer, the third portion of the first metal layer is electrically connected to the first terminal of the electronic package, the fourth gate of the second enhancement-mode transistor is electrically connected to the fourth portion of the first metal layer, and the fifth portion of the first metal layer is electrically connected to the second terminal; a first ferrite bead connected between the second portion and the third portion of the first metal layer; and a second ferrite bead connected between the fourth portion and the fifth portion of the first metal layer.

9. The electronic package of claim 8, wherein the first gate of the depletion-mode III-N device and the first source of the first enhancement-mode device are electrically connected to the third terminal of the electronic package.

10. The electronic package of claim 9, wherein the second gate of the depletion-mode III-N device and the second source of the second enhancement-mode device are electrically connected to the fourth terminal of the electronic package.

11. The electronic package of claim 10, wherein the first ferrite bead and the second ferrite bead form a low pass filter configured to reduce oscillations having frequencies above 100 MHz.

12. The electronic package of claim 8, wherein the substrate of the depletion-mode device and the first portion of the first metal layer are electrically isolated from the first, second, third, and fourth terminals of the electronic package.

13. The electronic package of claim 12, wherein the substrate of the depletion-mode device is maintained at a floating potential.

14. An electronic circuit, comprising: a high-voltage node, a ground node, a first resistor, and a second resistor; a four-quadrant switch (FQS) that is a depletion-mode III-N device comprising a first power electrode, a second power electrode, a first gate, and a second gate; a first enhancement-mode transistor comprising a first drain, a first source, and a third gate, wherein the first drain of the first enhancement-mode transistor is electrically connected first power electrode, and the first gate of the depletion-mode III-N device and the first source of the first enhancement-mode transistor are electrically connected to the high-voltage node; and a second enhancement-mode transistor comprising a second drain, a second source and a fourth gate, wherein the second drain of the second enhancement-mode transistor is electrically connected to the second power electrode, and the second gate of the depletion-mode III-N device and the second source of the second enhancement-mode transistor are electrically connected to the ground node; wherein a first terminal of the first resistor is connected to the first gate of the III- N device, and a second terminal of the first internal resistor is electrically connected to the first drain of the first enhancement-mode transistor; and wherein a first terminal of the second resistor is connected to the second gate of the III-N device, and a second terminal of the second resistor is electrically connected to the second drain of the second enhancement-mode transistor.

15. The electronic circuit of claim 14, further comprising a first ferrite bead connected between the first gate of the depletion-mode transistor and the high-voltage node, and a second ferrite bead connected between the second gate of the depletion-mode transistor and the ground node.

16. The electronic circuit of claim 15, wherein the high-voltage node can be greater than 600V

17. The electronic circuit of claim 16, wherein when the first gate is biased below a first threshold voltage and the second gate is biased above a second threshold voltage, substantial current flows through a channel of the depletion-mode III-N device in a first direction.

18. The electronic circuit of claim 17, wherein when the first gate is biased above the first threshold voltage and the second gate is biased below the second threshold voltage, substantial current flows through the channel of the depletion-mode III-N device in a second direction.

19. The electronic circuit of claim 18, wherein when the first gate is biased below the first threshold voltage and the second gate is biased below the second threshold voltage, substantial current is blocked through the channel of the depletion-mode III-N device in both the first and second directions.

20. The electronic circuit of claim 19, wherein the depletion-mode III-N device is an

AlGaN/GaN HEMT.