CN110391212A - 半导体装置以及其制造方法 - Google Patents
半导体装置以及其制造方法 Download PDFInfo
- Publication number
- CN110391212A CN110391212A CN201910292912.3A CN201910292912A CN110391212A CN 110391212 A CN110391212 A CN 110391212A CN 201910292912 A CN201910292912 A CN 201910292912A CN 110391212 A CN110391212 A CN 110391212A
- Authority
- CN
- China
- Prior art keywords
- metal film
- barrier metal
- interlayer dielectric
- semiconductor device
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 112
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 153
- 239000002184 metal Substances 0.000 claims abstract description 153
- 230000004888 barrier function Effects 0.000 claims abstract description 89
- 239000011229 interlayer Substances 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000000926 separation method Methods 0.000 claims abstract description 23
- 239000010410 layer Substances 0.000 claims description 66
- 238000000034 method Methods 0.000 claims description 63
- 239000000463 material Substances 0.000 claims description 7
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 6
- 230000000903 blocking effect Effects 0.000 claims description 3
- 239000004744 fabric Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 238000007689 inspection Methods 0.000 description 9
- 238000010276 construction Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000003252 repetitive effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000017260 vegetative to reproductive phase transition of meristem Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/57—Protection from inspection, reverse engineering or tampering
- H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66045—Field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明涉及半导体装置以及其制造方法。半导体装置具备:栅极绝缘膜,被设置在半导体基板上;栅极电极,被设置在栅极绝缘膜上;源极・漏极区域,以与栅极电极相邻的方式被设置于半导体基板;元件分离区域,被设置为包围栅极电极和源极・漏极区域;保护环,以包围元件分离区域的方式被设置于半导体基板;层间绝缘膜,被设置为覆盖栅极电极、源极・漏极区域、元件分离区域和保护环;线状的接触槽,以包围元件分离区域并且露出保护环的表面的方式被设置于层间绝缘膜;能够遮蔽X射线的阻挡金属膜,被设置为覆盖接触槽的内侧面和底面;以及金属膜,经由阻挡金属膜与保护环电连接。
Description
技术领域
本发明涉及半导体装置以及其制造方法。
背景技术
在半导体装置的检査工序中,为了进行将半导体装置内部特别是封装内部的引线框与半导体芯片结线的接合线的断线检査、或树脂封装内部的空隙检査、半导体装置与安装基板的安装状态的检査,广泛地使用X射线照射的手法来作为非破坏检査。
可是,已知当向在半导体装置内的半导体基板上设置的栅极绝缘膜照射大量的X射线时半导体装置的电特性持久地进行变动。作为向该问题的对策,在专利文献1中,在半导体装置的最上保护层之上新设置金属层,利用该金属层来作为X射线遮蔽膜。
现有技术文献
专利文献
专利文献1:日本特开平7-169804号公报。
发明要解决的课题
然而,近年来,使用从与半导体基板平行的方向照射X射线的检査装置的情况变多,在专利文献1的构造中,遮蔽这样的来自与半导体基板平行的方向的X射线是困难的。
发明内容
因此,本发明的目的在于提供即使在利用X射线的检査中从与半导体基板平行的方向即半导体基板的侧面侧照射X射线的情况下也能够遮蔽X射线来防止向栅极绝缘膜照射X射线的、半导体装置以及其制造方法。
用于解决课题的方案
本发明的一个方式的半导体装置的特征在于,具备:栅极绝缘膜,被设置在半导体基板上;栅极电极,被设置在所述栅极绝缘膜上;源极・漏极区域,以与所述栅极电极相邻的方式被设置于所述半导体基板;元件分离区域,被设置为包围所述栅极电极和所述源极・漏极区域;保护环,以包围所述元件分离区域的方式被设置于所述半导体基板;层间绝缘膜,被设置为覆盖所述栅极电极、所述源极・漏极区域、所述元件分离区域和所述保护环;线状的接触槽,以包围所述元件分离区域并且露出所述保护环的表面的方式被设置于所述层间绝缘膜;能够遮蔽X射线的阻挡金属膜,被设置为覆盖所述接触槽的内侧面和底面;以及金属膜,包括经由所述阻挡金属膜埋入到所述接触槽内的插塞部、和与所述插塞部连接且在所述层间绝缘膜上设置的布线部,并且,与所述保护环电连接。
本发明的半导体装置的制造方法的特征在于,具备:在半导体基板上形成栅极绝缘膜的工序;在所述栅极绝缘膜上形成栅极电极的工序;以与所述栅极电极相邻的方式在半导体基板形成源极・漏极区域的工序;以将形成有所述栅极电极和所述源极・漏极区域的区域包围的方式形成元件分离区域的工序;以包围所述元件分离区域的方式在所述半导体基板形成保护环的工序;以将所述栅极电极、所述源极・漏极区域、所述元件分离区域和所述保护环覆盖的方式形成层间绝缘膜的工序;以包围所述元件分离区域并且露出所述保护环的表面的方式在所述层间绝缘膜形成线状的接触槽的工序;以将所述接触槽的内侧面和底面覆盖的方式形成能够遮蔽X射线的阻挡金属膜的工序;以及形成金属膜的工序,所述金属膜包括经由所述阻挡金属膜埋入到所述接触槽内的插塞部、和与所述插塞部连接且在所述层间绝缘膜上形成的布线部,并且,与所述保护环电连接。
发明效果
根据本发明,为了形成与在半导体基板设置的保护环电连接的金属膜而设置在层间绝缘膜设置的线状的接触槽,以覆盖该接触槽的内侧面的方式形成了能够遮蔽X射线的阻挡金属膜,因此,在利用X射线的检査中从半导体基板的侧面侧照射X射线的情况下,能够防止X射线被照射到栅极绝缘膜。
附图说明
图1是示出本发明的实施方式的半导体装置的构造的平面图。
图2是示出本发明的实施方式的半导体装置的构造的剖面图。
图3是示出图1和图2所示的半导体装置的制造方法的工序剖面图。
图4是示出图1和图2所示的半导体装置的制造方法的工序剖面图。
图5是示出图1和图2所示的半导体装置的制造方法的工序剖面图。
图6是示出图1和图2所示的半导体装置的制造方法的工序剖面图。
图7是示出图1和图2所示的半导体装置的制造方法的工序剖面图。
图8是示出图1和图2所示的半导体装置的制造方法的工序剖面图。
图9是示出图1和图2所示的半导体装置的制造方法的工序剖面图。
图10是示出根据本发明的实施方式的第一变形例的半导体装置的构造的剖面图。
图11是示出图10所示的半导体装置的制造方法的工序剖面图。
图12是示出图10所示的半导体装置的制造方法的工序剖面图。
图13是示出图10所示的半导体装置的制造方法的工序剖面图。
图14是示出根据本发明的实施方式的第二变形例的半导体装置的构造的剖面图。
图15是示出图14所示的半导体装置的制造方法的工序剖面图。
图16是示出图14所示的半导体装置的制造方法的工序剖面图。
图17是示出图14所示的半导体装置的制造方法的工序剖面图。
图18是示出图14所示的半导体装置的制造方法的工序剖面图。
图19是示出图14所示的半导体装置的制造方法的工序剖面图。
具体实施方式
以下,一边参照附图一边对用于实施本发明的方式详细地进行说明。
图1是用于说明本发明的实施方式的半导体装置100的构造的概略平面图,图2是沿着图1所示的A-A’线的剖面图。
如图1和图2所示那样,本实施方式的半导体装置100具备:半导体基板101;在半导体基板101设置的P型的阱(well)102;以环绕半导体基板101的元件形成区域的方式设置的元件分离区域103;在元件形成区域中在半导体基板101上设置的栅极绝缘膜104;在栅极绝缘膜104上设置的栅极电极105;与栅极电极105相邻地设置于半导体基板101的、由N型扩散层构成的源极・漏极区域106;以包围元件分离区域103的方式设置于半导体基板101的、由P型扩散层构成的保护环(guard ring)107;以将栅极电极105、源极・漏极区域106、元件分离区域103和保护环107覆盖的方式设置的层间绝缘膜108;以包围元件分离区域103并且露出保护环107的表面的方式设置于层间绝缘膜108的、线状的接触槽(contact trench)110t;以将接触槽110t的内侧面和底面覆盖的方式设置的、能够遮蔽X射线的阻挡金属膜(barrier metal film)110;以及包括经由阻挡金属膜110埋入到接触槽110t内的插塞(plug)部111p和与插塞部111p连接且在层间绝缘膜108上设置的布线部111w并且与保护环107电连接的、金属膜111。在此,为了向阱102供给电位而设置有保护环107。
在层间绝缘膜108设置有将源极・漏极区域106的表面露出的接触孔109h,在该接触孔109h内埋入接触插塞109。
半导体装置100还具备:在层间绝缘膜108上在平面视中至少与栅极绝缘膜104重叠的区域中设置的、能够遮蔽X射线的阻挡金属膜112;在接触插塞109上设置的阻挡金属膜114;以及分别设置在阻挡金属膜112和114上并且构成与布线部111w相同的金属布线层的一部分的布线部113和115。阻挡金属膜110、112和114均由能够遮蔽X射线的相同的材料构成,在本实施方式中,由包括钛钨的膜形成。
根据如以上那样构成的半导体装置100,对于将保护环107与布线部111w电连接的部分,做成在层间绝缘膜108设置线状的接触槽110t、以覆盖接触槽110t的内侧面的方式设置能够遮蔽X射线的阻挡金属膜110、经由阻挡金属膜110形成插塞部111p后的结构。因此,能够在利用X射线的检査中遮蔽来自与半导体基板101平行的方向即侧面方向的X射线来防止向栅极绝缘膜104照射X射线。
此外,在本实施方式中,在层间绝缘膜108上的、在平面视中与栅极绝缘膜104重叠的区域中设置了能够遮蔽X射线的阻挡金属膜112,由此,即使在使用了从半导体基板101的上表面方向照射X射线的检査装置的情况下,也能够防止X射线被照射到栅极绝缘膜104。
接着,使用图3至9所示的工序剖面图来对图1和图2所示的半导体装置100的制造方法进行说明。
首先,如图3所示那样,在半导体基板101以环绕元件形成区域的方式通过例如LOCOS法形成元件分离区域103。接着,向半导体基板101导入P型的杂质,形成P型的阱102。接着,在半导体基板101上依次形成绝缘膜和多晶硅膜之后,利用光刻和蚀刻来对该绝缘膜和多晶硅膜的层叠膜进行图案化,由此,在元件形成区域中的半导体基板101上形成栅极绝缘膜104和栅极电极105。接着,将栅极电极105作为掩模来将N型的杂质离子注入,由此,在半导体基板101形成源极・漏极区域106。之后,将覆盖由元件分离区域103包围后的元件形成区域的抗蚀图案(resist pattern)(未图示)作为掩模来将P型的杂质离子注入,由此,在半导体基板101形成P型的保护环107。
接着,如图4所示那样,以将栅极电极105、源极・漏极区域106、元件分离区域103和保护环107覆盖的方式在整个表面形成层间绝缘膜108。
接着,如图5所示那样,在层间绝缘膜108上在平面视中与源极・漏极区域106重叠的区域中形成具有开口的抗蚀图案121,将该抗蚀图案121作为掩模来对层间绝缘膜108进行蚀刻,由此,形成将源极・漏极区域106的表面露出的接触孔109h。
在除去抗蚀图案121之后,在接触孔109h内和层间绝缘膜108上形成导电膜,利用回蚀刻(etch back)除去层间绝缘膜108上的导电膜而仅在接触孔109h内残存导电膜,由此,如图6所示那样形成埋入到接触孔109h的接触插塞109。
接着,如图7所示那样,在平面视中与保护环107重叠的区域中形成具有开口的抗蚀图案122,将该抗蚀图案122作为掩模来对层间绝缘膜108进行蚀刻,由此,形成将保护环107的表面露出的接触槽110t。
在除去抗蚀图案122之后,如图8所示那样,以将接触槽110t的内侧面和底面以及层间绝缘膜108的上表面覆盖的方式形成包括能够遮蔽X射线的材料即钛钨的、阻挡金属层123。
接下来,如图9所示那样,经由阻挡金属层123在接触槽110t内和层间绝缘膜108上形成金属层124。接着,在金属层124上形成将在平面视中与接触槽110t、接触孔109h和栅极绝缘膜104各个重叠的区域选择性地覆盖的抗蚀图案125。
之后,将抗蚀图案125作为掩模来利用蚀刻对金属层124和阻挡金属层123进行图案化,由此,同时形成图2所示的阻挡金属膜110、112和114、以及由插塞部111p及布线部111w构成的金属膜111、布线部113和布线部115。
如以上那样做,形成了图1和图2所示的半导体装置100。
像这样,根据本实施方式的半导体装置100的制造方法,具有以下这样的优点:能够在同一工序中同时形成用于将来自半导体基板101的侧面方向的X射线遮蔽的阻挡金属膜110、以及用于将来自半导体基板101的上表面方向的X射线遮蔽的阻挡金属膜112。
图10是用于说明根据本发明的实施方式的第一变形例的半导体装置200的构造的剖面图。再有,对与图1和图2所示的半导体装置100相同的结构要素标注同一附图标记,适当省略重复的说明。
在第一变形例的半导体装置200中,层间绝缘膜108的将源极・漏极区域106露出的接触孔209h的开口面积比图2所示的半导体装置100中的接触孔109h大,以将接触孔209h的内侧面和底面覆盖的方式设置了能够遮蔽X射线的阻挡金属膜214。在接触孔209h内经由阻挡金属膜214埋入插塞部215p,进而,在层间绝缘膜108上设置与插塞部215p连接的布线部215w,通过插塞部215p和布线部215w构成了金属膜215。布线部215w构成了与布线部111w和113相同的金属布线层的一部分。
接着,使用图11至13所示的工序剖面图来对图10所示的半导体装置200的制造方法进行说明。
半导体装置200的制造方法在形成图4所示的层间绝缘膜108的工序之前与半导体装置100的制造方法同样。
在图4的工序之后,如图11所示那样,在层间绝缘膜108上在平面视中与源极・漏极区域106和保护环107重叠的区域中形成具有开口的抗蚀图案221,将该抗蚀图案221作为掩模来对层间绝缘膜108进行蚀刻,由此,形成将源极・漏极区域106和保护环107的表面各个露出的接触孔209h和接触槽110t。
在除去抗蚀图案221之后,如图12所示那样,在接触孔209h和接触槽110t各自的内侧面和底面以及层间绝缘膜108上形成包括能够遮蔽X射线的材料即钛钨的、阻挡金属层222。
接下来,如图13所示那样,经由阻挡金属层222在接触孔209h内、接触槽110t内和层间绝缘膜108上形成金属层223。接着,在金属层223上形成将在平面视中与接触槽110t、接触孔209h和栅极绝缘膜104重叠的区域选择性地覆盖的抗蚀图案224。之后,将抗蚀图案224作为掩模来利用蚀刻对金属层223和阻挡金属层222进行图案化,由此,同时形成图10所示的阻挡金属膜110、112和214、以及由插塞部111p及布线部111w构成的金属膜111、布线部113和由插塞部215p及布线部215w构成的金属膜215。
如以上那样做,形成了图10所示的半导体装置200。
根据本变形例,在需要在接触孔内形成阻挡金属膜的情况下,能够在同一工序中形成接触孔209h内的阻挡金属膜214和接触槽110t内的阻挡金属膜110。即,能够在不追加用于在接触槽110t内形成阻挡金属膜110的专用的工序的情况下在接触槽110t内形成能够遮蔽X射线的阻挡金属膜110。
再有,在本变形例中,在将在栅极电极105的两侧形成的源极・漏极区域106的一个与布线部113电连接也可的情况下,在形成图13所示的抗蚀图案224的工序中,例如,在不分离的情况下整体地形成位于栅极绝缘膜104的上部的抗蚀图案224和位于一个接触孔209h的上部的224,将其作为掩模来对金属层223和阻挡金属层222进行图案化,由此,分别整体地形成阻挡金属膜112和一个阻挡金属膜214以及布线部113和一个布线部215w是优选的。
图14是用于说明根据本发明的实施方式的第二变形例的半导体装置300的构造的剖面图。关于本变形例,也对与图1和图2所示的半导体装置100相同的结构要素标注同一附图标记,适当省略重复的说明。
在第二变形例的半导体装置300中,在未设置半导体装置100中的阻挡金属膜112和布线部113的情况下在第二层的层间绝缘膜上在平面视中至少与栅极绝缘膜104重叠的区域中设置了能够遮蔽X射线的阻挡金属膜。
具体而言,半导体装置300为以下结构:在半导体装置100中未设置阻挡金属膜112和布线部113的结构中还具备:以将构成第一层的金属布线层的布线部111w和115覆盖的方式设置的第二层的层间绝缘膜316;将在层间绝缘膜316设置的布线部115的表面露出的接触孔317h;将接触孔317h的内侧面和底面覆盖并且在层间绝缘膜316上在平面视中至少与栅极绝缘膜104重叠的区域中设置的、能够遮蔽X射线的阻挡金属膜318;以及包括经由阻挡金属膜318埋入到接触孔317h内的插塞部319p、和与插塞部319p连接且在层间绝缘膜316上经由阻挡金属膜318设置的布线部319w并且与布线部115电连接的、金属膜319。
根据本变形例,在图2所示的半导体装置100中,即使在微细化发展而难以确保布线部113和阻挡金属膜112与布线部115和阻挡金属膜114的布线间隔并且在层间绝缘膜108上在平面视中与栅极绝缘膜104重叠的区域中未设置能够遮蔽X射线的阻挡金属膜112的情况下,也在层间绝缘膜316上的在平面视中至少与栅极绝缘膜104重叠的区域中设置能够遮蔽X射线的阻挡金属膜318,由此,即使从半导体基板101的上表面方向照射X射线,也能够防止X射线被照射到栅极绝缘膜104。
在此,在本变形例的半导体装置300中,采用了使阻挡金属膜318和金属膜319与布线部115电连接的结构,但是,只要能够在层间绝缘膜108上在平面视中与栅极绝缘膜104重叠的区域中形成阻挡金属膜318(和金属膜319)即可,使阻挡金属膜318和金属膜319电连接的第一层的金属布线层的布线部不限于布线部115。
接着,使用图15至19所示的工序剖面图来对图14所示的半导体装置300的制造方法进行说明。
半导体装置300的制造方法在图8所示的阻挡金属层123的形成之前与半导体装置100的制造方法同样。
在图8的工序之后,如图15所示那样,经由阻挡金属层123在接触槽110t内和层间绝缘膜108上形成金属层124。接着,形成将金属层124上的、在平面视中与接触槽110t和接触插塞109各个重叠的区域选择性地覆盖的抗蚀图案321。之后,将抗蚀图案321作为掩模来利用蚀刻对金属层124和阻挡金属层123进行图案化,由此,同时形成图16所示的阻挡金属膜110和114、以及由插塞部111p及布线部111w构成的金属膜111和布线部115。
在除去抗蚀图案321之后,如图17所示那样,以覆盖布线部111w和115的方式在层间绝缘膜108上形成层间绝缘膜316。接着,在层间绝缘膜316上在平面视中与布线部115重叠的区域中形成具有开口的抗蚀图案322,将该抗蚀图案322作为掩模来对层间绝缘膜316进行蚀刻,由此,形成将布线部115的表面露出的接触孔317h。
在除去抗蚀图案322之后,如图18所示那样,以将接触孔317h的内侧面和底面以及层间绝缘膜316的上表面覆盖的方式形成包括能够遮蔽X射线的材料即钛钨的、阻挡金属层323。
之后,如图19所示那样,经由阻挡金属层323在接触孔317h内和层间绝缘膜316上形成金属层324。接着,形成将金属层324上的、在平面视中至少与栅极绝缘膜104重叠的区域选择性地覆盖的抗蚀图案325。
接下来,将抗蚀图案325作为掩模来利用蚀刻对金属层324和阻挡金属层323进行图案化,由此,同时形成图14所示的阻挡金属膜318、以及由插塞部319p和布线部319w构成的金属膜319。
如以上那样做,形成了图14所示的半导体装置300。
以上,对本发明的实施方式进行了说明,但是,本发明不限定于上述实施方式,当然能够在不偏离本发明的主旨的范围内进行各种变更。
例如,在上述实施方式中,示出了使源极・漏极区域106为N型、使阱102和保护环107为P型的例子,但是,使这些导电型反转也可。
附图标记的说明
100、200、300 半导体装置
101 半导体基板
102 阱
103 元件分离区域
104 栅极绝缘膜
105 栅极电极
106 源极・漏极区域
107 保护环
108、316 层间绝缘膜
109 接触插塞
109h、209h、317h 接触孔
110、112、114、214、318 阻挡金属膜
110t 接触槽
111、215、319 金属膜
111p、215p、319p 插塞部
111w、113、115、215w、319w 布线部
121、122、125、221、224、321、322、325 抗蚀图案
123、222、323 阻挡金属层
124、223、324 金属层。
Claims (12)
1.一种半导体装置,其特征在于,具备:
栅极绝缘膜,被设置在半导体基板上;
栅极电极,被设置在所述栅极绝缘膜上;
源极・漏极区域,以与所述栅极电极相邻的方式被设置于所述半导体基板;
元件分离区域,被设置为包围所述栅极电极和所述源极・漏极区域;
保护环,以包围所述元件分离区域的方式被设置于所述半导体基板;
第1层间绝缘膜,被设置为覆盖所述栅极电极、所述源极・漏极区域、所述元件分离区域和所述保护环;
线状的接触槽,以包围所述元件分离区域并且露出所述保护环的表面的方式被设置于所述第1层间绝缘膜;
能够遮蔽X射线的第1阻挡金属膜,被设置为覆盖所述接触槽的内侧面和底面;以及
第1金属膜,包括经由所述第1阻挡金属膜埋入到所述接触槽内的第1插塞部、和与所述第1插塞部连接且在所述第1层间绝缘膜上设置的第1布线部,并且,与所述保护环电连接。
2.根据权利要求1所述的半导体装置,其特征在于,还具备:
在所述第1层间绝缘膜上在平面视中至少与所述栅极绝缘膜重叠的区域中设置的、能够遮蔽X射线的第2阻挡金属膜;以及
被设置在所述第2阻挡金属膜上并且构成与所述第1布线部相同的金属布线层的一部分的、第2布线部。
3.根据权利要求2所述的半导体装置,其特征在于,所述第1阻挡金属膜与所述第2阻挡金属膜为相同的材料。
4.根据权利要求1所述的半导体装置,其特征在于,还具备:
接触孔,以露出所述源极・漏极区域的表面的方式被设置于所述第1层间绝缘膜;
与所述第1阻挡金属膜相同材料的第3阻挡金属膜,被设置为覆盖所述接触孔的内侧面和底面;
与所述第1金属膜相同材料的第2金属膜,包括经由所述第3阻挡金属膜埋入到所述接触孔内的第2插塞部、和与所述第2插塞部连接且在所述第1层间绝缘膜上设置的构成与所述第1布线部相同的金属布线层的一部分的第3布线部,并且,与所述源极・漏极区域电连接。
5.根据权利要求1所述的半导体装置,其特征在于,还具备:
在所述第1层间绝缘膜上以覆盖所述第1布线部的方式设置的第2层间绝缘膜;
在所述第2层间绝缘膜上在平面视中至少与所述栅极绝缘膜重叠的区域中设置的、能够遮蔽X射线的第2阻挡金属膜;以及
在所述第2阻挡金属膜上设置的第2布线部。
6.根据权利要求1至5的任一项所述的半导体装置,其特征在于,所述第1阻挡金属膜包括钛钨。
7.一种半导体装置的制造方法,其特征在于,具备:
在半导体基板上形成栅极绝缘膜的工序;
在所述栅极绝缘膜上形成栅极电极的工序;
以与所述栅极电极相邻的方式在半导体基板形成源极・漏极区域的工序;
以将形成有所述栅极电极和所述源极・漏极区域的区域包围的方式形成元件分离区域的工序;
以包围所述元件分离区域的方式在所述半导体基板形成保护环的工序;
以将所述栅极电极、所述源极・漏极区域、所述元件分离区域和所述保护环覆盖的方式形成第1层间绝缘膜的工序;
以包围所述元件分离区域并且露出所述保护环的表面的方式在所述第1层间绝缘膜形成线状的接触槽的工序;
以将所述接触槽的内侧面和底面覆盖的方式形成能够遮蔽X射线的第1阻挡金属膜的工序;以及
形成第1金属膜的工序,所述第1金属膜包括经由所述第1阻挡金属膜埋入到所述接触槽内的第1插塞部、和与所述第1插塞部连接且在所述第1层间绝缘膜上形成的第1布线部,并且,与所述保护环电连接。
8.根据权利要求7所述的半导体装置的制造方法,其特征在于,
形成所述第1阻挡金属膜的工序和形成所述第1金属膜的工序包括:
在所述接触槽的内侧面和底面及所述第1层间绝缘膜上形成能够遮蔽X射线的阻挡金属层的工序;
经由所述阻挡金属层在所述接触槽内和所述第1层间绝缘膜上形成金属层的工序;
在所述金属层上的在平面视中至少与所述接触槽重叠的区域中选择性地形成抗蚀图案的工序;以及
通过将所述抗蚀图案作为掩模来对所述金属层和所述阻挡金属层进行蚀刻、从而在所述接触槽内残存所述金属层和所述阻挡金属层的一部分来形成包括所述第1阻挡金属膜的所述第1金属膜的工序。
9.根据权利要求8所述的半导体装置的制造方法,其特征在于,
在形成所述第1阻挡金属膜的工序和形成所述第1金属膜的工序中,
在所述金属层上的在平面视中至少与所述栅极绝缘膜重叠的区域中也选择性地形成所述抗蚀图案,
通过将所述抗蚀图案作为掩模来对所述金属层和所述阻挡金属层进行蚀刻,从而在平面视中至少与所述栅极绝缘膜重叠的区域中残存所述阻挡金属层来形成第2阻挡金属膜,并且,在所述第2阻挡金属膜上残存所述金属层来形成构成与所述第1布线部相同的金属布线层的一部分的、第2布线部。
10.根据权利要求8所述的半导体装置的制造方法,其特征在于,
还具备以露出所述源极・漏极区域的表面的方式在所述第1层间绝缘膜形成接触孔的工序,
在形成所述第1阻挡金属膜的工序和形成所述第1金属膜的工序中,
在所述接触孔的内侧面和底面上也形成所述阻挡金属层,
在所述金属层上的在平面视中至少与所述接触孔重叠的区域中也选择性地形成所述抗蚀图案,
通过将所述抗蚀图案作为掩模来对所述金属层和所述阻挡金属层进行蚀刻,从而在所述接触孔内残存所述阻挡金属层来形成第3阻挡金属膜,并且,残存所述金属层来形成第2金属膜,所述第2金属膜包括经由所述第3阻挡金属膜埋入到所述接触孔内的第2插塞部、和与所述第2插塞部连接且在所述第1层间绝缘膜上设置的构成与所述第1布线部相同的金属布线层的一部分的第3布线部,并且,与所述源极・漏极区域电连接。
11.根据权利要求7所述的半导体装置的制造方法,其特征在于,还具备:
在所述第1层间绝缘膜上以覆盖所述第1布线部的方式形成第2层间绝缘膜的工序;
在所述第2层间绝缘膜上在平面视中至少与所述栅极绝缘膜重叠的区域中形成能够遮蔽X射线的第2阻挡金属膜的工序;以及
在所述第2阻挡金属膜上形成第2布线部的工序。
12.根据权利要求7至11的任一项所述的半导体装置的制造方法,其特征在于,所述第1阻挡金属膜包括钛钨。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018-078516 | 2018-04-16 | ||
JP2018078516A JP2019186473A (ja) | 2018-04-16 | 2018-04-16 | 半導体装置及びその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN110391212A true CN110391212A (zh) | 2019-10-29 |
Family
ID=68161989
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910292912.3A Pending CN110391212A (zh) | 2018-04-16 | 2019-04-12 | 半导体装置以及其制造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20190318997A1 (zh) |
JP (1) | JP2019186473A (zh) |
KR (1) | KR20190120717A (zh) |
CN (1) | CN110391212A (zh) |
TW (1) | TW202002217A (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10276581B1 (en) * | 2017-10-31 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit chip and manufacturing method thereof |
KR102706729B1 (ko) * | 2018-11-02 | 2024-09-19 | 에스케이하이닉스 주식회사 | 반도체 장치 및 반도체 장치의 패턴 형성방법 |
CN116759433A (zh) * | 2021-06-09 | 2023-09-15 | 武汉新芯集成电路制造有限公司 | 半导体器件及其制造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0366123A (ja) * | 1989-08-03 | 1991-03-20 | Hitachi Ltd | 半導体集積回路装置及びその形成方法 |
JPH07169804A (ja) * | 1993-12-14 | 1995-07-04 | Hitachi Ltd | 半導体装置およびその半導体装置を組み込んだ電子装置 |
JP2004071538A (ja) * | 2002-05-17 | 2004-03-04 | Semiconductor Energy Lab Co Ltd | 表示装置 |
JP4502173B2 (ja) * | 2003-02-03 | 2010-07-14 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP5862290B2 (ja) * | 2011-12-28 | 2016-02-16 | 富士通セミコンダクター株式会社 | 半導体装置とその製造方法 |
JP2014008360A (ja) * | 2012-07-03 | 2014-01-20 | Canon Inc | 放射線発生装置及び放射線撮影システム |
-
2018
- 2018-04-16 JP JP2018078516A patent/JP2019186473A/ja active Pending
-
2019
- 2019-04-02 TW TW108111769A patent/TW202002217A/zh unknown
- 2019-04-08 US US16/377,589 patent/US20190318997A1/en not_active Abandoned
- 2019-04-12 CN CN201910292912.3A patent/CN110391212A/zh active Pending
- 2019-04-15 KR KR1020190043803A patent/KR20190120717A/ko unknown
Also Published As
Publication number | Publication date |
---|---|
JP2019186473A (ja) | 2019-10-24 |
TW202002217A (zh) | 2020-01-01 |
KR20190120717A (ko) | 2019-10-24 |
US20190318997A1 (en) | 2019-10-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI232542B (en) | Semiconductor device | |
JP5132977B2 (ja) | 半導体装置およびその製造方法 | |
CN110391212A (zh) | 半导体装置以及其制造方法 | |
CN113196500B (zh) | 半导体装置及其制造方法 | |
TWI656639B (zh) | 半導體器件及其形成方法 | |
JP2011040665A (ja) | 半導体装置及びその製造方法 | |
KR101277519B1 (ko) | 저 저항 반도체 접촉 및 이에 따른 구조를 형성하는 방법 | |
US20200168714A1 (en) | Semiconductor device and method for manufacturing the same | |
JP5733885B2 (ja) | 半導体装置およびその製造方法 | |
TW201114012A (en) | Power semiconductor device with drain voltage protection and manufacturing method thereof | |
JP2012230989A (ja) | 半導体装置 | |
CN109830523B (zh) | Nldmos器件及其制造方法 | |
CN109888016B (zh) | Nldmos器件及其制造方法 | |
CN106158744B (zh) | 静电保护结构及其制作方法、芯片及其制作方法 | |
CN103154719A (zh) | 用于离子敏感场效应晶体管的静电放电保护 | |
KR102086776B1 (ko) | 반도체 장치 | |
JP2007150125A (ja) | 半導体装置およびそれの製造方法 | |
KR100575613B1 (ko) | 반도체장치의 게이트산화막 손상방지방법 | |
US10446497B2 (en) | Combined source and base contact for a field effect transistor | |
US20230178646A1 (en) | Semiconductor device | |
KR101921492B1 (ko) | 반도체 소자 및 반도체 소자를 이용한 장치 | |
CN103928505B (zh) | 功率金属氧化物半导体晶体管元件 | |
KR100437617B1 (ko) | 반도체 소자의 디커플링 캐피시터 형성방법 | |
KR101455255B1 (ko) | 반도체 소자의 제조방법 | |
CN117832254A (zh) | 一种GaN基HEMT器件及制作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20191029 |
|
WD01 | Invention patent application deemed withdrawn after publication |