CN110349916A - 半导体器件及制造其的方法 - Google Patents

半导体器件及制造其的方法 Download PDF

Info

Publication number
CN110349916A
CN110349916A CN201910639578.4A CN201910639578A CN110349916A CN 110349916 A CN110349916 A CN 110349916A CN 201910639578 A CN201910639578 A CN 201910639578A CN 110349916 A CN110349916 A CN 110349916A
Authority
CN
China
Prior art keywords
region
tie
tie region
channel region
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910639578.4A
Other languages
English (en)
Other versions
CN110349916B (zh
Inventor
许然喆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN110349916A publication Critical patent/CN110349916A/zh
Application granted granted Critical
Publication of CN110349916B publication Critical patent/CN110349916B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1058—Channel region of field-effect devices of field-effect transistors with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

提供了半导体器件及制造其的方法。一种半导体器件包括：衬底；n型晶体管，其包括置于衬底上的第一结区域、置于第一结区域上的第一沟道区域、置于第一沟道区域上的第二结区域、以及至少部分地围绕第一沟道区域的第一栅极堆叠；以及p型晶体管，其包括置于衬底上的第三结区域、置于第三结区域上的第二沟道区域、置于第二沟道区域上的第四结区域、以及至少部分地围绕第二沟道区域的第二栅极堆叠，其中第一沟道区域和第二沟道区域是外延沟道层。

Description

半导体器件及制造其的方法
本申请是针对申请日为2017年11月24日、申请号为201711191137.X、发明名称为“半导体器件及制造其的方法”的专利申请的分案申请。
技术领域
本发明构思涉及半导体器件及制造其的方法。
背景技术
半导体器件具有诸如小尺寸、多功能性和/或低制造成本的特性，从而被用于许多电子行业中。半导体器件可以包括存储数据的存储器件、计算-处理数据的逻辑元件、能够同时执行各种功能的混合元件等。
由于电子工业的高度发展，半导体器件可以被高度集成，使得半导体器件变得小或精细，并且已经进行了各种研究以便在衬底的有限区域内集成更多诸如晶体管的器件。为了减小一个晶体管所占据的衬底的面积，已经提出了具有安装在衬底上的垂直半导体沟道的各种晶体管结构。
该背景技术部分中公开的以上信息仅用于增强对本发明构思的背景的理解，并且可以包含不构成在该国中已为本领域普通技术人员所知的现有技术的信息。
发明内容
当具有垂直半导体沟道的晶体管被形成以便允许更高的器件集成度时，形成结的工艺会变得更加复杂。本发明构思提供了其工艺管理更容易的半导体器件及制造其的方法。
本发明构思的一示例实施方式提供了一种半导体器件，其包括：衬底；n型晶体管，其包括置于衬底上的第一结区域、置于第一结区域上的第一沟道区域、置于第一沟道区域上的第二结区域、以及至少部分地围绕第一沟道区域的第一栅极堆叠；以及p型晶体管，其包括置于衬底上的第三结区域、置于第三结区域上的第二沟道区域、置于第二沟道区域上的第四结区域、以及至少部分地围绕第二沟道区域的第二栅极堆叠，其中第一沟道区域和第二沟道区域是外延沟道层。
本发明构思的另一示例实施方式提供了一种制造半导体器件的方法，该方法包括：通过将离子注入到衬底的上表面而形成第一掺杂层；通过外延方法在第一掺杂层上形成第一沟道层；通过将离子注入到第一沟道层的上表面而形成第二掺杂层；通过蚀刻第一掺杂层、第一沟道层和第二掺杂层而形成顺序地置于衬底上的第一结区域、第一沟道区域和第二结区域；以及将第一栅极堆叠形成为至少部分地围绕第一沟道区域，其中第一掺杂层和第二掺杂层具有相同的导电类型。
根据本发明构思的一些示例实施方式，一种制造半导体器件的方法包括：形成顺序地堆叠在衬底上的第一掺杂层、外延沟道层和第二掺杂层；分别蚀刻第二掺杂层、外延沟道层和第一掺杂层以限定第二结区域、第一沟道区域和第一结区域；以及响应于该蚀刻，在第一结区域与第二结区域之间的第一沟道区域上形成第一栅极堆叠。
根据本发明构思的一些示例实施方式，一种制造半导体器件的方法包括：在衬底上形成n型晶体管，n型晶体管包括第一结区域、在第一结区域上的第一沟道区域、以及在第一沟道区域上的第二结区域；以及邻近n型晶体管在衬底上形成p型晶体管，p型晶体管包括第三结区域、在第三结区域上的第二沟道区域、以及在第二沟道区域上的第四结区域。第一沟道区域和第二沟道区域是外延层。
根据本发明构思的示例实施方式，下结区域和上结区域在沟道的形成之前被形成，使得可以获得稳定的半导体器件特性。
此外，沟道层通过使用非选择性外延工艺被形成，使得可以容易地实现CMOS晶体管的集合工艺(collective process)。
附图说明
图1是示出根据一示例实施方式的晶体管的剖视图。
图2是示出包括图1的晶体管的CMOS晶体管的剖视图。
图3是示出图2的CMOS晶体管的一修改CMOS晶体管的剖视图。
图4至8是示出制造图1的晶体管的方法的剖视图。
图9至13是示出制造图2的CMOS晶体管的方法的剖视图。
图14和15是示出制造图3的CMOS晶体管的方法的剖视图。
具体实施方式
在下文中，将参照图1描述根据本发明构思的示例实施方式的半导体器件中的晶体管结构。
图1是示出根据一示例实施方式的晶体管的剖视图。
参照图1，根据一示例实施方式的晶体管包括衬底110、置于衬底110上的下结区域120、置于下结区域120上的沟道区域130、至少部分地围绕沟道区域130的栅极堆叠160、以及置于沟道区域130上的上结区域140。
衬底110可以包括诸如硅、多晶硅和锗的半导体材料。在这种情况下，衬底110可以是体硅。虽然未在图1中示出，但是衬底110可以包括P阱区域或N阱区域、或绝缘体上硅(SOI)结构。
在下结区域120中，n型离子或p型离子掺杂在与衬底110的材料相同的材料中。当下结区域120为n型时，下结区域120可以包括诸如磷(P)、砷(As)和/或锑(Sb)的掺杂剂，当下结区域120为p型时，下结区域120可以包括硼(B)作为掺杂剂。
下结区域120可以包括如图1中所示地具有不同厚度的第一部分120x和第二部分120y。第一部分120x厚于第二部分120y，并且是下结区域120的在相对于衬底110的垂直方向上重叠沟道区域130和上结区域140的部分。第二部分120y是不重叠沟道区域130和上结区域140的部分。当在此使用时，术语第一、第二、第三等仅用于将一个区域、部分或元件与另外的区域、部分或元件区分开。
根据本示例实施方式的晶体管还可以包括置于下结区域120的第二部分120y上的间隔物150。间隔物150可以重叠第二部分120y，并且可以具有与下结区域120的第一部分120x的高度相同或者比下结区域120的第一部分120x的高度更大的高度，并且可以具有比沟道区域130的高度更小的高度。间隔物150可以包括氧化物、二氧化硅、硅氮化物，和/或硅氮氧化物。间隔物150可以减少或防止器件的操作速度被寄生电容器或寄生电容降低。
沟道区域130可以包括与衬底110的材料相同的材料，并且可以处于不掺杂的状态。沟道区域130通过执行外延工艺被形成。然而，沟道区域130还可以在器件特性不受影响的范围内包括掺杂剂。例如，器件特性不受影响的范围可以是器件的开-关特性不受影响的范围。
在上结区域140中，n型离子或p型离子掺杂在与沟道区域130的材料相同的材料中。上结区域140中包括的掺杂剂具有与下结区域120的掺杂剂的类型相同的类型。上结区域140可以设置成基于沟道区域130与下结区域120对称的结构。在这种情况下，从沟道区域130的中心部分到上结区域140的距离可以与从沟道区域130的中心部分到下结区域120的距离基本相同。
下结区域120与上结区域140之间的距离，即沟道区域130的厚度，可以是沟道的长度。
栅极堆叠160可以具有至少部分地围绕沟道区域130并且沟道区域130插置于其间的形状。栅极堆叠160可以包括栅极电介质层和覆盖栅极电介质层的栅极导体。栅极电介质层可以包括高电介质材料、氧化物和/或二氧化硅。栅极导体可以由诸如铝、铜、TiN、TaN和TaC的单一导电材料形成，或者通过组合导电材料形成。
接触辅助层145可以置于上结区域140上。接触辅助层145可以通过外延工艺被形成。在这种情况下，当外延工艺被执行时，材料在相对于上结区域140的水平方向以及垂直方向上生长，使得接触辅助层145的宽度可以大于上结区域140的宽度。当接触辅助层145被形成时，可以增大与下面将描述的接触插塞的接触面积，从而减小电阻。
电介质区域165在具有接触孔的同时置于衬底110、下结区域120、沟道区域130、上结区域140和间隔物150上。电介质区域165的接触孔包括分别与下结区域120、上结区域140和栅极堆叠160接触的下接触插塞170、上接触插塞180和栅极接触插塞(未示出)。接触辅助层145置于上结区域140与上接触插塞180之间，使得上接触插塞180可以实质上与接触辅助层145接触。下接触插塞170、上接触插塞180和栅极接触插塞可以由导电材料形成，并且栅极接触插塞(未示出)可以连接到栅极堆叠160的侧表面。然而，本发明构思不限于此。例如，栅极堆叠160的侧部分可以形成为凸出到在垂直于衬底110的方向上不与上接触插塞180重叠的区域，使得栅极接触插塞也可以连接到栅极堆叠160的上表面。
在本示例实施方式中，下结区域120和上结区域140通过下面将描述的离子注入工艺被形成，使得与下结区域120和上结区域140通过外延工艺形成的情况相比，存在极少的掺杂剂限制。具体地，在仅已研究了使用磷(P)作为掺杂剂以便通过外延工艺形成结区域的技术的情况下，当结区域像本示例实施方式那样通过离子注入被形成时，除磷(P)以外，砷(As)和锑(Sb)也可以用作掺杂剂。当相对轻的磷(P)用作掺杂剂时，掺杂剂会在热处理期间分散到沟道区域130，但是像本示例实施方式那样当砷(As)或锑(Sb)用作掺杂剂时，前述分散可以被减少。
图2是示出包括图1的晶体管的CMOS晶体管的剖视图。具体地，图2表示CMOS晶体管，其中参照图1描述的晶体管由n型晶体管和p型晶体管形成。
参照图2，根据本示例实施方式的CMOS晶体管包括n型晶体管100a和p型晶体管100b。
n型晶体管100a包括置于衬底110上的P阱区域115a、置于P阱区域115a上的第一结区域120a、接触第一结区域120a的第一接触插塞170a、置于第一结区域120a上的第一沟道区域130a、至少部分地围绕第一沟道区域130a的第一栅极堆叠160a、置于第一沟道区域130a上的第二结区域140a、置于第二结区域140a上的第一接触辅助层145a、以及接触第一接触辅助层145a的第二接触插塞180a。第一结区域120a和第二结区域140a可以包括n型掺杂剂。
虽然未示出，但是根据本示例实施方式的CMOS晶体管还可以包括与第一栅极堆叠160a连接的栅极接触插塞以及与第二栅极堆叠160b连接的栅极接触插塞。
p型晶体管100b包括置于衬底110上的N阱区域115b、置于N阱区域115b上的第三结区域120b、接触第三结区域120b的第三接触插塞170b、置于第三结区域120b上的第二沟道区域130b、至少部分地围绕第二沟道区域130b的第二栅极堆叠160b、置于第二沟道区域130b上的第四结区域140b、置于第四结区域140b上的第二接触辅助层145b、以及接触第二接触辅助层145b的第四接触插塞180b。第三结区域120b和第四结区域140b可以包括p型掺杂剂。
器件隔离区域113被形成以便隔离n型晶体管100a和p型晶体管100b。器件隔离区域113可以由氧化物层形成，并且可以(例如)由二氧化硅形成。器件隔离区域113可以(例如)通过浅沟槽隔离(STI)工艺或硅的局部氧化(LOCOS)工艺被形成。器件隔离区域113可以使n型晶体管100a和p型晶体管100b绝缘，以便减少或防止不期望的泄漏电流在n型晶体管100a与p型晶体管100b之间流动。
在本示例实施方式中，第一沟道区域130a和第二沟道区域130b两者为外延沟道层。在一些示例实施方式中，第一沟道区域130a和第二沟道区域130b可以掺杂成与第一结区域120a和第三结区域120b中的一个的导电类型相同的导电类型。第一结区域120a可以包括第一部分和具有比第一部分的厚度更小的厚度的第二部分，第三结区域120b可以包括第三部分和具有比第三部分的厚度更小的厚度的第四部分。
图3是示出图2的CMOS晶体管的一修改CMOS晶体管的剖视图。
在图3的示例实施方式中，CMOS晶体管与参照图2描述的CMOS晶体管大部分相同，下面将更详细地描述不同的部分或元件。
参照图3，没有提供根据图2的示例实施方式的CMOS晶体管中包括的P阱区域115a和N阱区域115b，而是提供了绝缘体上硅(SOI)结构，使得氧化物层112以薄膜的形式形成在衬底110上。考虑到按比例缩放，SOI结构能用于减小形成阱区域的工艺负担，并且当使用SOI结构时，不形成pnpn结结构，使得可以减少或防止电流过度流动使得CMOS晶体管被烧毁的闭锁现象。
图4至8是示出制造图1的晶体管的方法的剖视图。
参照图4，下掺杂层120p通过将离子注入到衬底110的上表面被形成。n型离子或p型离子可以掺杂在下掺杂层120p中，并且当随后形成的下结区域为n型时，下掺杂层120p可以包括诸如磷(P)、砷(As)和锑(Sb)的掺杂剂，当下结区域为p型时，下掺杂层120p可以包括硼(B)作为掺杂剂。当在此描述时，掺杂层也可以称为被掺杂层。
接着，退火工艺可以被执行。在离子注入工艺期间，衬底110的晶体内部会产生缺陷，可以通过退火工艺减少缺陷。
参照图5，通过用与衬底110的材料相同的材料执行外延工艺，沟道层130p在下掺杂层120p上被形成。沟道层130p可以处于非掺杂状态，但沟道层130p也可以在器件特性不受影响的范围内包括掺杂剂。非选择性外延工艺可以应用于沟道层130p，并且非选择性外延工艺不是指仅在衬底110的上表面的一部分上形成沟道层130p，而是可以指在衬底110的整个表面上形成沟道层130p。
参照图6，通过将离子注入到沟道层130p的上表面，上掺杂层140p被形成。n型离子或p型离子可以掺杂在上掺杂层140p中，并且上掺杂层140p中包括的掺杂剂具有与下掺杂层120p的掺杂剂的类型相同的类型。
接着，退火工艺可以被执行。在离子注入工艺期间，在沟道层130p的晶体内部会产生缺陷，可以通过退火工艺减少缺陷。
参照图6和7，顺序地置于衬底110上的下结区域120、沟道区域130和上结区域140通过蚀刻下掺杂层120p、沟道层130p和上掺杂层140p被形成。在这种情况下，下掺杂层120p的不重叠沟道区域130的部分被蚀刻，使得下结区域120可以形成为包括具有不同厚度的第一部分120x和第二部分120y。第一部分120x厚于第二部分120y，并且是重叠沟道区域130和上结区域140的部分。
第二部分120y是不重叠沟道区域130和上结区域140的部分。
在图7中，间隔物150可以在第二部分120y上形成。在这种情况下，间隔物150的高度可以与下结区域120的第一部分120x的高度相同或者大于下结区域120的第一部分120x的高度，并且可以小于沟道区域130的高度。
参照图8，栅极堆叠160形成为至少部分地围绕沟道区域130。栅极堆叠160可以包括栅极电介质层以及在栅极电介质层上或覆盖栅极电介质层的栅极导体。栅极电介质层可以包括高电介质材料、氧化物和/或二氧化硅。栅极导体可以由诸如铝、铜、TiN、TaN和TaC的单一导电材料形成，或者通过组合导电材料形成。
然后，具有分别与下结区域120、上结区域140和栅极堆叠160接触的接触孔的电介质区域被形成，然后图1中所示的下接触插塞170和上接触插塞180以及栅极接触插塞(未示出)可以通过填充导电材料被形成。
在一些常规器件中，具有垂直半导体沟道的晶体管可以通过首先形成沟道然后形成下结区域和上结区域被形成。然而，在这种情况下，下结区域会在先前形成的沟道之间的狭窄空间中形成或者通过利用先前形成的沟道之间的狭窄空间形成，栅极堆叠会被形成，然后上结区域会被形成，但是结区域的深度会取决于对栅极堆叠的高度的控制，使得工艺变化会较大。因此，普通的工艺管理会是困难的，使得CMOS晶体管的集合工艺开发上会有难度。然而，在本示例实施方式中，结区域通过使用离子注入工艺被形成，并且应用了非选择性外延工艺，使得CMOS晶体管的集合工艺开发容易，并且可以通过减少外延工艺的量而减小或最小化会产生在每个器件的区域的边界中的缺陷产生区域，从而有利于减小器件的尺寸。
图9至13是示出制造图2的CMOS晶体管的方法的剖视图。
参照图9，器件隔离区域113通过执行器件隔离工艺在衬底110上被形成。在本示例实施方式中，器件隔离区域113可以通过浅沟槽隔离(STI)工艺或硅的局部氧化(LOCOS)工艺被形成。
参照图10，P阱区域115a和N阱区域115b在衬底110中被形成，第一掺杂层120ap和第三掺杂层120bp通过分别将离子注入到P阱区域115a和N阱区域115b被形成。在这种情况下，第一掺杂层120ap可以掺杂以n型离子，并且磷(P)、砷(As)和/或锑(Sb)可以被包括作为n型掺杂剂。第三掺杂层120bp可以掺杂以p型离子，并且硼(B)可以被包括作为p型掺杂剂。
参照图11，通过用与衬底110的材料相同的材料执行外延工艺，沟道层130p在第一掺杂层120ap、器件隔离区域113和第三掺杂层120bp上被形成。因为非选择性外延工艺应用于沟道层130p，所以沟道层130p可以在n型区域和p型区域两者上形成。
然后，第二掺杂层140ap和第四掺杂层140bp通过分别将离子注入到重叠第一掺杂层120ap和第三掺杂层120bp的沟道层130p的上表面被形成。在这种情况下，第二掺杂层140ap中包括的掺杂剂具有与第一掺杂层120ap的掺杂剂的类型相同的类型，并且第四掺杂层140bp中包括的掺杂剂具有与第三掺杂层120bp的掺杂剂的类型相同的类型。
参照图11和12，顺序地置于衬底110上的第一结区域120a、第一沟道区域130a和第二结区域140a通过蚀刻第一掺杂层120ap、沟道层130p和第二掺杂层140ap被形成，顺序地置于衬底110上的第三结区域120b、第二沟道区域130b和第四结区域140b通过蚀刻第三掺杂层120bp、沟道层130p和第四掺杂层140bp被形成。在这种情况下，第一掺杂层120ap的不重叠第一沟道区域130a的部分被蚀刻，并且第三掺杂层120bp的不重叠第二沟道区域130b的部分被蚀刻，使得第一结区域120a可以包括具有不同厚度的第一部分和第二部分，第二部分具有比第一部分的厚度更小的厚度；并且第三结区域120b可以包括具有不同厚度的第三部分和第四部分，第四部分具有比第三部分的厚度更小的厚度。
然后，间隔物150在第一结区域120a和第三结区域120b的第二部分上被形成。
参照图13，第一栅极堆叠160a形成为至少部分地围绕第一沟道区域130a，第二栅极堆叠160b形成为至少部分地围绕第二沟道区域130b。第一栅极堆叠160a和第二栅极堆叠160b的每个可以包括栅极电介质层和覆盖栅极电介质层的栅极导体。
然后，通过形成具有用于接触第一结区域120a、通过外延工艺形成在第二结区域140a上的第一接触辅助层145a、第三结区域120b和通过外延工艺形成在第四结区域140b上的第二接触辅助层145b的接触孔的电介质区域、然后用导电材料填充接触孔，图2中所示的第一接触插塞170a、第二接触插塞180a、第三接触插塞170b和第四接触插塞180b可以被形成。
在本示例实施方式中，用于使器件电绝缘的隔离工艺在外延工艺之前被执行，使得可以降低隔离工艺上的难度，并解决当隔离工艺在形成沟道之后被执行时会需要的热工艺的限制，从而获得稳定的器件特性和隔离特性。
图14和15是示出制造图3的CMOS晶体管的方法的剖视图。
在图14和15的示例实施方式中，制造CMOS晶体管的方法与参照图9至13描述的制造CMOS晶体管的方法大部分相同，下面将更详细地描述不同的部分或元件。
参照图14，氧化物层112通过应用绝缘体上硅(SOI)工艺以薄膜的形式在衬底110与硅单晶层116之间被形成。然后，器件隔离区域113通过执行器件隔离工艺被形成，参照图15，第一掺杂层120ap和第三掺杂层120bp通过将离子注入到硅单晶层116被形成。
在本示例实施方式中，不包括参照图9至13描述的制造CMOS晶体管的方法中的形成P阱区域115a和N阱区域115b的操作，而是执行SOI工艺，使得氧化物层112在衬底110与硅单晶层116之间被形成。
然后，当参照图11至13描述的工艺以相同的方式被执行时，可以制造图3中所示的CMOS晶体管。
在此使用的术语仅是为了描述特定实施方式的目的，并且不旨在成为对示例实施方式的限制。将理解，当一元件被称为“在”另一元件(例如层或衬底)“上”，或者“连接到”或“邻近”另一元件(例如层或衬底)时，它可以直接在所述另一元件上，或者直接连接到或邻近所述另一元件，或者也可以存在居间元件。相反，当一元件被称为“直接在”另一元件“上”，或者“直接连接到”或“紧邻”另一元件时，没有居间元件存在。
还将理解，虽然术语第一、第二等可以在此用于描述各种元件，但这些元件不应受这些术语限制。这些术语仅用于将一个元件与另外的元件区分开。因此，上面讨论的第一元件可以被称为第二元件，而不背离本发明构思的范围。
将理解，除图中所绘的取向之外，诸如“在……之下”、“在……下面”、“下部”、“在……之上”、“上部”等的空间关系术语旨在还涵盖装置在使用或操作中的不同取向。例如，如果图中的装置被翻转，则被描述为“在”另外的元件或特征“下面”或“之下”的元件将取向“在”所述另外的元件或特征“之上”。装置可以被另行取向(旋转90度或者处于另外的取向)，并且在此使用的空间关系描述语被相应地解释。
术语“一”和“该”及类似引用在这里的使用将被解释为涵盖单数和复数两者，除非在此另有指示或者明显与上下文相矛盾。术语“包含”、“具有”、“包括”和“含有”将被解释为开放式术语(即意为“包括但不限于”)，除非另有说明。术语“和/或”包括相关所列举项目中的一个或更多个的任意及所有组合。
虽然已经结合目前被认为是可行的示例实施方式描述了本发明构思，但是将理解，本发明构思不限于所公开的实施方式，而是相反，旨在覆盖所附权利要求的精神和范围内包括的各种修改和等同布置。
本申请要求享有2016年12月9日在韩国知识产权局提交的韩国专利申请第10-2016-0167936号的优先权及权益，其全部内容通过引用合并于此。

Claims (25)

1.一种半导体器件，包括：
衬底；
n型晶体管，包括置于所述衬底上的第一结区域、置于所述第一结区域上的第一沟道区域、置于所述第一沟道区域上的第二结区域和至少部分地围绕所述第一沟道区域的第一栅极堆叠；以及
p型晶体管，包括置于所述衬底上的第三结区域、置于所述第三结区域上的第二沟道区域、置于所述第二沟道区域上的第四结区域和至少部分地围绕所述第二沟道区域的第二栅极堆叠，
其中所述第一沟道区域和所述第二沟道区域是非掺杂的。
2.根据权利要求1所述的半导体器件，其中：
所述第一结区域具有第一部分和第二部分，所述第二部分具有比所述第一部分的厚度小的厚度，所述第三结区域具有第三部分和第四部分，所述第四部分具有比所述第三部分的厚度小的厚度。
3.根据权利要求2所述的半导体器件，其中所述第一沟道区域置于所述第一结区域的所述第一部分上，所述第二沟道区域置于所述第三结区域的所述第三部分上。
4.根据权利要求2所述的半导体器件，还包括：
间隔物，置于所述第一结区域的所述第二部分和所述第三结区域的所述第四部分上。
5.根据权利要求4所述的半导体器件，其中所述间隔物的高度小于所述第一沟道区域或所述第二沟道区域的高度。
6.根据权利要求4所述的半导体器件，还包括：
第一接触插塞，穿透所述间隔物并且接触所述第一结区域的所述第二部分，以及
第三接触插塞，穿透所述间隔物并且接触所述第三结区域的所述第四部分。
7.根据权利要求1所述的半导体器件，还包括：
置于所述第二结区域上的第一接触辅助层和置于所述第四结区域上的第二接触辅助层，
其中所述第一接触辅助层具有比所述第二结区域的宽度大的宽度，所述第二接触辅助层具有比所述第四结区域的宽度大的宽度。
8.根据权利要求7所述的半导体器件，还包括：
接触所述第一接触辅助层的第二接触插塞，以及
接触所述第二接触辅助层的第四接触插塞。
9.根据权利要求1所述的半导体器件，其中：
所述第一栅极堆叠和所述第二栅极堆叠包括包含高电介质材料的栅极电介质层和覆盖所述栅极电介质层的栅极导体。
10.一种半导体器件，包括：
衬底；
置于所述衬底上的第一结区域；
置于所述第一结区域上的第一沟道区域；
置于所述第一沟道区域上的第二结区域；
至少部分地围绕所述第一沟道区域的第一栅极堆叠；
置于所述衬底上的第三结区域；
置于所述第三结区域上的第二沟道区域；
置于所述第二沟道区域上的第四结区域；以及
至少部分地围绕所述第二沟道区域的第二栅极堆叠，
其中所述第一结区域具有第一部分和第二部分，所述第二部分具有比所述第一部分的厚度小的厚度，所述第一沟道区域置于所述第一结区域的所述第一部分上，
所述第三结区域具有第三部分和第四部分，所述第四部分具有比所述第三部分的厚度小的厚度，所述第二沟道区域置于所述第三结区域的所述第三部分上。
11.根据权利要求10所述的半导体器件，还包括：
间隔物，置于所述第一结区域的所述第二部分和所述第三结区域的所述第四部分上。
12.根据权利要求11所述的半导体器件，还包括：
第一接触插塞，穿透所述间隔物并且接触所述第一结区域的所述第二部分，以及
第三接触插塞，穿透所述间隔物并且接触所述第三结区域的所述第四部分。
13.根据权利要求10所述的半导体器件，还包括：
置于所述第二结区域上的第一接触辅助层和置于所述第四结区域上的第二接触辅助层，
其中所述第一接触辅助层具有比所述第二结区域的宽度大的宽度，所述第二接触辅助层具有比所述第四结区域的宽度大的宽度。
14.根据权利要求13所述的半导体器件，还包括：
接触所述第一接触辅助层的第二接触插塞，以及
接触所述第二接触辅助层的第四接触插塞。
15.根据权利要求10所述的半导体器件，其中：
所述第一结区域和所述第二结区域具有n型掺杂剂，所述第三结区域和所述第四结区域具有p型掺杂剂。
16.一种半导体器件，包括：
衬底；
下结区域，置于所述衬底上并且具有第一部分和第二部分，所述第二部分具有比所述第一部分的厚度小的厚度；
沟道区域，置于所述下结区域的所述第一部分上并且是非掺杂的；
上结区域，置于所述沟道区域上；以及
栅极堆叠，至少部分地围绕所述沟道区域并且包括栅极电介质层和覆盖所述栅极电介质层的栅极导体。
17.根据权利要求16所述的半导体器件，还包括：
间隔物，置于所述下结区域的所述第二部分上，
其中所述间隔物的高度小于所述沟道区域的高度。
18.根据权利要求16所述的半导体器件，还包括：
置于所述上结区域上的接触辅助层，以及
接触所述接触辅助层的接触插塞。
19.一种制造半导体器件的方法，该方法包括：
在衬底上形成n型晶体管，所述n型晶体管包括第一结区域、所述第一结区域上的第一沟道区域和所述第一沟道区域上的第二结区域；以及
在邻近所述n型晶体管的所述衬底上形成p型晶体管，所述p型晶体管包括第三结区域、所述第三结区域上的第二沟道区域和所述第二沟道区域上的第四结区域，
其中所述第一结区域具有第一部分和第二部分，所述第二部分具有比所述第一部分的厚度小的厚度，所述第三结区域具有第三部分和第四部分，所述第四部分具有比所述第三部分的厚度小的厚度，以及
其中形成所述n型晶体管和形成所述p型晶体管包括：
在所述衬底上形成外延沟道层、以及蚀刻所述外延沟道层以同时限定所述n型晶体管的所述第一沟道区域和所述p型晶体管的所述第二沟道区域。
20.根据权利要求19所述的方法，其中形成所述n型晶体管和形成所述p型晶体管还包括：
通过将离子注入到所述衬底中，在所述衬底上形成第一掺杂层和第三掺杂层；
通过非选择性外延工艺，在所述第一掺杂层和所述第三掺杂层上形成所述外延沟道层；
通过将离子分别注入到所述外延沟道层的与所述第一掺杂层和所述第三掺杂层相反的表面中，形成第二掺杂层和第四掺杂层，其中所述第一掺杂层和所述第二掺杂层是n型，以及其中所述第三掺杂层和所述第四掺杂层是p型；
顺序地蚀刻所述第二掺杂层和所述第四掺杂层、所述外延沟道层、及所述第一掺杂层和所述第三掺杂层，以限定所述第二结区域和所述第四结区域、所述第一沟道区域和所述第二沟道区域、及所述第一结区域和所述第三结区域；以及
形成第一栅极堆叠以使其至少部分地围绕所述第一沟道区域并形成第二栅极堆叠以使其至少部分地围绕所述第二沟道区域。
21.根据权利要求19所述的方法，其中所述第一部分在所述第一沟道区域之下，并且所述第二部分沿着所述衬底横向地延伸超过所述第一沟道区域，以及其中所述第三部分在所述第二沟道区域之下，并且所述第四部分沿着所述衬底横向地延伸超过所述第二沟道区域。
22.根据权利要求19所述的方法，还包括：
在所述第一结区域的所述第二部分和所述第三结区域的所述第四部分上形成间隔物。
23.根据权利要求19所述的方法，还包括：
在所述第二结区域上形成第一接触辅助层并在所述第四结区域上形成第二接触辅助层，
其中所述第一接触辅助层具有比所述第二结区域的宽度大的宽度，所述第二接触辅助层具有比所述第四结区域的宽度大的宽度。
24.根据权利要求19所述的方法，其中所述第一沟道区域和所述第二沟道区域分别包括与所述第一结区域和所述第三结区域的导电类型相同导电类型的掺杂剂。
25.根据权利要求19所述的方法，其中所述第一结区域和所述第二结区域的每个包括砷(As)和锑(Sb)中的至少一种。
CN201910639578.4A 2016-12-09 2017-11-24 半导体器件及制造其的方法 Active CN110349916B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR10-2016-0167936 2016-12-09
KR1020160167936A KR20180066746A (ko) 2016-12-09 2016-12-09 반도체 소자 및 그 제조 방법
CN201711191137.XA CN108231688B (zh) 2016-12-09 2017-11-24 半导体器件及制造其的方法

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201711191137.XA Division CN108231688B (zh) 2016-12-09 2017-11-24 半导体器件及制造其的方法

Publications (2)

Publication Number Publication Date
CN110349916A true CN110349916A (zh) 2019-10-18
CN110349916B CN110349916B (zh) 2022-12-27

Family

ID=62489610

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201711191137.XA Active CN108231688B (zh) 2016-12-09 2017-11-24 半导体器件及制造其的方法
CN201910639578.4A Active CN110349916B (zh) 2016-12-09 2017-11-24 半导体器件及制造其的方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201711191137.XA Active CN108231688B (zh) 2016-12-09 2017-11-24 半导体器件及制造其的方法

Country Status (3)

Country Link
US (3) US10204834B2 (zh)
KR (1) KR20180066746A (zh)
CN (2) CN108231688B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180066746A (ko) * 2016-12-09 2018-06-19 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR20210129460A (ko) 2020-04-20 2021-10-28 삼성전자주식회사 수직채널 구조체를 포함하는 집적회로 및 그 레이아웃방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5510287A (en) * 1994-11-01 1996-04-23 Taiwan Semiconductor Manuf. Company Method of making vertical channel mask ROM
US20030087495A1 (en) * 1998-08-04 2003-05-08 Micron Technology, Inc. Memory address decode array with vertical transistors
US20080272408A1 (en) * 2007-05-01 2008-11-06 Dsm Solutions, Inc. Active area junction isolation structure and junction isolated transistors including igfet, jfet and mos transistors and method for making
US20140029161A1 (en) * 2011-04-06 2014-01-30 The Florida International University Board Of Trustees Electrochemically activated c-mems electrodes for on-chip micro-supercapacitors
US20160268256A1 (en) * 2015-03-13 2016-09-15 Qualcomm Incorporated Complementary metal-oxide semiconductor (cmos) transistor and tunnel field-effect transistor (tfet) on a single substrate

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4554570A (en) * 1982-06-24 1985-11-19 Rca Corporation Vertically integrated IGFET device
JPH0793365B2 (ja) * 1984-09-11 1995-10-09 株式会社東芝 半導体記憶装置およびその製造方法
JPS63239973A (ja) * 1986-10-08 1988-10-05 テキサス　インスツルメンツ　インコーポレイテツド 集積回路およびその製造方法
KR100576464B1 (ko) * 2003-12-24 2006-05-08 주식회사 하이닉스반도체 반도체소자의 도전배선 형성방법
CN101393904B (zh) * 2007-05-16 2012-08-08 三星电子株式会社 包括层间导电接触的半导体器件及其形成方法
CN107039515B (zh) 2011-12-19 2021-05-25 英特尔公司 高电压场效应晶体管
WO2013101172A1 (en) 2011-12-30 2013-07-04 Seoul National University R&Db Foundation Compound tunneling field effect transistor integrated on silicon substrate and method for fabricating the same
US9484460B2 (en) 2013-09-19 2016-11-01 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device having gate dielectric surrounding at least some of channel region and gate electrode surrounding at least some of gate dielectric
US9306063B2 (en) 2013-09-27 2016-04-05 Intel Corporation Vertical transistor devices for embedded memory and logic technologies
DE102013223263B4 (de) 2013-11-14 2018-09-27 Globalfoundries Inc. Nanodraht - Transistorbauteil und Verfahren
US10361270B2 (en) 2013-11-20 2019-07-23 Taiwan Semiconductor Manufacturing Co., Ltd. Nanowire MOSFET with different silicides on source and drain
US9583615B2 (en) 2015-02-17 2017-02-28 Sandisk Technologies Llc Vertical transistor and local interconnect structure
KR20180066746A (ko) * 2016-12-09 2018-06-19 삼성전자주식회사 반도체 소자 및 그 제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5510287A (en) * 1994-11-01 1996-04-23 Taiwan Semiconductor Manuf. Company Method of making vertical channel mask ROM
US20030087495A1 (en) * 1998-08-04 2003-05-08 Micron Technology, Inc. Memory address decode array with vertical transistors
US20080272408A1 (en) * 2007-05-01 2008-11-06 Dsm Solutions, Inc. Active area junction isolation structure and junction isolated transistors including igfet, jfet and mos transistors and method for making
US20140029161A1 (en) * 2011-04-06 2014-01-30 The Florida International University Board Of Trustees Electrochemically activated c-mems electrodes for on-chip micro-supercapacitors
US20160268256A1 (en) * 2015-03-13 2016-09-15 Qualcomm Incorporated Complementary metal-oxide semiconductor (cmos) transistor and tunnel field-effect transistor (tfet) on a single substrate

Also Published As

Publication number Publication date
CN108231688A (zh) 2018-06-29
US10622258B2 (en) 2020-04-14
CN108231688B (zh) 2022-11-22
US20180166344A1 (en) 2018-06-14
US11127640B2 (en) 2021-09-21
US20200185279A1 (en) 2020-06-11
KR20180066746A (ko) 2018-06-19
US20190139834A1 (en) 2019-05-09
US10204834B2 (en) 2019-02-12
CN110349916B (zh) 2022-12-27

Similar Documents

Publication Publication Date Title
CN101257039B (zh) 半导体结构及其制造方法
CN107887387A (zh) 半导体器件及其制造方法及包括该器件的电子设备
CN106252352A (zh) 半导体设置及其制造方法及包括该设置的电子设备
CN103545370A (zh) 用于功率mos晶体管的装置和方法
KR20140071244A (ko) 핀과 드레인 확장 영역을 포함하는 반도체 디바이스 및 제조 방법
US9379104B1 (en) Method to make gate-to-body contact to release plasma induced charging
CN104517856A (zh) 具有横向fet单元和场板的半导体器件及其制造方法
CN103904116B (zh) 金属氧化物半导体器件和制作方法
WO2007144053A2 (en) Semiconductor device with a trench isolation and method of manufacturing trenches in a semiconductor body
TWI478288B (zh) 閘流體隨機存取記憶體裝置及方法
US20230301069A1 (en) Semiconductor devices and preparation methods thereof
CN109494191A (zh) 半导体器件及其制备方法
US20110101467A1 (en) Stacked semiconductor device and method of manufacturing the same
CN103681850B (zh) 功率mosfet及其形成方法
CN110349916A (zh) 半导体器件及制造其的方法
CN104701236A (zh) 在例如FinFET器件中使用的形成电介质隔离的鳍结构的方法
CN111916448B (zh) 一种半导体器件及其制造方法、电子设备
CN105405890B (zh) 包括带电荷体侧墙的半导体器件及其制造方法
KR100853799B1 (ko) 트렌치 게이트 반도체 소자 및 그의 제조 방법
TWI527195B (zh) 在動態單元中之非對稱應力場效電晶體
CN105489606A (zh) 半导体器件及其制造方法
US11894433B2 (en) Method and structure to improve stacked FET bottom EPI contact
US20230299000A1 (en) Method and structure for forming landing for backside power distribution network
TWI506705B (zh) 半導體裝置及其製造方法
US20230411386A1 (en) Method and structure of forming contacts and gates for staggered fet

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant