CN104701236A - 在例如FinFET器件中使用的形成电介质隔离的鳍结构的方法 - Google Patents

在例如FinFET器件中使用的形成电介质隔离的鳍结构的方法 Download PDF

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CN104701236A
CN104701236A CN201410616975.7A CN201410616975A CN104701236A CN 104701236 A CN104701236 A CN 104701236A CN 201410616975 A CN201410616975 A CN 201410616975A CN 104701236 A CN104701236 A CN 104701236A
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CN104701236B (zh
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N·劳贝特
P·卡雷
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STMicroelectronics International NV
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Abstract

本发明的各个实施例涉及一种在例如FinFET器件中使用的用于形成电介质隔离鳍结构的方法。该方法包括：在由第一半导体材料形成的衬底上，沉积由第二半导体材料形成的第一覆盖层；在第一覆盖层之上，沉积由第三半导体材料形成的第二覆盖层。图案化第一和第二覆盖层以限定鳍，其中每个鳍包括在由第二材料形成的第二区域之上的由第三材料形成的第一区域；氧化物材料填充鳍之间的空间；然后执行热氧化以将第二区域转换为，将由第三材料形成的第一区域与衬底隔离的材料。作为可选的步骤，在沉积氧化物材料以及执行热氧化之前，水平地使由第二材料形成的第二区域变薄。一旦鳍形成并与衬底绝缘，则执行传统的FinFET制作。

Description

在例如FinFET器件中使用的形成电介质隔离的鳍结构的方法
技术领域
本发明涉及集成电路，并且尤其涉及形成在例如FinFET类型集成电路器件中使用的鳍结构的工艺。
背景技术
现有技术教导了使用一个或多个FinFET类型的场效应晶体管的集成电路的形成方法。FinFET晶体管包括用以传导与衬底的表面平行的电流的沟道区。沟道区形成于半导体材料的细长部分中。晶体管的源区和漏区形成在细长形部分中并位于沟道区的两侧。栅极位于在沟道区位置处的细长形部分之上，以及在该处的细长形部分的相对两侧，从而用于设置或控制晶体管的导通状态。该FinFET设计最适合用于制造多沟道晶体管，其中多个细长形部分被并联形成以限定相邻的沟道区，这些沟道区通过晶体管栅极的以垂直方向跨过多个细长形部分的中间栅极部而彼此分隔。
FinFET晶体管由半导体材料制成的至少一个薄部分(被称作″鳍″)创建，该至少一个薄部分限定了细长形部分，细长形部分用于形成晶体管的沟道以及它的源区和漏区。鳍典型地由掩模限定，该掩模形成在单晶硅(或其他的半导体材料，例如硅锗)的顶部上在鳍的位置。然后衬底材料在没有掩膜的地方被方向性地刻蚀到确定的深度，从而使得限定了鳍的细长形部分在掩模下保留并由衬底材料组成。
在一个现有技术实施例中，这样获得并且包括最终晶体管的沟道的半导体材料的鳍不与电路衬底的有源部电绝缘，该有源部本身也是晶体半导体材料。这样的FinFET器件遭受三种不同类型的漏电流。第一种漏电流可以经由处于沟道之下的衬底的有源部，在FinFET晶体管的源极和漏极之间环流(circulate)。位于各晶体管内部的第一漏电流不受施加到晶体管栅极的电势控制。第二种漏电流由于FinFET晶体管的沟道也经由衬底与相同导电类型的其他晶体管电接触而产生。第二漏电流以晶体管间的漏电流的形式在晶体管之间流动。第三种漏电流响应于衬底被连接到参考电势，而出现在各FinFET晶体管的沟道与衬底的下部分之间。
为了处理上面提到的漏电流问题，在本技术领域已知有用于将鳍电介质隔离的工艺。
在一种被称作通过STI底部氧化(BOTS)技术中，在鳍的两侧都形成有浅槽隔离(STI，shallow trench isolation)结构。鳍的硅材料在顶侧由阻挡结构层(例如，由氮化硅制成)保护，并且在鳍的上横向侧由另一个阻挡结构层(例如，由氮化硅制成)将其从STI结构隔离。然后集成电路晶片经受氧化工艺。阻挡结构层作为氧气(O2)阻挡结构并且鳍的下部分(低于该横向阻挡结构层)被转变为热氧化材料，其将鳍的上部分与下方的衬底材料隔离。该工艺在鳍的底部产生不合需要的扇贝形(scalloped)界面形状(由于热氧化生长的特性的影响)。另外，该工艺与由硅锗(SiGe)制成的鳍不兼容，并且因此不能方便地在形成p沟道SiGe FinFET器件时使用。
在本技术领域中被称为悬空硅(SON)的另一种技术中，鳍的底部由硅锗形成并且鳍的上部分由硅形成。选择性的刻蚀被执行以去除底部SiGe部分，以使在硅鳍的下侧与其下方的衬底之间的区域开口。然后电介质材料填充操作被执行，从而用绝缘材料填充该开口区域。该工艺向对于硅鳍会出现机械稳定性问题。另外，不能确保用绝缘材料完全填充开口区域，并且留下的任何空隙都会表现出隧道填充保形性问题。
因此在本技术领域存在对于改进工艺以在FinFET构造期间将鳍与衬底隔离的需求。
随着CMOS工艺持续朝着越来越小的尺寸发展，必须进一步改进晶体管性能。本领域技术人员认识到使用硅锗(SiGe)材料用于晶体管制造在晶体管性能方面提供了重要的进步，尤其对于p沟道场效应晶体管器件而言。实际上，该技术朝着将SiGe用于许多不同类型的p沟道器件发展。具体对于FinFET器件的使用而言，本领域技术人员认识到需要从SiGe材料形成p沟道器件的鳍，以便达到超过仅采用Si材料的现有技术器件的改进的晶体管性能指标。另外，SiGe鳍必须与下方衬底绝缘，最起码需要关注如上所述的漏电流。
因此，需要改进的工艺以便在FinFET构造过程中将鳍与衬底隔离，包括需要提供与形成SiGe结构相兼容的解决方案。
发明内容
在一实施例中，一种方法包括：在由第一材料形成的衬底上，沉积由第二材料形成的第一覆盖层；在第一覆盖层之上沉积由第三材料形成的第二覆盖层；图案化第一和第二覆盖层以限定多个鳍，每个鳍包括在由第二材料形成的第二区域之上的由第三材料形成的第一区域；沉积氧化物材料以填充多个鳍之间的空间；以及执行热氧化以将第二区域转换为，将由第三材料形成的第一区域与由第一材料形成的衬底绝缘的材料。
在一实施例中，一种方法包括：在由第一材料形成且具有第一区域和第二区域的衬底上，沉积由第二材料形成的覆盖的第一层；在第一层之上对于第一区域形成第一材料部分；在第一层之上对于第二区域形成第二材料部分；图案化第一材料部分以及第二材料的第一层以限定至少一个第一鳍，每个第一鳍包括在由第二材料形成的第二部之上的由第一材料部分形成的第一部；图案化第二材料部分以及第二材料的第一层以限定至少一个第二鳍，每个第二鳍包括在由第二材料形成的第二部之上的由第二材料部分形成第一部；沉积氧化物材料以填充第一和第二鳍之间的空间；以及执行热氧化以将第一鳍和第二鳍的第二部转换为，将第一和第二鳍的第一部与由第一材料形成的衬底绝缘的材料。
附图说明
为了更好地理解本发明，现在将仅示例性地参考附图，其中：
图1-图16示出在块状衬底上形成鳍(例如，用于FinFET器件)的过程中的工艺步骤。
具体实施方式
现在参考图1-图16，图1-图16示出在块状衬底上形成鳍的工艺步骤。应当注意到图示不一定按比例呈现。
图1示出从硅衬底14开始的传统块状硅衬底晶片10。
使用外延工艺工具，执行本领域熟知的外延生长工艺以在块状硅衬底晶片10的硅衬底14上生长硅锗(SiGe)层12。硅锗(SiGe)层12的厚度例如为大约10nm到60nm。可以根据应用选择SiGe层中Ge的含量，例如，为了n沟道或p沟道器件的形成，这将在下面讨论。在一实施例中，Ge含量的范围可以从大约10％到大约40％。在不将衬底晶片10从外延工艺工具去除的情况下，执行本领域熟知的外延生长工艺以在硅锗(SiGe)层12上生长硅(Si)层16。硅(Si)层16的厚度例如为大约10nm到60nm。图2中的点虚线被提供以区别SiGe材料与Si材料。当为了集成电路应用或制造工艺的需求时，硅锗(sige)层12和硅层16可以被掺杂。例如，n型或p型掺杂剂可以被添加到硅层16以支持n沟道和p沟道晶体管的构造。
虽然这些描述是具体关于将硅用于层16，但是本质上该描述是例示性的，并且应该理解层16可以包括其他的半导体材料，例如包括硅锗，如将要在本文论述的那样。在这样的实施中，如果存在于层16中的锗的百分比含量不同于层12中的呈现，则存在优点。
图3示出在硅(Si)层16之上沉积氮化硅(SiN)层20。层20可以具有大约10nm到100nm的厚度。
现在参考图4。然后使用在本领域熟知的光刻技术以限定用于FinFET器件的鳍50。在硅(Si)层18的顶表面之上施加的氮化硅(SiN)层20被光刻图案化以在鳍50的预定位置处留下SiN掩模材料。然后在每个鳍50两侧执行刻蚀操作以在硅(Si)层16和硅锗(SiGe)层12中开孔52。孔52进一步延伸以部分地到达衬底14中，从而确保鳍深度完全穿过硅锗(SiGe)层12。因此每个鳍50被形成为包括在由硅锗(SiGe)层12制成的区域之上的由硅(Si)层16构成的区域。在一更优选的实施中，刻蚀工艺可以利用侧壁图像转移(SIT)工艺，例如在美国专利号8,298,954中描述的，其中的公开通过引用的方式被并入。
然后如图5所示执行可选的选择性刻蚀，以在层12的硅锗(SiGe)材料的位置处在鳍50的每侧的侧壁中形成槽(notch)54。使用的刻蚀技术被选择性的，用于相对于层16中的硅除去层12中的硅锗。例如，如本领域技术人员所熟知的，刻蚀技术可以包括HCl或WETS刻蚀。重要的是，刻蚀过程是受控的从而使得仅硅锗的部分被去除并且区域16仍然被支撑。
然后执行沉积工艺以沉积电介质填充材料60。材料60填充鳍50之间的空间并且包括槽54(如果存在)。沉积工艺可以包括，例如，化学气相沉积工艺，并且电介质填充材料可以包括，例如，二氧化硅(SiO2)。沉积的材料60也将在由氮化硅(SiN)层20形成的掩模之上覆盖每个鳍50的顶部。平坦化工艺(例如，化学机械抛光(CMP))，被用来使晶片的顶部平坦化。抛光工艺被配置用于停止在由氮化硅(SiN)层20形成的掩模处。二氧化硅(SiO2)沉积和抛光工艺的结果如图6所示。
然后在图7中晶片经受在本领域中熟知的热氧化工艺，使用下列工艺条件和参数：使用本领域熟知的快速热氧化(RTO)工艺，在氧气环境下在700℃-1100℃的温度范围内达10-500秒。掩模由氮化硅(SiN)层20形成，起到防止氧气(O2)侵蚀每个鳍50的顶部的阻挡结构的作用。然而，热氧化工艺将消耗每个鳍50的层12的残留的硅锗(SiGe)材料部分以及层16的硅材料的横向侧的小部分，以便转换为二氧化硅(SiO2)。热氧化工艺的结果如图8所示。横向设置在鳍50之间以使得鳍彼此绝缘的电介质填充材料(在这些例子中，为二氧化硅(SiO2))现在进一步在层16的硅材料之下存在，从而使得每个鳍50与下方的晶片的衬底14绝缘。
然后如图9所示执行选择性的刻蚀，以去除由氮化硅(SiN)层20形成的掩模并且露出用于每个鳍50的层16的硅材料的顶部。选择性的刻蚀被设计成选择性地去除氮化硅材料。在一实施例中，刻蚀可以包括以本领域技术人员所熟知的方式施加的H3PO4。在一实施例中，刻蚀可以使用RIE工艺执行。
然后，例如使用如本领域技术人员熟知的湿法或干法化学工艺，来执行隔离凹槽工艺，以去除电介质填充材料60的材料(SiO2)的一部分(例如至大约等于或略微低于层16的硅材料的底部的深度)，从而对于每个鳍50，从层16露出硅材料的区域的侧表面。隔离凹槽工艺的结果如图10所示。电介质填充材料60的剩余部分62覆盖下方的晶片的衬底14，并且对于每个鳍50，将层16的硅材料的底部与下方衬底14绝缘。
然后在图11中晶片经受在本领域中熟知的热氧化工艺。从而对于每个鳍50，在硅材料的侧部和顶部生长了二氧化硅(SiO2)的层70。应该理解层70可以可替换地被沉积，例如使用如本领域技术人员熟知的在低温SiO2原子层沉积。
然后执行沉积工艺以沉积非晶硅(Si)材料80以覆盖鳍50。如果有需要，非晶硅(硅)材料80可以被抛光，以在晶片上提供平坦的操作表面。现在准备以本领域技术人员所熟知的方式将晶片进一步处理以生产集成电路器件，例如为任一导电类型的FinFET晶体管。
例如，非晶硅(Si)材料80可以包括关于形成用于FinFET晶体管的虚设(dummy)栅极结构的起始材料。用于在已形成的鳍50/50′之上形成栅极的工艺、以及用于限定源极和漏极区域的工艺、以及用于制作到源极、漏极和栅极的电接触的工艺，对本领域技术人员来说是熟知的，因此将不会在这里描述。
如上所述的和在图1-图12中示出的工艺将被具体化以形成由硅(Si)材料制成的鳍50。然而，应该理解，图1-图12的工艺将同样地与由硅锗(SiGe)材料制成的鳍的制造相兼容。在这样的工艺中，在图2中形成的层16将代之以由硅锗(SiGe)材料形成。在一实施例中，包括在层12的硅锗材料中的锗的量不同于包括在层16的硅锗材料中的锗的量。例如，层12可以包括大约40％的锗，层16可以包括大约＞10％的锗。图4-图12的剩余的工序仍然一样，除了需要修改下列具体的操作以支持SiGe鳍的形成：对于富锗(Ge-rich)材料(诸如对于层12的40％的Ge含量)，刻蚀侵蚀将是选择性的，以产生槽，随后执行氧化，该氧化比SiGe区域16更快地消耗SiGe区域12。
对于形成互补晶体管结构，例如对于在共有的晶片上形成p型和n型FinFET晶体管而言，本领域技术人员理解，在从掺杂的Si鳍中形成n型晶体管的同时从掺杂的SiGe鳍中形成p型晶体管的优点。再一次地，图1-图12的工艺与两种类型的FinFET晶体管中任一种或实际上两种都兼容。在采用硅(Si)层16形成了图3所示的结构以及覆盖的氮化硅(SiN)层20之后，然后使用本领域熟知的光刻工艺以形成氮化硅(SiN)层20中的开口22，该开口22向下延伸至少达到硅(Si)层16的顶表面。光刻工艺的结果如图13所示。开口22与衬底晶片10的保留用于形成p沟道FinFET器件的区域24相关联。反之，衬底晶片10的区域26被保留用于形成n沟道FinFET器件。在平面视图中，开口22可以采用任何需要的形状，这取决于要在区域24内形成的p沟道器件的尺寸和数量。
然后，通过使用外延工艺工具，执行本领域熟知的高压方向性刻蚀工艺(例如RIE工艺)，以去除硅(Si)层16的在区域24内的部分，下至硅锗(SiGe)层12。在一实施例中，方向性刻蚀可以包括高压HCl刻蚀。方向性刻蚀工艺的结果如图14所示。
在不从用于图14的刻蚀的外延工艺工具去除衬底10的情况下，然后执行本领域熟知的外延生长工艺以在硅锗(SiGe)层12的顶部生长附加的硅锗(SiGe)层30，以填充之前被去除的硅(Si)层16的部分28。外延生长工艺的结果如图15所示。图15中的点虚线被提供以区别SiGe材料与Si材料。用于层30的锗百分比含量可以包括大约10％的锗，同时用于层16的锗百分比含量可以包括大约40％的锗(如在图15中的点虚线的不同程度所提示的)。区域24中的附加的硅锗(SiGe)层30的厚度优选地至少达到相邻区域26中的硅(Si)层16的厚度。再一次地，层30的SiGe材料可以按应用所需地掺杂。然后氮化硅(SiN)层20可以被去除并置换以新的氮化硅(SiN)层20′，该新氮化硅层20′覆盖晶片并且随后可以被图案化用于如上所述的鳍的掩模。
然后该工艺继续进行图4-图12所示的操作。在该工艺结束之时，如图16所示，衬底晶片10的区域24将包括硅锗材料(例如用于在p沟道FinFET器件的形成过程中)的鳍50′，并且衬底晶片10的区域26将包括硅材料(例如用于在n沟道FinFET器件的形成过程中)的鳍50。
这里公开的用于形成鳍50/50′的工艺具有优于用于块状衬底支持的FinFET器件的现有技术的许多优点，包括：a)该工艺比现有技术的BOTS或SON工艺更简单；b)鳍高度由外延生长工艺决定，与依赖例如SiO2凹槽以限定鳍尺寸的传统批处理工艺相比，产生尺寸更一致的鳍；c)用于n沟道FinFET器件的鳍50由硅(从硅(Si)层16)形成，并且用于p沟道的FinFET的鳍50′由硅锗(从硅锗(SiGe)层30)形成，这相对于两种导电类型的晶体管两者都促成了更好的晶体管性能；d)鳍50/50′的源极/漏极区与块状硅衬底14通过电介质材料(二氧化硅(SiO2))隔离，从而抑制结泄漏(junction leakage)；e)该工艺技术很适合用在强烈地缩放的、处于10nm以及低于10nm的工艺节点的CMOS制造技术中；以及f)可以在从经开槽的SiGe区域产生电介质隔离时，保持对氧化的良好控制。该方法的步骤可以与半导体制造相同并可以以有限的成本应用。
前面的描述已经通过示例性且非限制性的示例，提供了对本发明的例示性实施例的全面且翔实的描述。然而，对于相关领域的技术人员而言，鉴于前面的描述，当结合附图和附带的权利要求来阅读本说明书时，各种修改和适配会变得显而易见。然而，所有对本发明的教导的这类和类似的修改都将落入如所附的权利要求所限定的本发明的范围。

Claims (20)

1.一种方法，包括：
在由第一材料形成的衬底上，沉积由第二半导体材料形成的第一覆盖层；
在所述第一覆盖层之上，沉积由第三半导体材料形成的第二覆盖层；
图案化所述第一覆盖层和所述第二覆盖层以限定多个鳍，每个鳍包括在由所述第二半导体材料形成的第二区域之上的由所述第三半导体半导体材料形成的第一区域；
沉积氧化物材料以填充所述多个鳍之间的空间；以及
执行热氧化以将所述第二区域转换为如下材料，所述材料将由所述第三半导体材料形成的所述第一区域与由所述第一材料形成的所述衬底绝缘。
2.根据权利要求1的方法，其中所述第一材料是硅，所述第二半导体材料是硅锗，并且所述第三半导体材料是硅。
3.根据权利要求1的方法，其中所述第一材料是硅，所述第二半导体材料是具有第一百分比含量的锗的硅锗，并且所述第三材料是具有不同于所述第一百分比含量的第二百分比含量的锗的硅锗。
4.根据权利要求1的方法，进一步包括从所述多个鳍形成FinFET晶体管。
5.根据权利要求1的方法，进一步包括去除填充所述多个鳍之间的所述空间的所述氧化物材料，以便露出由所述第三半导体材料形成的所述第一区域的侧表面。
6.根据权利要求5的方法，进一步包括使由所述第三半导体材料形成的所述第一区域的所述侧表面氧化。
7.根据权利要求6的方法，进一步包括沉积第四材料以覆盖经氧化的由所述第三半导体材料形成的所述第一区域。
8.根据权利要求7的方法，其中所述第四材料与所述第一材料相同。
9.根据权利要求8的方法，其中所述第一材料和所述第四材料是硅，并且所述第二半导体材料是硅锗。
10.根据权利要求1的方法，进一步包括在沉积了所述氧化物材料以及执行了所述热氧化之前，水平地减薄由所述第二半导体材料形成的所述第二区域。
11.根据权利要求1的方法，其中图案化所述第一覆盖层和所述第二覆盖层包括：
在由第三半导体材料形成的所述第二覆盖层之上，沉积掩模层；以及
图案化所述掩模层以提供用于形成所述多个鳍的掩模。
12.一种方法，包括：
在由第一半导体材料形成并且具有第一区域和第二区域的衬底上，沉积由第二半导体材料形成的覆盖的第一层；
在所述第一层之上，针对所述第一区域形成第一半导体材料部分；
在所述第一层之上，针对所述第二区域形成第二半导体材料部分；
图案化所述第一半导体材料部分以及所述第二半导体材料的所述第一层以限定至少一个第一鳍，每个第一鳍包括在由所述第二半导体材料形成的第二部之上的由所述第一半导体材料部分形成的第一部；
图案化所述第二材料部分以及所述第二半导体材料的所述第一层以限定至少一个第二鳍，每个第二鳍包括在由所述第二半导体材料形成的第二部之上的由所述第二半导体材料形成的第一部；
沉积氧化物材料以填充所述第一鳍和所述第二鳍之间的空间；以及
执行热氧化以将所述第一鳍和所述第二鳍的第二部转换为如下材料，所述材料将所述第一鳍和所述第二鳍的所述第一部与由所述第一材料形成的所述衬底绝缘。
13.根据权利要求12的方法，其中所述第一半导体材料是硅，并且所述第二半导体材料是硅锗。
14.根据权利要求12的方法，进一步包括：
从所述第一鳍形成第一导电类型的FinFET晶体管；以及
从所述第二鳍形成第二导电类型的FinFET晶体管。
15.根据权利要求14的方法，其中所述第一导电类型是n型，并且所述第二导电类型是p型。
16.根据权利要求12的方法，进一步包括在沉积了所述氧化物材料以及执行了所述热氧化之前，水平地减薄所述第一鳍和所述第二鳍的所述第二部。
17.根据权利要求12的方法，进一步包括去除填充所述鳍之间的所述空间的所述氧化物材料，以便露出所述第一鳍和所述第二鳍的所述第一部的侧面。
18.根据权利要求17的方法，进一步包括使露出的所述侧面氧化。
19.根据权利要求18的方法，进一步包括沉积材料以覆盖经氧化的所述第一鳍和所述第二鳍的所述第一部。
20.根据权利要求12的方法，其中所述衬底是块状衬底。
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