CN110301042A - 带有导线键合网的半导体封装 - Google Patents

带有导线键合网的半导体封装 Download PDF

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Publication number
CN110301042A
CN110301042A CN201880012045.7A CN201880012045A CN110301042A CN 110301042 A CN110301042 A CN 110301042A CN 201880012045 A CN201880012045 A CN 201880012045A CN 110301042 A CN110301042 A CN 110301042A
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China
Prior art keywords
bonding
lead
tube core
welding pad
leads
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CN201880012045.7A
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CN110301042B (zh
Inventor
S·P·古鲁姆
A·S·南吉亚
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

半导体封装包括引线框架，引线框架具有管芯附接焊盘(502)和引线(504)。管芯(300)附接到管芯附接焊盘(502)并电连接到引线(504)。管芯(300)包括沿管芯(300)的外围的键合焊盘(302)和围绕管芯(300)中的电路(314)的键合焊盘条(316)。第一键合导线(306)键合在键合焊盘条(316)的第一相对侧之间。第一键合导线(306)沿第一方向对齐。第二键合导线(308)键合在键合焊盘条(316)的第二相对侧之间。第二键合导线(308)沿第二方向对齐。模制化合物(502)覆盖引线框架(502，504)、管芯(300)、键合焊盘条(316)、第一键合导线(306)和第二键合导线(308)的部分。

Description

带有导线键合网的半导体封装
技术领域
本文通常涉及半导体封装，更具体地涉及具有导线键合的半导体封装。
背景技术
半导体封装包括附接到引线框架并且电连接到引线框架的引线的半导体管芯。封装包封，例如，模制化合物保护半导体管芯免受外部操作环境的影响。由于封装半导体管芯，一些高精度模拟器件(例如，数据转换器、放大器、电压或电流基准、传感器等)的各种参数的精度可能会降低。这种精度的降低可以表现为参数分布的增加(例如，偏移电压、参考电压等的分布)，这又限制了可以为半导体封装指定的某些参数非常少。半导体封装中的应力的一个主要原因是模制化合物中的填料颗粒。通常，80-90％的模制化合物由填料颗粒组成。模制化合物还含有环氧树脂和硬化剂。对于填料颗粒和树脂，热膨胀系数(CTE)显著不同。因为树脂和填料颗粒具有显著不同的CTE值，所以半导体封装可能由于温度变化而经历半导体管芯上的局部应力变化。
发明内容
一个方面提供一种半导体封装。该半导体封装包括引线框架，该引线框架具有管芯附接焊盘和多个引线。管芯附接到管芯附接焊盘并电连接到多个引线。管芯包括沿管芯外围的多个键合焊盘和围绕管芯中的电路的键合焊盘条。第一多个键合导线键合在键合焊盘条的第一相对侧之间。第一多个键合导线沿第一方向对齐。第二多个键合导线键合在键合焊盘条的第二相对侧之间。第二多个键合导线沿第二方向对齐。模制化合物覆盖引线框架、管芯、键合焊盘条、第一多个键合导线和第二多个键合导线的部分。
在另一方面，半导体封装包括管芯，该管芯沿着管芯的外围具有多个键合焊盘，以及围绕管芯中的电路的键合焊盘条。第一多个键合导线键合在键合焊盘条的第一相对侧之间，并且第一多个键合导线沿第一方向对齐。第二多个键合导线键合在键合焊盘条的第二相对侧之间，第二多个键合导线沿第二方向对齐。模制化合物覆盖引线框、管芯、键合焊盘条、第一多个键合导线和第二多个键合导线的部分。
又一方面提供一种用于封装半导体管芯的方法。管芯附接到引线框架的管芯附接焊盘。第一多个键合导线沿第一方向附接在键合焊盘条的第一相对侧之间。键合焊盘条位于管芯的表面上并围绕管芯中的电路。然后，第二多个键合导线沿第二方向附接在键合焊盘条的第二相对侧之间。此后，管芯电连接到引线框架的多个引线。使用模制化合物，覆盖管芯、第一和第二多个键合导线以及引线框架的部分。
附图说明
图1示出具有模制化合物的半导体封装的横截面的部分；
图2示出具有大填料颗粒的模制化合物的半导体封装；
图3是根据示例的具有导线键合网的管芯的平面图；
图4是根据示例的具有导线键合网的管芯的三维视图；
图5是根据示例的四方扁平无引脚(QFN)封装中的管芯的横截面图；
图6是图5的一部分的放大横截面图，示出了导线键合网和模制化合物中的填料颗粒；
图7是根据示例的QFN封装中的管芯的横截面图，示出了模制化合物与管芯的表面之间的空隙；和
图8是示出根据示例的用于封装半导体管芯的方法的流程图。
具体实施方式
来自封装的应力可以影响半导体管芯(下文中称为“管芯”)上的组件的性能，例如晶体管、电阻器和电容器。已经确定问题的根源是填料颗粒的尺寸，填料颗粒包括在管芯的封装过程中使用的模制化合物。所公开的示例通过限制在管芯中的电路附近的半导体封装中的填料颗粒的最大尺寸来解决上述问题。
图1示出半导体封装100的横截面的一部分。半导体封装100包括其上形成集成电路的管芯102、应力缓冲层110和模制化合物120。集成电路包括电容器106和108和/或附加组件。应力缓冲层110覆盖管芯102，并且模制化合物120设置在与集成电路相对的应力缓冲层110的表面上。模制化合物也位于管芯102的部分上。形成在管芯上的集成电路是，例如，电压参考、电流参考、传感器、数据转换器(例如模数转换器)、放大器或任何其他类型的电路。
应力缓冲层110是聚酰亚胺、基于硅树脂的材料或其他合适的材料，以减少模制化合物在集成电路上引起的应力。应力缓冲层110减小了由于半导体衬底102上的模制化合物120中的填料颗粒引起的应力的变化。应力缓冲层具有在图1中标记为T1的厚度。应力缓冲层110的厚度在1微米(micron)至50微米的范围内。
模制化合物120包括树脂132(例如，聚合物树脂)，并且树脂132包括填料颗粒130(参见封装100的部分放大图像150)。在图1中已经将两种填料颗粒标识为填料颗粒130a和130b。模制化合物中的填料颗粒在本文中统称为填料颗粒130。填料颗粒130包括二氧化硅(SiO2)、氧化铝(Al2O3)或其他合适的材料。二氧化硅填料减少了模制化合物对水分的吸收，降低了模制化合物的热膨胀系数(CTE)。
如图1的示例中所示，模制化合物120中的填料颗粒130具有多种尺寸。也就是说，一些填料颗粒130比其他填料颗粒大。例如，填料颗粒130b大于填料颗粒130a。
这里提到填料颗粒130的“尺寸”。在填料颗粒130是球形的示例中，该特定填料颗粒的尺寸是球体的直径。在填料颗粒130是非球形并且具有非几何形状的示例中，尺寸可以指填料颗粒的相对表面之间的最大距离。在放大视图150中，填料颗粒130c显示为具有尺寸SI，其表示穿过填料颗粒的最大距离。
已经确定，填料颗粒130和填料颗粒130所在的树脂132具有不同的热膨胀系数(CTE)和模量(当纵向拉伸或压缩时，材料承受长度变化的能力的度量)。因为树脂132和填料颗粒130具有基本上不同的CTE和模量值，所以封装可以由于温度变化而经历半导体衬底(管芯)上的局部应力变化。大填料颗粒在半导体衬底上引起更高的应力梯度。例如，图1示出了电容器对106和108，如上所述，它们可以是形成在半导体衬底102上的集成电路的部分。这种电容器可以用在，例如，逐次逼近寄存器模数字转换器(SAR ADC)中。为了提高SARADC的精度和准确度，电容器106和108匹配(例如，相同的电容值)。电容器的不匹配的变化不应超过阈值量，而不影响SAR ADC精度。然而，如果模制化合物含有尺寸大于50微米的填料颗粒，则由模制化合物引起的局部应力会不利地影响电容器保持匹配的程度。
图2示出了具有尺寸大于50微米的填料颗粒(称为“大填料颗粒”)的模制化合物。填料颗粒130d，例如，可具有75微米或更大的尺寸。在该尺寸下，填料颗粒130d在下面的电容器108上施加与相邻区域不同的应力。然而，电容器106上方的填充物颗粒(通常在190处标识)小于在电容器108上方的区域195中的填充物颗粒130d，因此与电容器108相比，电容器106可以在变化的温度的情况下经历不同的应力水平。由于在电容器106上方的区域190中存在更多树脂132并且因为树脂具有与由二氧化硅制成的填料颗粒130明显不同的CTE和模量，电容器106由于温度和其他应力因素的变化而经历与电容器108明显不同的应力水平。
本公开的各种示例通过使用导线键合网过滤大颗粒来解决由于大填料颗粒引起的应力问题。在管芯中的电路上的导线键合网过滤大的填料颗粒，使得大的填料颗粒保持与管芯中的电路一定距离，因此，减少了由于大填料颗粒引起的应力。
现在参考图3，示出了根据示例的具有导线键合网的管芯300的平面图。图3示出了具有多个键合焊盘302、管芯300中的电路314、键合焊盘条316以及由键合导线306、308、310和312形成的导线键合网的管芯300(从成品半导体晶片单个化)，键合导线306、308、310和312附接到键合焊盘条316的多个侧。键合导线306、308、310和312中的每个具有附接到键合焊盘条316的相对侧的两端。键合焊盘条316位于管芯300的有源表面上。在一个示例中，键合焊盘条316是连续的金属片，其形状为矩形。在另一个示例中，键合焊盘条316的形状包括正方形或圆形或围绕管芯302中的电路314的任何其他封闭结构。在又一个示例中，键合焊盘条是部分围绕该管芯的结构。在该示例中，在电路的相对端上存在键合焊盘条316表面，但是那些表面不一定彼此物理接触。键合焊盘条316的表面由诸如金、铝或其合金的可键合金属形成。在一个示例中，键合焊盘条316电连接到接地电压。导线键合连接(图3中未示出)用于将键合焊盘条316电连接到接地电压。
导线键合网包括在第一方向(大致在水平方向上)对齐并键合的第一多个键合导线306和第三多个键合导线310，在第二方向(大致在垂直方向上)对齐的第二多个键合导线308和第四多个键合导线312。从平面图上，第一方向大致垂直于第二方向。这里使用的术语“大致垂直”包括由于制造公差而发生的离90度的变化。
在一个示例中，第一306多个键合导线和第三多个键合导线310中的每个接触第二多个键合导线308和第四多个键合导线312中的每个。在另一个示例中，从管芯300的侧视图看，第一多个键合导线306和第三多个键合导线310在第二多个键合导线308和第四多个键合导线312下方。图3示出了键合导线306、308、310和312每个的五条导线用于说明目的。键合导线306、308、310和312中的每一个的数量不限于五条，并且其可以基于器件的设计要求。设计要求包括电路尺寸、管芯尺寸和电路形状。在一个示例中，键合导线306、308、310和312中的每个的数量在5-200条导线之间。在一个示例中，仅存在第一多个导线306和第二多个导线308。
多个键合导线中的每个包括铜或铜合金，因为其具有高导热系数(4.01W cm-1K-1)，接近银的最佳值，(4.29W cm-1K-1)。或者，可以使用金或金合金；金的导热系数(3.17Wcm-1K-1)小于铜的导热系数，但由于金的电化学特性更加惰性，所以金的键合性更好。取决于金导线直径，具有约1％或更少的铍、铜、钯、铁、银、钙或镁的合金可以允许更好地控制球成形中的热影响区(其对于弯曲或者其他变形应力的机械性能弱)并且增强导线的弹性。或者，多个键合导线包括铝或铝合金。在另一个例子中，铜线也可以用钯涂覆。
在一个示例中，多个键合导线306、308、310和312中的每个在一侧上具有球形键合并且在另一侧上具有针脚支撑键合(stand-off-stitch bond,SSB)。例如，键合导线306和310在管芯300的左侧(如图3所示)具有球形键合并且在右侧(如图3所示)具有针脚支撑键合。类似地，键合导线308和312在管芯300的顶侧(如图3所示)具有球形键合并且在管芯300的底侧(如图3所示)具有针脚支撑键合。在另一个例子中，多个键合导线306、308、310和312中的每个是带状导线，其具有两个带状键合，将多个带状导线中的每个连接到键合焊盘条316的两个相对端。结合图8详细说明导线键合和带状键合的过程。
第三多个键合导线310中的每个位于第一多个键合导线306中的两个之间，并且第四多个键合导线312中的每个位于第二多个键合导线306中的两个之间。如图3所示，第三多个键合导线310中的每个的长度小于第一多个键合导线306中的每个的长度。类似地，第四多个键合导线312中的每个的长度小于第二多个键合导线308中的每个的长度。注意，两个连续的球形键合(或针脚支撑键合)需要在它们之间具有最小间隙(大约5微米)，这限制了一行中的键合焊盘条316上的键合的数量。通过具有从另一组球形键合偏移的一组键合，可以将更多数量的键合导线附接到键合焊盘条316，从而增加导线键合网中的导线键合的密度。与键合导线306和308相比，偏移的导线键合是较短的导线(310和312)。最小间隙在图3中标记为两个连续球形键合之间的距离“d”。距离“d”取决于模制化合物中填料颗粒的尺寸，填料颗粒应通过导线键合网过滤。
管芯300中的一个或更多个电路314是敏感电路，其中封装内的任何应力影响电路314的性能。一个或更多个电路的示例包括数据转换器(例如，逐次逼近寄存器模数转换器、放大器、电压基准电路、电容器等)。沿着管芯外围的键合焊盘302是导电焊盘，其提供到管芯300的电连接和来自管芯300的电连接。当封装时，多个导线键合(如图5所示，第五多个导线键合)键合到管芯300的每个键合焊盘302。图3中的键合焊盘302是方形或矩形。
图4中示出具有图3的导线键合网的管芯300的三维视图。图4具有如图3中的所有组件，有相同的附图标记，因此，为了简单起见，不再对其进行说明。应注意，导线键合网的多个键合导线306、308、310和312中的每个不连接到管芯的信号或电源端子。在管芯300的操作期间，导线键合网可累积在其外围的电荷。为了避免电荷累积，键合焊盘条316电连接到接地电压。
在一个示例中，对于金导线和铜导线，多个键合导线306、308、310和312中的每个的直径在15-100微米之间。在铝导线的情况下，导线(306、308、310和312)的直径可以高达500微米。在带状导线的情况下，带状导线306、308、310和312中的每个具有6-300微米的厚度和20微米到2毫米的宽度。多个键合导线306、308、310和312中的两个连续键合导线之间的距离在5-15微米之间。
图5是根据示例的四方扁平无引脚(QFN)封装中的管芯的横截面图。QFN封装包括管芯附接焊盘502和多个引线504。管芯附接焊盘502和引线504是所谓的引线框架的部分。引线框架由基底金属片制成，该基底金属选自包括铜、铜合金、铝、铝合金、铁镍合金和KovarTM的组。对于许多器件，引线框架基底金属的平行表面被处理以产生对粘附到模制化合物的亲和力。例如，铜引线框架的表面被氧化，因为已知氧化铜表面对模制化合物表现出良好的粘附性。其他方法包括表面的等离子体处理，或者在基底金属表面上沉积其他金属的薄层。例如，对于铜引线框架，使用镀锡层。也可将镍层(约0.5至2.0μm厚)，接着是钯层(约0.01至0.1μm厚)，可选地随后是最外层的金(0.003至0.009μm厚)用于铜引线框架。应注意，其他示例可以使用具有管芯附接焊盘的其他类型的引线框架，例如具有细长引线，具有悬臂引线，或者具有在偏离引线平面的平面中具有一个或多个焊盘的框架的引线框架。或者，引线框架是由与导电层交替的绝缘材料制成的层压衬底。这些衬底可以具有适于附接一个或多个芯片的区域，以及适合于针脚键合导线的导电连接。
使用管芯附接材料503将管芯300的背侧(无源侧)附接到管芯附接焊盘502。管芯附接材料是共晶材料层，例如金-硅(Au-Si)共晶层，银-硅(Ag-Si)或有机管芯附接材料，例如环氧树脂或聚酰亚胺。管芯300经由键合导线506电连接到引线504。键合导线506由与导线键合网的多个键合导线306、308、310和312相同的材料制成，其为铜、金或铝。每个键合导线506的一端使用球形键合附接到管芯300的相应键合焊盘302，并且另一端通过针脚键合或楔形键合附接到相应的引线504。
QFN封装没有引线504延伸超出封装体。从封装的俯视图看，引线504通常为矩形。每个引线504的两侧从封装体暴露。每个引线504的一侧与封装的底侧共面。术语“共面”意味着元件位于同一平面中。然而，在制造中，由于制造的公差，在表面高度上发生一些变化。这里使用的术语“共面”是指两个元件意图在同一平面内，即使制造的一个或另一个表面中的微小差异略微在平面外。被定位成使得两个元件的表面意图位于共同平面中的元件是共面的。管芯附接焊盘502的一侧从封装的底侧暴露，用于来自QFN封装的热传递。QFN封装可通过焊料附接到印刷电路板(PCB，未示出)。
如结合图3所解释的，导线键合网附接到键合焊盘条316。由于是横截面视图，仅一根线306在水平方向上对齐。第二和第四多个导线308和312在导线306下面示出。第一多个键合导线306(和第三多个键合导线310，图5中未示出)中的每个接触第二多个键合导线308和第四多个键合导线312中的每个。在另一个示例中，第一多个键合导线306(和第三多个键合导线310)在第二多个键合导线308和第四多个键合导线312下方。
模制化合物505覆盖引线框架(502和504)、管芯300、键合焊盘条316、电路314和多个导线306、308、310和312的部分。模制化合物505包括热固性化合物。热固性化合物由环氧酚醛清漆树脂或与填料颗粒如氧化铝结合的类似材料组成。添加其他材料如促进剂、固化剂、填料和脱模剂以使模制化合物适于模制。该化合物的特征还在于低粘度和触变行为，因此当受到干扰时它表现出弱化的组成并且当静置时表现出强化的行为。由于材料的模量表征其对施加的应力(或压力)的应变响应，因此模制化合物具有顺应的机械特性。如前所述，填料颗粒具有各种尺寸，分类为大填料颗粒和小填料颗粒。
导线键合网的多个键合导线306、308、310和312的功能类似于仅使小填料颗粒(604，参见图6)穿过导线键合网的筛。小填料颗粒是指颗粒的尺寸在1-50微米之间。如图6的横截面图所示，大填料颗粒602不穿过导线键合网并停留在导线键合网的顶侧。大填料颗粒是指颗粒的尺寸大于50微米。由于大填料颗粒602保持远离QFN封装中的电路314，因此减小了由电路314上的大填料颗粒引起的任何应力。
这里使用QFN封装作为示例描述了各种示例。注意，由多个键合导线306、308、310和312形成的导线键合网可用于任何类型的半导体封装中，该半导体封装具有在管芯，该管芯在管芯的有源表面上具有键合焊盘条。
多个键合导线306、308、310和312中的每个包括两个扭结606，如图6所示。扭结是指键合导线中相对于键合导线中的先前点的弯曲或角度变化。在一个示例中，扭结的角度约为45度。请注意，由于制造公差，扭结可能会出现不同于45度的变化。扭结提高了导线键合网的高度，使得模制化合物505中的大填料颗粒602保持与半导体封装中的电路314相距一定距离。
现在参考图7，图解说明QFN封装中的管芯300的横截面图，示出了模制化合物505与管芯300的表面之间的空隙702。图7示出固化后的模制化合物505。在固化阶段之前，加热模制化合物505，使其形成粘性化合物。当模制化合物505通过模具注入时(结合图8的描述详细说明的模制过程)，它采用阻力最小的路径。导线键合网的多个键合导线306、308、310和312是具有电阻的路径，因此，模制化合物在一定程度上绕过导线键合网的区域。具有小填料颗粒的模制化合物505的一些部分可以穿过导线键合网，但是不足以覆盖导线键合网下面的区域。这在管芯300的一部分上方以及在导线键合网的多个键合导线306、308、310和312下方产生空隙702。或者，在管芯300的部分上方以及在导线键合网的多个键合导线306、308、310和312下方可存在多个空隙。这里使用的术语“空隙”是指管芯300的未填充模制化合物505的部分的上方的区域。
图8是示出根据示例的用于封装半导体管芯的方法的流程图。在步骤802，将管芯300附接到引线框架的管芯附接焊盘502。将包括多个管芯的完成的半导体晶片单个化以产生单独的管芯，在步骤802处其中一个管芯附接到管芯附接焊盘502。管芯300通过环氧基化合物附接到管芯附接焊盘。在引线框架条中可以有多个连接在一起的引线框架，并且可以在相应的管芯附接焊盘上放置多个管芯用于并行处理。引线框架条由约120至250微米厚的金属板制成。最常见的是，板由诸如铜或铜合金的基本金属制成；或者，使用铝或铁镍合金的基础金属板。生产方法包括由掩模支撑的化学蚀刻技术或冲压技术。如前所述，管芯300包括键合焊盘条316。在步骤804，第一多个键合导线306沿第一方向附接在键合焊盘条316的第一相对侧之间。在步骤806，第三多个键合导线310沿第一方向附接在键合焊盘条316的第一相对侧之间。
使用一侧上的球形键合和另一侧上的SSB来附接键合导线。球形键合过程使用热、压力和超声能量的组合以在多个键合导线306、308、310和312中的每个的一端处形成键合。球形键合过程通过将管芯300定位在加热的基座上，以将温度升高到150℃-300℃之间而开始。键合导线穿过毛细管。在键合导线的尖端处，使用火焰或火花技术产生自由空气球。球的直径约为1.2至1.6的导线直径。毛细管朝向键合焊盘条316移动，并且球压靠键合焊盘条316。对于金导线和铝焊盘，压缩力和超声能量的组合产生金-铝金属间化合物的形成，因此形成强的冶金学键合。压缩(也称为Z-或捣碎)力在约17g和75g之间；超声时间在10毫秒到20毫秒之间；并且超声功率在约20mW和50mW之间。在键合时，温度范围为150℃至270℃。在铜焊盘上的铜导线的情况下，仅发生金属相互扩散以生成强焊接。
在附接第一多个键合导线和第三多个键合导线之后，该过程前进以分别在步骤808和810处附接第二多个键合导线和第四多个键合导线。第二键合导线308和第四键合导线312沿大致垂直于第一键合导线和第二键合导线的方向附接到键合焊盘条316的第二相对侧。在步骤808和810处，毛细管沿大致垂直于第一导线键合和第二导线键合的方向移动。在步骤812，将第五多个导线键合506附接到管芯300的键合焊盘302。该步骤将管芯300电连接到封装的引线504。第五多个键合导线中的每个经由球形键合附接到相应的键合焊盘302并且经由针脚键合附接到相应的引线504。
在SSB键合中，首先使用上述技术产生球。然后毛细管移动到球并产生第二键合，其是在形成的键合表面的顶部的针脚键合。在使用带状键合的示例中，楔形键合器具有灵活性，以行进圆形导线或铝或金材料带状物。楔形键合器的深入口键合头沿着楔形工具的后部垂直地引导带状导线，并提供两个夹紧点，在夹紧点处，它可以在撕开运动期间被夹紧到键合焊盘条316。当夹具闭合时，该运动是键合头和工作台之间的受控相对运动。带状物优于圆形导线的优点是与横截面面积成比例的相对大的表面积。与2密耳的圆形导线相比，1/2×6密耳的带状物具有两倍以上的表面积，且具有几乎相同的横截面积。带状线的这种特征有效地提高了导线键合网的过滤能力，其中带状线的宽度(在20微米至2毫米之间)起到对模制化合物505中的大填料颗粒的有效阻挡的作用。与圆形导线键合相比，带状键合可以实现更低的环角度和更低的环高度，从而相比导线键合增加了带状键合的机械环稳定性。特别地，如果环相对于导线直径非常长，则环上的重力拉力设定对环稳定性的限制。
在步骤814，模制化合物505用于覆盖管芯300、键合导线(306、308、310、312和506)以及引线框架的部分。一些模制方法包括传递模制、腔体直接注模和液体压缩模制。例如，传递模制方法包括在模压机中液化和传递粒化的模制化合物。液化导致低粘度材料，其易于流入模腔并完全覆盖该器件。在传递到模腔中的过程后不久，固化反应开始并且模制化合物505的粘度增加直到树脂系统硬化。在烘箱中在模具外部进行另外的固化周期，以确保模制化合物505完全固化。模制化合物505在机械和环境方面保护QFN封装免受外部环境的影响。在模制之后，使用机械锯将模制的引线框架条单个化以分离各个QFN封装。
在权利要求的范围内，所描述的实施例中的修改是可能的，并且其他实施例也是可能的。

Claims (20)

1.一种半导体封装，包括：
引线框架，其包括管芯附连焊盘和多个引线；
附接到所述管芯附接焊盘并电连接到所述多个引线的管芯，所述管芯包括沿所述管芯的外围的多个键合焊盘和围绕所述管芯中的电路的键合焊盘条；
第一多个键合导线，键合在所述键合焊盘条的第一相对侧之间，所述第一多个键合导线沿第一方向对齐；
第二多个键合导线，键合在所述键合焊盘条的第二相对侧之间，所述第二多个键合导线沿第二方向对齐；和
模制化合物，其覆盖所述引线框架、所述管芯、所述键合焊盘条、所述第一多个键合导线和所述第二多个键合导线的部分。
2.根据权利要求1所述的半导体封装，还包括：
第三多个键合导线，键合在所述键合焊盘条的第一相对侧之间，所述第三多个键合导线沿所述第一方向对齐；和
第四多个键合导线，键合在所述键合焊盘条的第二相对侧之间，所述第四多个键合导线沿所述第一方向对齐，其中所述模制化合物覆盖所述第三多个键合导线和所述第四多个键合导线的部分。
3.根据权利要求2所述的半导体封装，其中：
所述第三多个键合导线的长度小于所述第一多个键合导线的长度；和
所述第四多个键合导线的长度小于所述第二多个键合导线的长度。
4.根据权利要求1所述的半导体封装，其中所述键合焊盘条位于所述管芯的有源表面上。
5.根据权利要求1所述的半导体封装，还包括第五多个键合导线，所述第五多个键合导线将所述管芯电连接到所述多个引线。
6.根据权利要求5所述的半导体封装，其中所述第一键合导线、所述第二键合导线、所述第三键合导线、所述第四键合导线和所述第五多个键合导线中的每个包括铜和金中的至少一种。
7.根据权利要求2所述的半导体封装，其中：
所述第一多个键合导线和所述第三多个键合导线中的每个包括在所述第一相对侧的一侧上的球形键合和在所述第一相对侧的另一侧上的针脚支撑键合；所述第二多个键合导线和所述第四多个键合导线中的每个包括在所述第二相对侧的一侧上的球形键合和在所述第二相对侧的另一侧上的针脚支撑键合。
8.根据权利要求2所述的半导体封装，其中：
所述第一键合导线、所述第二键合导线、所述第三键合导线和所述第四键合导线中的每个包括带状线，所述带状线的两端通过带状键合附接到所述键合焊盘条。
9.根据权利要求1所述的半导体封装，还包括所述管芯中的所述电路和所述模制化合物之间的空隙。
10.根据权利要求2所述的半导体封装，其中所述第一键合导线、所述第二键合导线、所述第三键合导线和所述第四键合导线中的每个包括至少两个纽结。
11.根据权利要求2所述的半导体封装，其中所述第二方向大致垂直于所述第一方向。
12.根据权利要求2所述的半导体封装，其中所述第一多个键合导线和所述第三多个键合导线中的每个接触所述第二多个键合导线和所述第四多个键合导线中的每个。
13.根据权利要求2所述的半导体封装，其中所述第一多个键合导线和所述第三多个键合导线位于所述第二多个键合导线和所述第四多个键合导线下方。
14.根据权利要求1所述的半导体封装，其中：
所述第一多个键合导线、所述第二多个键合导线、所述第三多个键合导线和所述第四多个键合导线未连接到所述管芯的信号或电源端子；和
所述键合焊盘条电连接到接地电压。
15.一种半导体封装，包括：
管芯，其包括沿所述管芯的外围的多个键合焊盘和围绕所述管芯中的电路的键合焊盘条；
第一多个键合导线，键合在所述键合焊盘条的第一相对侧之间，所述第一多个键合导线沿第一方向对齐；
第二多个键合导线，键合在所述键合焊盘条的第二相对侧之间，所述第二多个键合导线沿第二方向对齐；和
模制化合物，其覆盖所述引线框架、所述管芯、所述键合焊盘条、所述第一多个键合导线和所述第二多个键合导线的部分。
16.根据权利要求15所述的半导体封装，还包括：
第三多个键合导线，键合在所述键合焊盘条的第一相对侧之间，所述第三多个键合导线沿所述第一方向对齐；和
第四多个键合导线，键合在所述键合焊盘条的第二相对侧之间，所述第四多个键合导线沿所述第一方向对齐，其中所述模制化合物覆盖所述第三多个键合导线和所述第四多个键合导线的部分。
17.根据权利要求15所述的半导体封装，还包括所述管芯中的电路和所述模制化合物之间的空隙。
18.一种封装半导体芯片的方法，包括：
将管芯附接到引线框架的管芯附接焊盘上；
将第一多个键合导线沿第一方向连接在键合焊盘条的第一相对侧之间，所述键合焊盘条位于所述管芯的表面上并围绕所述管芯中的电路；
在所述键合焊盘条的第二相对侧之间沿第二方向附接第二多个键合导线；
将所述管芯电连接到所述引线框架的多个引线；和
使用模制化合物覆盖所述管芯、所述第一多个键合导线和所述第二多个键合导线以及所述引线框架的部分。
19.根据权利要求18所述的方法，还包括：在附接所述第二多个键合导线之前，在所述键合焊盘条的所述第一相对侧之间沿所述第一方向附接第一多个键合导线，所述第三多个键合导线的长度小于所述第一多个键合导线的长度。
20.根据权利要求18所述的方法，还包括：在所述键合焊盘条的所述第二相对侧之间沿所述第二方向附接第四多个键合导线，所述第四多个键合导线的长度小于所述第二多个键合导线的长度。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10446414B2 (en) 2017-12-22 2019-10-15 Texas Instruments Incorporated Semiconductor package with filler particles in a mold compound
JP7070373B2 (ja) * 2018-11-28 2022-05-18 三菱電機株式会社 半導体装置の製造方法、半導体装置、電力変換装置
JP7098052B2 (ja) * 2019-04-05 2022-07-08 三菱電機株式会社 半導体装置およびその製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050040501A1 (en) * 2003-08-20 2005-02-24 Hagen Deborah A. Wirebonded assemblage method and apparatus
CN101697348A (zh) * 2009-10-11 2010-04-21 天水华天科技股份有限公司 一种小载体四面扁平无引脚封装件及其制备方法
US8012868B1 (en) * 2008-12-15 2011-09-06 Amkor Technology Inc Semiconductor device having EMI shielding and method therefor
US9508658B1 (en) * 2015-08-05 2016-11-29 Macom Technology Solutions Holdings, Inc. Electromagnetic wall in millimeter-wave cavity

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5309321A (en) 1992-09-22 1994-05-03 Microelectronics And Computer Technology Corporation Thermally conductive screen mesh for encapsulated integrated circuit packages
US5723906A (en) * 1996-06-07 1998-03-03 Hewlett-Packard Company High-density wirebond chip interconnect for multi-chip modules
US5960307A (en) * 1996-11-27 1999-09-28 Texas Instruments Incorporated Method of forming ball grid array contacts
US5927193A (en) * 1997-10-16 1999-07-27 International Business Machines Corporation Process for via fill
KR100595317B1 (ko) 2000-07-11 2006-07-03 앰코 테크놀로지 코리아 주식회사 반도체 패키지
JP2002076229A (ja) * 2000-07-13 2002-03-15 Texas Instruments Inc 銀めっきを含む半導体のリードフレームおよびその製造方法
US6770963B1 (en) * 2001-01-04 2004-08-03 Broadcom Corporation Multi-power ring chip scale package for system level integration
KR100403619B1 (ko) * 2001-02-21 2003-10-30 삼성전자주식회사 열적/기계적 스트레스에 저항성이 강한 반도체 소자의 본드패드 및 그 형성방법
US7739624B2 (en) 2002-07-29 2010-06-15 Synopsys, Inc. Methods and apparatuses to generate a shielding mesh for integrated circuit devices
CN1774959A (zh) 2003-04-15 2006-05-17 波零公司 用于印刷电路板的电磁干扰屏蔽
TWI376756B (en) * 2003-07-30 2012-11-11 Taiwan Semiconductor Mfg Ground arch for wirebond ball grid arrays
US20050278936A1 (en) * 2004-06-18 2005-12-22 Nikolaus Schunk Optoelectronic apparatus with a shielding cage, and methods for production of an optoelectronic apparatus with a shielding cage.
WO2006131776A1 (en) 2005-06-10 2006-12-14 Infineon Technologies Ag Leadframe, semiconductor package and methods of producing the same
JP2009032906A (ja) 2007-07-27 2009-02-12 Seiko Instruments Inc 半導体装置パッケージ
US20090072373A1 (en) * 2007-09-14 2009-03-19 Reynaldo Corpuz Javier Packaged integrated circuits and methods to form a stacked integrated circuit package
US20100149773A1 (en) * 2008-12-17 2010-06-17 Mohd Hanafi Mohd Said Integrated circuit packages having shared die-to-die contacts and methods to manufacture the same
KR101737053B1 (ko) * 2010-12-31 2017-05-18 삼성전자주식회사 반도체 패키지
US8686547B1 (en) * 2011-01-03 2014-04-01 Marvell International Ltd. Stack die structure for stress reduction and facilitation of electromagnetic shielding
US9147628B2 (en) * 2012-06-27 2015-09-29 Infineon Technoloiges Austria AG Package-in-packages and methods of formation thereof
US9240390B2 (en) * 2013-06-27 2016-01-19 Freescale Semiconductor, Inc. Semiconductor packages having wire bond wall to reduce coupling
US8981541B2 (en) * 2013-07-10 2015-03-17 Freescale Semiconductor, Inc. Quad flat semiconductor device with additional contacts
CN104576590A (zh) * 2013-10-09 2015-04-29 飞思卡尔半导体公司 具有附加的底面接触件的表面安装半导体装置
US9305898B2 (en) * 2014-01-23 2016-04-05 Freescale Semiconductor, Inc. Semiconductor device with combined power and ground ring structure
US9704785B2 (en) * 2015-01-14 2017-07-11 Mediatek Inc. Semiconductor package with die paddle
EP3403279A4 (en) * 2016-01-11 2019-09-11 INTEL Corporation MULTICHIP HOUSING WITH MULTIPLE THERMAL INTERMEDIATES
KR101815754B1 (ko) * 2016-03-10 2018-01-08 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
WO2017171859A1 (en) * 2016-04-01 2017-10-05 Intel Corporation Semiconductor package with electromagnetic interference shielding structures

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050040501A1 (en) * 2003-08-20 2005-02-24 Hagen Deborah A. Wirebonded assemblage method and apparatus
US8012868B1 (en) * 2008-12-15 2011-09-06 Amkor Technology Inc Semiconductor device having EMI shielding and method therefor
CN101697348A (zh) * 2009-10-11 2010-04-21 天水华天科技股份有限公司 一种小载体四面扁平无引脚封装件及其制备方法
US9508658B1 (en) * 2015-08-05 2016-11-29 Macom Technology Solutions Holdings, Inc. Electromagnetic wall in millimeter-wave cavity

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