CN110277309A - 用于半导体制程的方法 - Google Patents
用于半导体制程的方法 Download PDFInfo
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- CN110277309A CN110277309A CN201811480549.XA CN201811480549A CN110277309A CN 110277309 A CN110277309 A CN 110277309A CN 201811480549 A CN201811480549 A CN 201811480549A CN 110277309 A CN110277309 A CN 110277309A
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- High Energy & Nuclear Physics (AREA)
- Chemical Kinetics & Catalysis (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
此处所述的实施例一般关于在半导体制程中,用于图案化结构的遮罩其形成方法。在一实施例中,形成介电层于基板上。形成遮罩于介电层上。形成遮罩的步骤包括沉积第一层于介电层上;在第一布植制程中以第一能量将掺质物种布植穿过图案化材料至第一层中;在第一布植制程之后,在第二布植制程中以第二能量将掺质物种布植穿过图案化材料至第一层中,且第二能量大于第一能量;以及形成遮罩的遮罩部分,包括选择性移除第一层其未布植掺质物种的部分。
Description
技术领域
本发明实施例关于半导体制程,更特别关于在半导体制程中形成遮罩以用于图案化结构的方法。
背景技术
集成电路产业已经历快速成长。集成电路设计与材料的技术进展,使每一代的集成电路比前一代的集成电路具有更小且更复杂的电路。在集成电路的演进中,功能密度(比如单位芯片面积所含的内连线装置数目)通常随着几何尺寸(比如制程所能产生的最小构件或线路)缩小而增加。
制程的尺寸缩小通常有利于增加产能并降低相关成本。尺寸缩小亦增加集成电路制程的复杂度。为实现上述进展,集成电路制程亦需类似发展。上述进展的领域之一为制作遮罩。虽然制作集成电路装置的现有方法一般可适用于其发展目的,但仍无法完全适用于所有方面。举例来说,较大世代中集成电路内的结构变异其容忍度,可能无法被较新且较小的世代接受。
发明内容
本发明一实施例提供的用于半导体制程的方法,包括:形成介电层于基板上;以及形成遮罩于介电层上,且形成遮罩的步骤包括:沉积第一层于介电层上;在第一布植制程中以第一能量将掺质物种布植穿过图案化材料至第一层中;在第一布植制程之后,在第二布植制程中以第二能量将掺质物种布植穿过图案化材料至第一层中,且第二能量大于第一能量;以及形成遮罩的遮罩部分,包括选择性移除第一层其未布植掺质物种的部分。
附图说明
图1至图16是一些实施例中,在进行半导体制程用以图案化的例示性方法时的个别中间结构的剖视图。
图17和图18是一些实施例中,显示形成遮罩部分时的一些损失效应的个别中间结构的剖视图。
附图标记说明:
D1 第一深度
D2 第二深度
HL 水平损失
VL 垂直损失
50 半导体基板
52 第一介电层
54、150 导电结构
56 第二介电层
58 第一遮罩子层
60 第二遮罩子层
62 第三遮罩子层
64、100 底层
66、102 中间层
68、104 光刻胶
80、110 低能量布植
82、94、98、112、124、128 掺杂区
90、120 第一高能量斜向布植
92 垂直线
96、126 第二高能量斜向布植
140 遮罩部分
200、200’ 侧壁
202、204 横向边缘
具体实施方式
下述公开内容提供许多不同实施例或实例以实施本发明的不同结构。下述特定构件与排列的实施例用以简化本发明而非局限本发明。举例来说,形成第一构件于第二构件上的叙述包含两者直接接触,或两者之间隔有其他额外构件而非直接接触。此外,本发明的多个实例可采用重复标号及/或符号使说明简化及明确,但这些重复不代表多种实施例中相同标号的元件之间具有相同的对应关系。
此外,空间性的相对用语如“下方”、“其下”、“较下方”、“上方”、“较上方”、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件,而非局限于图示方向。元件亦可转动90°或其他角度,因此方向性用语仅用以说明图示中的方向。
此处所述的实施例一般关于形成遮罩,以在半导体制程中图案化结构的一或多个方法。一般而言,可将掺质物种布植至层状物,以改变层状物的蚀刻选择性。布植并选择性地蚀刻层状物,可移除层状物的未布植(如未掺杂)部分,以形成具有图案的遮罩部分,且图案之后将转移至一或多个其他层状物。布植掺质物种的方法可包含两个布植制程。第一布植制程可低能量地布植掺质物种,而后续的第二布植制程可高能量地布植掺质物种。据信在高能量布植之前进行低能量布植,可让高能量布植的掺质物种优选地限制在目标区中,并使布植区域的侧壁更垂直。在选择性移除未布植区的蚀刻制程之后,布植区其更垂直的侧壁可让保留的布植区具有较小的尺寸变异。上述步骤亦可具有其他优点。
此处所述的一些实施例其内容为末段制程。其他实施例的范围中,其他制程与结构的内容可为中段制程或其他内容。公开的实施例说明各种调整,然而对实施例进行的其他调整亦属本发明范围。本技术领域中技术人员应理解其他调整属于其他实施例的范围。虽然以特定顺序描述方法的实施例,但其他方法的实施例可由任何逻辑性的顺序执行,并可包含比此处描述的步骤更少或更多的步骤。
图1至图16是一些实施例中,在进行半导体制程用以图案化的例示性方法时的个别中间结构的剖视图。如图1所示,第一介电层52位于半导体基板50上。半导体基板50可为或可包含基体半导体、绝缘层上半导体基板、或类似物,且其可未掺杂或掺杂p型或n型掺质。在一些实施例中,半导体基板50的半导体材料可包含半导体元素如硅或锗、半导体化合物、半导体合金、或上述的组合。
多种装置可位于半导体基板50之上及/或之中。举例来说,半导体基板50可包含场效晶体管(如鳍状场效晶体管、平面场效晶体管、垂直全绕式栅极场效晶体管、或类似物)、二极管、电容、电感、或其他装置。举例来说,装置可完全形成于半导体基板50中、形成于半导体基板50的部分与一或多个上方层状物中、及/或完全形成于一或多个上方层状物中。此处所述的制程可用于形成装置及/或使装置内连线,以形成集成电路。集成电路可为电路如特定应用集成电路、处理器、存储器、或其他电路。
第一介电层52位于半导体基板50上。第一介电层52可直接位于半导体基板50上,或者任何数目的其他层状物可夹设于第一介电层52与半导体基板50之间。举例来说,第一介电层52可为或可包括层间介电层或金属间介电层。举例来说,第一介电层52可为或可包括低介电常数介电层,其介电常数低于约4.0。在一些实施例中,第一介电层52包含磷硅酸盐玻璃、硼磷硅酸盐玻璃、氟化硅酸盐玻璃、碳氧化硅、旋转涂布玻璃、旋转涂布聚合物、碳硅材料、上述的化合物、上述的复合物、或上述的组合。
导电结构54可位于第一介电层52中及/或穿过第一介电层52。导电结构54可为或可包含晶体管的栅极结构、连接至晶体管的栅极结构及/或源极/漏极区的接点插塞、导电线路、及/或导电通孔。举例来说,第一介电层52可包含层间介电层,而导电结构54可包含层间介电层中的栅极(如钨、钴、或类似物),且栅极的形成方法可采用置换栅极制程。在另一例中,第一介电层52可为层间介电层,而导电结构54可包含接点插塞。举例来说,接点插塞的形成方法可为形成开口穿过层间介电层,以达形成于半导体基板50上的晶体管其栅极及/或源极/漏极区。接点插塞可包含粘着层(如钛或类似物)、粘着层上的阻障层(如氮化钛或类似物)、与阻障层上的导电充填材料(如钨、钴、或类似物)。在又一例中,第一介电层52可为金属间介电层,而导电结构54可包含导电线路及/或导电通孔(可一并或个别地称作内连线结构)。举例来说,内连线结构的形成方法可采用镶嵌制程形成开口及/或凹陷穿过金属间介电层,及/或形成开口或/或凹陷于金属间介电层中。
第一介电层52与导电结构54的描述方式,说明此处所述的方法其多种应用。在其他例子中,导电结构54可为半导体基板50中的掺杂区如场效晶体管的源极/漏极区,因此导电结构54位于半导体基板50中而可省略第一介电层52。此处所述的方法可用于图案化任何结构。
第二介电层56位于第一介电层52与导电结构54上。举例来说,第二介电层56可为或可包含层间介电层或金属间介电层。第二介电层56沉积于第一介电层52与导电结构54的上表面上。举例来说,第二介电层56可为或可包含低介电常数介电层,其介电常数低于约4.0。在一些例子中,第二介电层56包含磷硅酸盐玻璃、硼磷硅酸盐玻璃、氟化硅酸盐玻璃、碳氧化硅、旋转涂布玻璃、旋转涂布聚合物、碳硅材料、上述的化合物、上述的复合物、或上述的组合。第二介电层56的沉积方法可采用化学气相沉积如等离子体增强化学气相沉积或可流动的化学气相沉积、旋转涂布、或另一沉积技术。在一些例子中,可进行化学机械研磨或另一平坦化制程以平坦化第二介电层56的上表面。虽然未图示,蚀刻停止层可位于第一介电层52与导电结构54上,并位于第二介电层56下。
遮罩堆叠位于第二介电层56上。遮罩堆叠包含第一遮罩子层58、第二遮罩子层60、与第三遮罩子层62。在其他实施例中,遮罩堆叠可为或可包括单一或任何数目的其他层。第一遮罩子层58位于第二介电层56上。第二遮罩子层60位于第一遮罩子层58上。第三遮罩子层62位于第二遮罩子层60上。
第一遮罩子层58可为或可包含氮化物层,比如氮化钛、氮化硅、氮化钽、类似物、或上述的组合,且其形成方法可采用化学气相沉积、物理气相沉积、原子层沉积、或另一沉积技术。举例来说,第一遮罩子层58的厚度可介于约20nm至约50nm之间。
第二遮罩子层60可为或可包括等离子体增强化学气相沉积的氧化物(如等离子体增强氧化物)。在一些例子中,第二遮罩子层60可为抗反射涂层,比如无氮的抗反射涂层(例如富硅氧化物)或类似物。在其他例子中,第二遮罩子层60可为另一材料,且其形成方法可采用化学气相沉积、物理气相沉积、原子层沉积、或另一沉积技术。举例来说,第二遮罩子层60的厚度可介于约10nm至约50nm之间。
第三遮罩子层62可为或可包含硅层如非晶硅层、类似物、或上述的组合。第三遮罩子层62的形成方法可采用化学气相沉积、物理气相沉积、原子层沉积、或另一沉积技术。举例来说,第三遮罩子层62的厚度可介于约20nm至约50nm之间,比如约25nm。
底层64(如牺牲层)位于第三遮罩子层62上。底层64可为或可包含硬遮罩材料如含碳材料,且其形成方法可采用旋转涂布、化学气相沉积、物理气相沉积、原子层沉积、或另一沉积技术。在一例中,底层64为聚合物材料如氧化物,其形成方法可为旋转涂布。在一些例子中,可在沉积底层64后平坦化底层64,且平坦化方法可为化学机械研磨或另一平坦化制程。举例来说,底层64的厚度可介于约20nm至约150nm之间。
中间层66(如牺牲层)位于底层64上。中间层66可为或可包含另一遮罩材料如含碳材料(比如碳氧化硅),且其形成方法可采用化学气相沉积、物理气相沉积、原子层沉积、或另一沉积技术。在一例中,中间层66为碳氧化硅。举例来说,中间层66的厚度可介于约10nm至约40nm之间。
光刻胶68位于中间层66上,其形成方法可采用旋转涂布。光刻胶68的图案化方法可为采用合适光罩,并以穿过光罩的光曝光光刻胶68。接着可移除光刻胶68的曝光部分或未曝光部分,端视光刻胶68为正光刻胶或负光刻胶。光刻胶68被移除部分的区域将露出中间层66的对应部分,即之后形成硬遮罩处。
如图2所示,将图案化的光刻胶68的图案转移至中间层66与底层64。转移光刻胶68的图案的方法,可采用蚀刻制程如干(等离子体)蚀刻制程,其可为非等向。蚀刻制程可为反应性离子蚀刻、中性束蚀刻、类似方法、或另一蚀刻制程。将图案化的光刻胶68的图案转移至中间层66与底层64,可自中间层66与底层64露出第三遮罩子层62的区域,而第三遮罩子层62的露出区域对应图案化的光刻胶68之前露出的中间层66的区域。在蚀刻制程之后可移除任何残留的光刻胶68,且移除方法可为灰化制程。
如图3所示,进行低能量布植80以形成掺杂区82于第三遮罩子层62中。对自中间层66与底层64露出的第三遮罩子层62进行布植,可形成掺杂区82于第三遮罩子层62中。低能量布植80所布植的物种,可限制后续高能量布植所布植的至少一些物种,如下所述。物种可进一步改变掺杂区82(即布植物种处)中的第三遮罩子层62其材料性质,比如改变后续蚀刻制程对掺杂区82的蚀刻速率(相对于后续蚀刻制程对第三遮罩子层62其未掺杂区部分的蚀刻速率)。
在一些例子中,低能量布植80布植物种的能量等于或小于约5keV,比如介于约1keV至约5keV之间。在一些例子中,低能量布植80布植物种所形成的掺杂区82,其第一深度D1可介于约3nm至约4nm之间。在一些例子中,低能量布植80所掺杂的掺杂区82其掺杂浓度大于约1×1020cm-3,比如介于约1×1020cm-3至5×1020cm-3之间,特别为约3×1020cm-3。在一些例子中,低能量布植80所布植的物种包含硼如二氟化硼。在其他例子中,可实施或采用不同的能量、深度、浓度、或物种。
如图4和图5所示,进行互补的第一高能量斜向布植90与第二高能量斜向布植96,以分别形成掺杂区94与98于第三遮罩子层62中。图4中的第一高能量斜向布植90相对于垂直线92(与半导体基板50的主要平面垂直)具有第一倾斜角度,而图5中的第二高能量斜向布植96相对于垂直线92具有第二倾斜角度,且第一倾斜角度与第二倾斜角度互补。在一些例子中,第一倾斜角与第二倾斜角可介于约-20°至约20°之间。举例来说,第一倾斜角度可为8°,而第二倾斜角度可为-8°。
对自中间层66与底层64露出的第三遮罩子层62的区域进行图4中的第一高能量斜向布植90,可形成掺杂区94于第三遮罩子层62中。掺杂区94的形成方法,可为布植物种穿过图3的低能量布植所形成的掺杂区82,及/或布植物种至图3的低能量布植所形成的掺杂区82中。因此掺杂区94可与掺杂区82重叠(至少部分重叠)。
对自中间层66与底层64露出的第三遮罩子层62的区域进行图5中的第二高能量斜向布植96,可类似地形成掺杂区98于第三遮罩子层62中。掺杂区98的形成方法,可为布植物种穿过图3的低能量布植所形成的掺杂区82,及/或布植物种至图3的低能量布植所形成的掺杂区82中,并位于图4的第一高能量斜向布植90形成的掺杂区94的至少部分中。因此掺杂区98可与掺杂区82重叠(至少部分重叠),并包含掺杂区94。
第一高能量斜向布植90与第二高能量斜向布植96所布植的物种,可改变掺杂区98(即布植物种处)中的第三遮罩子层62其材料性质,比如改变后续蚀刻制程对掺杂区98的蚀刻速率(相对于后续蚀刻制程对第三遮罩子层62其未掺杂区部分的蚀刻速率)。
在一些例子中,第一高能量斜向布植90与第二高能量斜向布植96其布植物种的能量各自等于或大于约10keV,比如介于约10keV至约25keV之间(如约18keV)。第一高能量斜向布植90与第二高能量斜向布植96的能量,各自大于低能量布植80的能量。在一些例子中,第一高能量斜向布植90与第二高能量斜向布植96布植物种以形成的掺杂区98,其第二深度D2可介于约20nm至约50nm之间。第二深度D2可大于第一深度D1。第二深度D2可等于或小于第三遮罩子层62的厚度。在一些例子中,第一高能量斜向布植90与第二高能量斜向布植96掺杂的掺杂区98,其掺杂浓度大于或等于约1×1019cm-3,比如介于约1×1019cm-3至约1×1020cm-3之间,特别为约5×1019cm-3。在一些例子中,掺杂区98其掺杂浓度可小于、等于、或大于低能量布植80所形成的掺杂区82其掺杂浓度。在一些特定例子中,掺杂区98其掺杂浓度小于低能量布植80所形成的掺杂区82其掺杂浓度。在一些例子中,第一高能量斜向布植90与第二高能量斜向布植96所布植的物种含硼,比如二氟化硼。在其他例子中,可实施或采用不同能量、深度、浓度、或物种。
在第一高能量斜向布植90与第二高能量斜向布制96之前实施低能量布植80,可将第一高能量斜向布植90与第二高能量斜向布制96所布植的物种,限制在第一高能量斜向布植90与第二高能量斜向布制96时自中间层66与底层64露出的第三遮罩子层62的表面下方的第三遮罩子层62的区域中。通过更精准地限制布植物种至此区域,掺杂区98的侧壁可更垂直,进而减少遮罩的尺寸变异,如下所述。由本发明的实际研究可知,若无低能量布植80,则第一高能量斜向布植90与第二高能量斜向布植96所布植的物种会发生散射;而低能量布植可减少上述物种散射的问题。据信上述散射会造成侧壁轮廓的明显变异,即造成遮罩尺寸的明显变异。
如图6所示,移除中间层66与底层64。举例来说,中间层66与底层64的移除方法可为一或多道蚀刻制程,其对中间层66与底层64的材料具有选择性。
图7至图12所示的制程与图1至图6所示的制程类似,可形成另一掺杂区于第三遮罩子层62中。通过重复此制程以形成第三遮罩子层62的另一区,可缩小后续形成的遮罩所形成的结构之间的间距。可重复任意次数的制程,使后续形成的遮罩具有任何图案。此重复制程可称作多重图案化,比如双重图案化。一些例子并未重复制程,即省略图7至图12所示的制程。
如图7所示,形成底层100于具有掺杂区82与98的第三遮罩子层62上,形成中间层102于底层100上,并形成图案化的光刻胶104于中间层102上。底层100、中间层102、与图案化的光刻胶104的材料与形成制程,可分别与图1所示的底层64、中间层66、与图案化的光刻胶68的材料与形成制程相同或类似。移除光刻胶104其部分的区域将露出中间层102的对应部分,即之后形成硬遮罩处。
如图8所示,将图案化的光刻胶104的图案转移至中间层102与底层100。转移图案的方法,可如图2所示的上述内容。将图案化的光刻胶104的图案转移至中间层102与底层100,可自中间层102与底层100露出第三遮罩子层62的区域,而第三遮罩子层62的露出区域对应图案化的光刻胶104露出的中间层102的区域。之后可移除任何保留的光刻胶104。
如图9所示,进行低能量布植110以形成掺杂区112于第三遮罩子层62中。经由自中间层102与底层100露出的第三遮罩子层62的区域,可形成掺杂区112于第三遮罩子层62中。低能量布植110可与图3的低能量布植80相同或类似,因此省略相关内容以简化说明。图9的低能量布植110所布植的物种,可与图3的低能量布植80所布植的物种相同。
如图10和图11所示,进行互补的第一高能量斜向布植120与第二高能量斜向布植126,以分别形成掺杂区124与128于第三遮罩子层62中。对自中间层102与底层100露出的第三遮罩子层62的区域进行图10的第一高能量斜向布植120,可形成掺杂区124于第三遮罩子层62中。掺杂区124的形成方法,可为布植物种穿过图9的低能量布植所形成的掺杂区112,及/或布植物种至图9的低能量布植所形成的掺杂区112中。因此掺杂区124可与掺杂区112重叠(至少部分重叠)。对自中间层102与底层100露出的第三遮罩子层62的区域进行图11的第二高能量斜向布植126,可类似地形成掺杂区128于第三遮罩子层62中。掺杂区128的形成方法,可为布植物种穿过图9的低能量布植所形成的掺杂区112,及/或布植物种至图9的低能量布植所形成的掺杂区112中,并位于图10的第一高能量斜向布植120形成的掺杂区124的至少部分中。因此掺杂区128可与掺杂区112重叠(至少部分重叠)并包含掺杂区124。第一高能量斜向布植120与第二高能量斜向布植126可分别与图4和图5中的第一高能量斜向布植90与第二高能量斜向布植96相同或类似,因此省略相关叙述以简化说明。图10的第一高能量斜向布植120与图11的第二高能量斜向布植126所布植的物种,可分别与图4的第一高能量斜向布植90与图5的第二高能量斜向布植96所布植的物种相同。
如图12所示,移除中间层102与底层100。举例来说,中间层102与底层100的移除方法可为一或多道蚀刻制程,其对中间层102与底层100的材料具有选择性。
如图13所示,移除第三遮罩子层62的未掺杂部分,以形成遮罩部分140。进行蚀刻制程,其选择性地蚀刻第三遮罩子层62的未掺杂部分的速率,大于蚀刻掺杂区82、98、112、与128的速率。上述蚀刻制程可移除第三遮罩子层62的未掺杂部分,并保留对应掺杂区82、98、112、与128的遮罩部分140。蚀刻制程可能导致掺杂区82、98、112、与128的一些损失,因为蚀刻制程可能蚀刻这些掺杂区(尽管这些掺杂区的蚀刻速率低)。在一些例子中,蚀刻制程为湿蚀刻,其可为等向。在一些例子中,湿蚀刻包含的溶液含氢氧化铵稀释于去离子水中。氢氧化铵与去离子水的重量比可介于约1:1至约1:1000之间。在蚀刻制程中,含氢氧化铵溶液的温度可介于约25℃至约100℃之间。采用含氢氧化铵溶液的蚀刻制程,可历时约60秒至约600秒之间。亦可实施其他制程以移除第三遮罩子层62的未掺杂部分,并形成遮罩部分140。
如图14所示,将遮罩部分140的图案转移至第二遮罩子层60与第一遮罩子层58。图案化的第二遮罩子层60与第一遮罩子层58形成的遮罩,可用于后续图案化第二介电层56的步骤。将图案转移至第二遮罩子层60与第一遮罩子层58的方法,可采用一或多道合适的蚀刻制程,比如非等向(例如干等离子体)蚀刻制程。非等向蚀刻制程的例子包含反应性离子蚀刻、中性束蚀刻、类似方法、或另一蚀刻制程。如图14所示,移除遮罩部分140。在转移图案时可消耗遮罩部分140,及/或在后续蚀刻中可移除遮罩部分140。
如图15所示,采用第二遮罩子层60与第一遮罩子层58以图案化第二介电层56。图案化第二介电层56的方法可采用一或多道合适的蚀刻制程,比如非等向蚀刻制程。例示性的非等向蚀刻制程包含反应性离子蚀刻、中性束蚀刻、类似方法、或另一蚀刻制程。如图15所示,可在此图案化步骤中消耗第二遮罩子层60,及/或可在后续蚀刻步骤中移除第二遮罩子层60。
如图16所示,形成导电结构150于图案化的第二介电层56中,并移除第一遮罩子层58。举例来说,导电结构150可包含金属充填材料于第二介电层56中的开口或凹陷中。开口或凹陷的形成方法可为图案化第二介电层56,如图15所示。例示性的金属充填材料可包含钴、钨、铜、铝、钌、类似物、或上述的组合。导电结构150亦可包含沿着第二介电层56的开口侧壁的阻障层,比如位于第二介电层56与金属充填材料之间的阻障层。阻障层可为或可包含氮化钛、氮化钽、类似物、或上述的组合。导电结构150的材料其沉积方法可采用任何合适的沉积制程。平坦化制程如化学机械研磨可移除导电材料150与第一遮罩子层58的多余材料,使导电结构150的上表面与第二介电层56的上表面齐平。导电结构150可称作接点、通孔、线路、垫、或类似物。
图17和图18显示一些实施例中,形成遮罩部分140时的一些损失效应。图17显示图6中形成的掺杂区82与98。图17亦可表示图12中形成的掺杂区112与128。图18表示图13中形成的遮罩部分140。
在图17中,掺杂区82与98具有侧壁200,且侧壁200具有横向边缘202。横向边缘202为掺杂区82与98的横向边界,并沿着侧壁200。本技术领域中技术人员应理解,掺质浓度可由掺杂区82与98朝向第三遮罩子层62的未掺杂部分渐变。侧壁200沿着掺杂区82与98的边界,而掺质浓度在侧壁200处降低,可选择性移除第三遮罩子层62在边界之外的部分(如第三遮罩子层62的未掺杂部分),并保留掺杂区82与98的至少部分以作为遮罩部分140。举例来说,当布植至掺杂区82与98的物种为二氟化硼,且第三遮罩子层62为非晶硅时,移除第三遮罩子层62的未掺杂部分的蚀刻制程可为采用稀氢氧化铵的湿蚀刻制程,而侧壁200可定义为沿着掺质渐变的位置,即掺质浓度转变为低于约1×1019cm-3处,其可让第三遮罩子层62的部分的掺质浓度低于稀氢氧化铵可选择性移除的浓度。如此一来,掺杂区82与98可各自具有大于约1×1019cm-3的浓度。
在图18中,在移除第三遮罩子层62的未掺杂部分以形成遮罩部分140之后,遮罩部分140具有侧壁200’,且侧壁200’具有横向边缘204。如图所示,在移除第三遮罩子层62的未掺杂部分时,比如移除第三遮罩子层62的蚀刻制程中,会造成垂直损失VL。垂直损失VL可能导致水平损失HL,其对应横向边缘202与204之间的横向差异。
在高能量斜向布植前实施低能量布植,可让高能量斜向布植的物种限制在高能量布植时露出的第三遮罩子层62的表面下方的第三遮罩子层62的区域中。更精准地限制布植物种于上述区域,可让掺杂区98的侧壁200更垂直。在发生垂直损失VL时,更垂直的侧壁200可减少遮罩部分140的水平损失HL。如此一来,制程(如用以形成导电结构150)的关键尺寸可更精准。此处所述的一些实施例可实施于任何技术节点,特别是进阶的技术节点。
一实施例为用于半导体制程的方法。形成介电层于基板上。形成遮罩于介电层上。形成遮罩的步骤包括沉积第一层于介电层上;在第一布植制程中以第一能量将掺质物种布植穿过图案化材料至第一层中;在第一布植制程之后,在第二布植制程中以第二能量将掺质物种布植穿过图案化材料至第一层中,且第二能量大于第一能量;以及形成遮罩的遮罩部分,包括选择性移除第一层其未布植掺质物种的部分。
在一些实施例中,上述方法形成遮罩的步骤还包括形成第二层于介电层上,且第一层位于第二层上;以及将遮罩部分的图案转移至第二层。
在一些实施例中,上述方法还包括采用遮罩并蚀刻介电层,以将遮罩的图案转移至介电层;以及形成导电结构于介电层中的图案化开口中。
在一些实施例中,上述方法在第二布植制程中布植掺质物种的步骤包括以互补的倾斜角度将掺质物种布植穿过图案化材料至第一层中。
在一些实施例中,上述方法的第一层为非晶硅,而掺质物种为二氟化硼。
在一些实施例中,上述方法的第一能量等于或小于5keV,而第二能量大于或等于10keV。
在一些实施例中,上述方法的第一布植制程所布植的掺质物种具有第一浓度与第一深度;第二布植制程所布植的掺质物种具有第二浓度与第二深度;第一浓度大于第二浓度,且第二深度大于第一深度。
在一些实施例中,上述方法选择性移除第一层的部分的步骤包括:以湿蚀刻制程蚀刻第一层,且湿蚀刻制程对第一层其未布植掺质物种的部分的蚀刻速率,大于对第一层布植掺质物种的部分的蚀刻速率。
另一实施例为用于半导体制程的方法。形成第一层于基板上。将掺质物种布植至第一层的第一区。布植的第一区具有第一深度与掺质物种的第一浓度。将掺质物种布植穿过布植的第一区至第一层的第二区。布植的第二区具有第二深度与掺质物种的第二浓度。第二深度大于第一深度。第一浓度大于第二浓度。选择性蚀刻第一层以移除第一层其布植的第一区与布植的第二区以外的第三区。选择性蚀刻之后保留布植的第一区与布植的第二区其至少部分。
在一些实施例中,上述方法以第一能量将掺质物种布植至第一区,以第二能量将掺质物种布植至第二区,且第一能量小于第二能量。
在一些实施例中,第一能量等于或小于5keV,而第二能量等于或大于10keV。
在一些实施例中,上述方法将掺质物种布植至第二区的步骤,包括以互补的倾斜角度将掺质物种布植至第一层的第二区。
在一些实施例中,上述方法的第一层为非晶硅,掺质物种为二氟化硼,第二浓度等于或大于1×1019cm-3,且选择性蚀刻第一层的步骤包括采用湿蚀刻,且湿蚀刻包括采用含氢氧化铵的溶液。
在一些实施例中,上述方法还包括形成介电层于基板上,且第一层形成于介电层上;将对应布植的第一区与布植的第二区的至少部分的图案,转移至介电层;以及形成导电结构于图案化的介电层中。
又一实施例为用于半导体制程的方法。形成介电层于基板上。形成多层遮罩结构于介电层上。多层遮罩结构包括上方层。形成图案化结构于多层遮罩结构上。经由图案化结构的开口,露出上方层的区域。经由开口与露出区域,以第一布植能量将掺质物种布植至上方层的第一区中。在以第一能量布植掺质物种之后,经由开口与露出区域,以第二布植能量将掺质物种布植至上方层的第二区中。第二布植能量大于第一布植能量。以蚀刻剂蚀刻上方层。蚀刻剂对上方层不含掺质物种的部分的蚀刻速率,大于对第一区与第二区的蚀刻速率。将蚀刻的上方层其图案转移至介电层。
在一些实施例中,上述方法形成图案化结构的步骤包括:形成第一牺牲层于多层遮罩结构上;形成第二牺牲层于第一牺牲层上;形成图案化的光刻胶于第二牺牲层上;以及将图案化的光刻胶的图案转移至第二牺牲层与第一牺牲层,以形成图案化结构的开口,且开口延伸穿过第二牺牲层与第一牺牲层。
在一些实施例中,上述方法的多层遮罩结构还包括介电层上的下方层,与下方层上的中间层,且上方层位于中间层上,上方层为非晶硅,中间层为氧化物材料,下方层为氮化物材料,且转移蚀刻的上方层的图案至介电层的步骤包括:转移蚀刻的上方层的图案至中间层与下方层。
在一些实施例中,上述方法的上方层为非晶硅,掺质物种为二氟化硼,第一布植能量等于或小于5keV,第二布植能量等于或大于10keV,且蚀刻剂为稀氢氧化铵的溶液。
在一些实施例中,上述方法的第一区中的掺质物种其第一浓度,大于第二区中的掺质物种其第二浓度。
在一些实施例中,上述方法以第二布植能量将掺质物种布植至上方层的第二区中的步骤,包括以互补的倾斜角度与第二布植能量将掺质物种布植至上方层的第二区中。
上述实施例的特征有利于本技术领域中技术人员理解本发明。本技术领域中技术人员应理解可采用本发明作基础,设计并变化其他制程与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中技术人员亦应理解,这些等效置换并未脱离本发明构思与范围,并可在未脱离本发明的权利要求的构思与范围的前提下进行改变、替换、或变动。
Claims (1)
1.一种用于半导体制程的方法,包括:
形成一介电层于一基板上;以及
形成一遮罩于该介电层上,且形成该遮罩的步骤包括:
沉积一第一层于该介电层上;
在一第一布植制程中以一第一能量将一掺质物种布植穿过一图案化材料至该第一层中;
在该第一布植制程之后,在一第二布植制程中以一第二能量将该掺质物种布植穿过该图案化材料至该第一层中,且该第二能量大于该第一能量;以及
形成该遮罩的遮罩部分,包括选择性移除该第一层其未布植该掺质物种的部分。
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US15/920,745 US10460940B2 (en) | 2018-03-14 | 2018-03-14 | Mask formation by selectively removing portions of a layer that have not been implanted |
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CN113078049A (zh) * | 2020-01-06 | 2021-07-06 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
CN115513051A (zh) * | 2022-11-04 | 2022-12-23 | 合肥晶合集成电路股份有限公司 | 硬掩模层返工方法及dmos形成方法 |
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CN111524794B (zh) * | 2019-02-02 | 2023-07-07 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
US11688610B2 (en) * | 2020-09-30 | 2023-06-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Feature patterning using pitch relaxation and directional end-pushing with ion bombardment |
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US7737049B2 (en) * | 2007-07-31 | 2010-06-15 | Qimonda Ag | Method for forming a structure on a substrate and device |
TWI362692B (en) * | 2008-03-11 | 2012-04-21 | Nanya Technology Corp | Method for promoting a semiconductor lithography resolution |
US8772183B2 (en) * | 2011-10-20 | 2014-07-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming an integrated circuit |
US8772102B2 (en) * | 2012-04-25 | 2014-07-08 | Globalfoundries Inc. | Methods of forming self-aligned contacts for a semiconductor device formed using replacement gate techniques |
US9852983B1 (en) * | 2017-02-08 | 2017-12-26 | United Microelectronics Corporation | Fabricating method of anti-fuse structure |
US10411020B2 (en) * | 2017-08-31 | 2019-09-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Using three or more masks to define contact-line-blocking components in FinFET SRAM fabrication |
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CN113078049A (zh) * | 2020-01-06 | 2021-07-06 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
CN115513051A (zh) * | 2022-11-04 | 2022-12-23 | 合肥晶合集成电路股份有限公司 | 硬掩模层返工方法及dmos形成方法 |
CN115513051B (zh) * | 2022-11-04 | 2023-02-10 | 合肥晶合集成电路股份有限公司 | 硬掩模层返工方法及dmos形成方法 |
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US20200058505A1 (en) | 2020-02-20 |
US20190287802A1 (en) | 2019-09-19 |
US10460940B2 (en) | 2019-10-29 |
TW201939576A (zh) | 2019-10-01 |
US10714344B2 (en) | 2020-07-14 |
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