CN110246829A - 半导体封装件和半导体模块 - Google Patents

半导体封装件和半导体模块 Download PDF

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Publication number
CN110246829A
CN110246829A CN201910115969.6A CN201910115969A CN110246829A CN 110246829 A CN110246829 A CN 110246829A CN 201910115969 A CN201910115969 A CN 201910115969A CN 110246829 A CN110246829 A CN 110246829A
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layer
semiconductor chip
semiconductor
electro
magnetic screen
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CN201910115969.6A
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CN110246829B (zh
Inventor
李政泌
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B17/00—Layered products essentially comprising sheet glass, or glass, slag, or like fibres
    • B32B17/06—Layered products essentially comprising sheet glass, or glass, slag, or like fibres comprising glass as the main or only constituent of a layer, next to another layer of a specific material
    • B32B17/10—Layered products essentially comprising sheet glass, or glass, slag, or like fibres comprising glass as the main or only constituent of a layer, next to another layer of a specific material of synthetic resin
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
    • B32B7/04—Interconnection of layers
    • B32B7/12—Interconnection of layers using interposed adhesives or interposed materials with bonding properties
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Abstract

可以提供半导体封装件和半导体模块。所述半导体封装件包括：封装件基底，包括接地层，接地层的第一段暴露于封装件基底外部；半导体芯片，位于封装件基底上；以及功能层，包括导电聚合物和粘合剂聚合物，功能层覆盖半导体芯片，并与接地层的第一段接触。

Description

半导体封装件和半导体模块
本申请要求于2018年3月9日在韩国知识产权局提交的第10-2018-0028026号韩国专利申请以及于2018年9月14日在美国专利商标局提交的第16/131,596号美国专利申请的的优先权，该韩国专利申请和该美国专利申请的全部内容通过引用包含于此。
技术领域
发明构思涉及半导体封装件和/或半导体模块，更具体地，涉及半导体封装件和/或包括具有透明度、粘附性和高导电性的功能层的半导体模块。
背景技术
随着移动市场的扩大，正在积极地进行对从电子设备发射的电磁波的研究。对于多种电子产品，来自半导体封装件的电磁波发射可能与其它附近的半导体封装件引起问题。电磁干扰会导致各种故障、操作异常、操作失败等。
已经开发了各种类型的半导体封装件以满足对高速且致密的半导体封装件的不断增长的需求，然而，电磁干扰问题仍然存在。
发明内容
发明构思的一些示例实施例提供了以低成本制造、具有小的厚度并且没有环境和残留问题的半导体封装件。
发明构思的一些示例实施例提供了均包括半导体芯片的半导体封装件，可以可视地识别半导体芯片上的标记。
根据发明构思的示例实施例，半导体封装件可以包括：封装件基底，包括绝缘层和接地层，接地层在绝缘层中纵向延伸，接地层的端部部分被绝缘层暴露；半导体芯片，位于封装件基底上；模制层，位于封装件基底上，并至少围绕半导体芯片的侧表面；以及电磁屏蔽层，覆盖模制层和半导体芯片，电磁屏蔽层的端部部分与接地层的端部部分平行地延伸并与接地层的端部部分接触，电磁屏蔽层包括第一侧部分和第二侧部分，第一侧部分面对半导体芯片的侧表面，第二侧部分位于电磁屏蔽层的端部处并与第一侧部分水平地间隔开，电磁屏蔽层的第二侧部分与接地层的侧端部表面位于大体直线上并暴露于封装件基底的外部。
根据发明构思的示例实施例，半导体封装件可以包括：封装件基底，包括绝缘层和接地层，接地层在绝缘层中纵向延伸，接地层的端部部分被绝缘层暴露；半导体芯片，位于封装件基底上；模制坝，从封装件基底的顶表面向上延伸，模制坝与半导体芯片水平地间隔开；窗层，由模制坝支撑，窗层和模制坝包围封装件基底上的半导体芯片，窗层是透明的；以及电磁屏蔽层，覆盖模制坝和窗层，电磁屏蔽层包括与接地层的暴露的端部部分平行地延伸并与接地层的暴露的端部部分接触的端部部分，电磁屏蔽层还包括第一侧部分和第二侧部分，第一侧部分面对半导体芯片的侧表面，第二侧部分位于电磁屏蔽层的端部处并与第一侧部分水平地间隔开，电磁屏蔽层的第二侧部分与接地层的侧端部表面位于大体直线上并暴露于封装件基底的外部。
根据发明构思的示例实施例，半导体模块可以包括：模块基底；多个电子组件，位于模块基底上，电子组件包括一个或更多个半导体芯片；多个底部填充树脂层，位于模块基底与所述多个电子组件中的各个电子组件之间；以及电磁屏蔽层，覆盖电子组件的顶表面和侧表面以及所述多个底部填充树脂层的侧表面，电磁屏蔽层包括：多个上部，位于所述多个电子组件的各个顶表面上；多个第一侧部分，位于所述多个电子组件的各个侧表面上；多个第二侧部分，位于所述多个底部填充树脂层的各个侧表面上；以及多个下部，位于模块基底的顶表面上，所述多个第一侧部分中的一个第一侧部分与所述多个第二侧部分中的一个第二侧部分的竖直连接对使所述多个上部中的相应一个上部与所述多个下部中的相应一个下部连接。
根据发明构思的示例实施例，一种制备半导体封装件的方法可以包括：设置包括绝缘层和在绝缘层内纵向延伸的接地层的封装件基底；将多个半导体芯片设置在封装件基底的顶表面上以彼此间隔开；将模制层设置在封装件基底上以至少围绕半导体芯片的侧表面并具有基本平坦的顶表面；在所述多个半导体芯片之间切割模制层直到封装件基底中的接地层被暴露，使得在所述多个半导体芯片中的相邻半导体芯片之间形成多个凹槽；在模制层和半导体芯片上顺序地设置电磁屏蔽层和垫层；对垫层和电磁屏蔽层进行处理以(1)使电磁屏蔽层共形地覆盖模制层的顶表面和侧表面并且(2)使垫层填充凹槽，凹槽的侧表面和底表面被电磁屏蔽层共形地覆盖；去除垫层；以及在所述多个凹槽中对封装件基底进行切割以形成单独的半导体封装件，使得在每个单独的半导体封装件中，(1)电磁屏蔽层的端部部分与接地层的端部部分平行地延伸并与接地层的端部部分接触，(2)电磁屏蔽层包括第一侧部分和第二侧部分，第一侧部分面对半导体芯片的侧表面，第二侧部分位于电磁屏蔽层的端部处并与第一侧部分水平地间隔开，电磁屏蔽层的第二侧部分与接地层的侧端部表面位于大体直线上并暴露于封装件基底的外部。
附图说明
图1A示出了显示根据发明构思的示例实施例的半导体封装件的剖视图。
图1B示出了显示图1A的部分A的放大图。
图2A示出了显示根据发明构思的示例实施例的半导体封装件的剖视图。
图2B示出了显示根据发明构思的示例实施例的半导体封装件的剖视图。
图3A示出了显示根据发明构思的示例实施例的半导体模块的剖视图。
图3B示出了显示根据发明构思的示例实施例的半导体模块的剖视图。
图4A至图4E示出了显示根据发明构思的示例实施例的制造半导体封装件的方法的剖视图。
图5A至图5E示出了显示根据发明构思的示例实施例的制造半导体封装件的方法的剖视图。
图6示出了显示根据发明构思的示例实施例的制造半导体封装件的方法的剖视图。
图7A至图7C示出了显示根据发明构思的示例实施例的制造半导体模块的方法的剖视图。
图8示出了显示根据发明构思的示例实施例的制造半导体模块的方法的剖视图。
具体实施方式
图1A示出了显示根据发明构思的示例实施例的半导体封装件的剖视图。图1B示出了显示图1A的部分A的放大图。
参照图1A和图1B，半导体封装件1000可以包括封装件基底101、外部端子105、半导体芯片201、结合布线203、模制层205和功能层207。
封装件基底101可以是具有电路图案的印刷电路板(PCB)，或者可以包括具有电路图案的印刷电路板(PCB)。封装件基底101可以包括第一区域10和第二区域20。封装件基底101的第二区域20可以围绕封装件基底101的第一区域10。封装件基底101可以包括第一顶表面1、第二顶表面3和底表面2。封装件基底101可以被构造为使得第一顶表面1放置在第一区域10上且第二顶表面3放置在第二区域20上。封装件基底101的第二顶表面3可以位于与封装件基底101的第一顶表面1的水平不同的水平处。例如，封装件基底101的第二顶表面3可以位于比封装件基底101的第一顶表面1的水平低的水平处。
封装件基底101可以包括接地层103和绝缘层107。接地层103可以在绝缘层107中纵向延伸，并且接地层103的端部部分可以被绝缘层107暴露。接地层103可以设置在封装件基底101的第一区域10和第二区域20二者上。接地层103可以设置在封装件基底101的第一区域10的第一侧表面4下方。接地层103可以包括位于第一区域10上的第一段RG1和位于第二区域20上的第二段RG2。例如，如所示出的，接地层103的第二段RG2可以具有顶表面(例如，第二顶表面3)和第二侧表面6，第二段RG2的表面3和6可以暴露于封装件基底101外部。在一些示例实施例中，接地层103的第二段RG2的第二侧表面6可以暴露于封装件基底101外部，接地层103的第二段RG2的第二顶表面3可以不暴露于封装件基底101外部。接地层103的第二段RG2可以被定义为接地端子。接地层103可以包括导电材料。例如，导电材料可以包括金属材料(例如，银(Ag)、金(Au)或铜(Cu))、金属合金(例如，铜-银(Cu-Ag)、钛-银-铜(Ti-Ag-Cu)或铜-锌(Cu-Zn))或其它导电材料。
外部端子105可以设置在封装件基底101的底表面2上。外部端子105可以是但不局限于焊球、导电凸块、导电垫片(conductive spacer)或针栅阵列。
接地层103可以电连接到外部端子105中的特定的外部端子105。该特定的外部端子105可以供应有接地电压。
半导体芯片201可以设置在封装件基底101的第一顶表面1上。半导体芯片201可以设置在封装件基底101的第一区域10上。半导体芯片201可以通过粘合层202粘附到封装件基底101的第一顶表面1上。例如，半导体芯片201可以是半导体逻辑芯片、半导体存储器芯片、芯片上系统(SOC)或芯片上实验室(LOC)。
半导体芯片201和封装件基底101可以通过设置在半导体芯片201与封装件基底101之间的结合布线203而彼此电连接。结合布线203可以包括例如金(Au)、银(Ag)、铂(Pt)、铝(Al)、铜(Cu)、钯(Pd)、镍(Ni)、钴(Co)、铬(Cr)和钛(Ti)中的一种或更多种。虽然未示出，但是半导体芯片201可以以芯片倒装结合方式或其它可能的方式安装在封装件基底101上。
模制层205可以设置在封装件基底101的第一区域10上。模制层205可以覆盖封装件基底101的第一区域10的第一顶表面1。模制层205可以具有与封装件基底101的第一区域10的第一侧表面4对齐的侧表面。模制层205可以至少围绕半导体芯片201的侧表面。在一些示例实施例中，模制层205可以围绕半导体芯片201的侧表面并覆盖半导体芯片201的顶表面。模制层205可以具有比封装件基底101的宽度W2小的宽度W1(W1<W2)。例如，模制层205可以包括环氧模制化合物(EMC)或底部填充材料。可以在模制层205的顶表面上显示标记(未示出)。该标记可以是用于表达特定信息的一个或更多个字符，或者可以包括用于表达特定信息的一个或更多个字符。
模制层205可以覆盖(涂覆)有功能层207，功能层207延伸到封装件基底101的第一区域10的第一侧表面4上并延伸到接地层103的第二段RG2的第二顶表面3上。功能层207可以与接地层103的第二段RG2的第二顶表面3接触。在一些示例实施例中，模制层205可以被功能层207覆盖，功能层207延伸到接地层103的第二段RG2的第二侧表面6上。在这样的示例实施例中，功能层207可以与接地层103的第二段RG2的第二侧表面6接触，而不与接地层103的第二段RG2的第二顶表面3接触。
功能层207可以具有均匀的厚度。例如，功能层207的覆盖模制层205的部分、功能层207的覆盖封装件基底101的第一区域10的第一侧表面4的部分以及功能层207的覆盖接地层103的第二段RG2的第二顶表面3的部分可以具有彼此基本相同或基本相似的厚度。例如，功能层207可以具有等于或小于大约40μm的厚度。
功能层207可以是电磁屏蔽层。因此，术语“功能层”和“电磁屏蔽层”可以在整个此公开中可交换地使用。再次参照图1A，功能层207可以覆盖模制层205和半导体芯片201。功能层207的端部部分可以与接地层103的端部部分平行地延伸并与接地层103的端部部分接触。功能层207可以包括：第一侧部分，面对半导体芯片201的侧表面；以及第二侧部分，设置在功能层207的端部处，并与第一侧部分水平地间隔开。功能层207的第二侧部分和接地层103的侧端部表面可以在大体直线上，并可以暴露于封装件基底101的外部。因此，功能层207可以电连接到接地层103，并且可以提供用于使入射在功能层207上的电磁波接地的电路径。
返回参照图1B，功能层207可以包括导电聚合物207a和粘合剂聚合物207b。导电聚合物207a可以具有相对高的导电率。例如，导电聚合物207a可以具有在大约500S/cm至大约2000S/cm范围内的导电率。导电聚合物207a可以是透明的。例如，导电聚合物207a可以具有等于或高于大约90％的可见光透射率。例如，导电聚合物207a可以包括聚(3,4-乙撑二氧噻吩)(PEDOT)、聚(3,4-乙撑二氧噻吩)(PEDOT):聚苯乙烯磺酸钠(PSS)以及聚(4,4-二辛基环戊二噻吩)中的一种或更多种。粘合剂聚合物207b可以具有相对高的粘附性。粘合剂聚合物207b可以是透明的。例如，粘合剂聚合物207b可以具有等于或高于大约90％的可见光透射率。例如，粘合剂聚合物207b可以包括丙烯酸聚合物类介孔和丙烯酸微乳液中的一种或更多种。粘合剂聚合物207b可以包括光引发剂。光引发剂可以在执行固化工艺时加速粘合剂聚合物207b的交联反应。
功能层207还可以包括导电填料207c。导电填料207c的导电率可以大于导电聚合物207a的导电率。例如，导电填料207c可以具有在大约5000S/cm至大约20000S/cm范围内的导电率。导电填料207c可以是透明的。例如，导电填料207c可以具有等于或高于大约90％的可见光透射率。例如，导电填料207c可以包括透明导电氧化物(TCO)。例如，导电填料207c可以是包括氧化铟锌(IZO)、氧化铟锡(ITO)和氧化铝锌(AZO)中的一种或更多种的无机材料。在一些示例实施例中，导电填料207c可以是包括碳纳米管(CNT)和石墨烯中的一种或更多种的有机材料。因为功能层207还包括导电填料207c，所以可以增大功能层207的导电率。在一些示例实施例中，导电填料207c可以具有薄片形状。导电聚合物207a、粘合剂聚合物207b和导电填料207c可以不规则地布置在功能层207中。
因为功能层207包括导电聚合物207a、粘合剂聚合物207b和导电填料207c，所以可以增大功能层207的导电率和粘附性。因此，功能层207可以用作电磁波的接地路径，并且可以粘附到模制层205和接地层103，而不需要单独提供粘合剂。功能层207可以是透明的。因此，即使在功能层207覆盖模制层205时，也可以可视地识别印刷在模制层205的顶表面上的标记。
功能层207可以使半导体封装件1000以较低的成本制造并且/或者具有较小的厚度。半导体封装件1000可以不具有用于屏蔽电磁波的金属材料，从而使环境和残留问题减少。
图2A示出了显示根据发明构思的示例实施例的半导体封装件的剖视图。
为了简化描述，与参照图1A和图1B所讨论的组件相同或基本相似的组件分配了与参照图1A和图1B所讨论的组件的附图标记相同的附图标记，并且将省略它们的重复说明。
参照图2A，半导体封装件1000’可以包括封装件基底101、外部端子105、半导体芯片201、结合布线203、模制坝204、窗层206和功能层207。
封装件基底101可以是具有电路图案的印刷电路板(PCB)，或者可以包括具有电路图案的印刷电路板(PCB)。封装件基底101可以包括接地层103和绝缘层107。接地层103可以在绝缘层107中纵向延伸，并且接地层103的端部部分可以被绝缘层107暴露。外部端子105可以设置在封装件基底101的底表面2上。
半导体芯片201可以设置在封装件基底101的第一顶表面1上。半导体芯片201可以通过粘合层202粘附到封装件基底101的第一顶表面1上。例如，半导体芯片201可以是发光芯片、光学传感器芯片或芯片上实验室(LOC)。半导体芯片201和封装件基底101可以通过设置在半导体芯片201与封装件基底101之间的结合布线203而彼此电连接。
模制坝204可以设置在封装件基底101的第一区域10上。模制坝204可以竖直地位于功能层207下，并且可以水平地位于功能层207内。模制坝204可以从封装件基底101的第一区域10的第一顶表面1的边缘向上延伸。模制坝204可以具有与封装件基底101的第一区域10的第一侧表面4对齐的侧表面。模制坝204可以与半导体芯片201水平地间隔开。当在平面图中观看时，模制坝204可以围绕半导体芯片201的侧表面。模制坝204可以具有比封装件基底101的宽度W2小的宽度W3(W3<W2)。换言之，当在剖面中观看时，模制坝204的左外壁和右外壁之间的距离W3可以小于封装件基底101的宽度W2。模制坝204的顶表面可以位于比半导体芯片201的顶部高的水平或位置处。
窗层206可以设置在模制坝204和半导体芯片201上。模制坝204可以支撑窗层206。窗层206可以与半导体芯片201间隔开。窗层206和模制坝204可以在封装件基底101上包围半导体芯片201。窗层206可以是透明的。例如，窗层206可以包括玻璃。
腔C可以由第一顶表面1、模制坝204和窗层206限定。例如，腔C可以是由第一顶表面1、模制坝204和窗层206围绕的空的空间。半导体芯片201可以设置在腔C中。
例如，如所示出的，模制坝204和窗层206可以被功能层207覆盖，功能层207延伸到封装件基底101的第一区域10的第一侧表面4上，并且延伸到接地层103的第二段RG2的第二顶表面3上。功能层207可以包括与接地层103的暴露的端部部分平行地延伸并且与接地层103的暴露的端部部分接触的端部部分。功能层207可以包括：第一侧部分，面对半导体芯片201的侧表面；以及第二侧部分，设置在功能层207的端部处，并与第一侧部分水平地间隔开。功能层207的第二侧部分和接地层103的侧端部表面可以在大体直线上，并可以暴露于封装件基底101的外部。在一些示例实施例中，模制坝204和窗层206可以被功能层207覆盖，功能层207延伸到接地层103的第二段RG2的第二侧表面6上，同时功能层207被设置为与接地层103接触。功能层207可以包括导电聚合物207a和粘合剂聚合物207b，如图1B中所示。功能层207还可以包括导电填料207c，如图1B中所示。
因为功能层207包括导电聚合物207a、粘合剂聚合物207b和导电填料207c，所以可以增大功能层207的导电率和粘附性。因此，功能层207可以用作电磁波的接地路径，并且可以粘附到模制坝204、窗层206和接地层103，而不需要单独提供粘合剂。窗层206和功能层207可以是透明的。因此，在半导体芯片201为发光芯片的情况下，从半导体芯片201发射的光可以通过窗层206和功能层207向外辐射。在半导体芯片201为光学传感器芯片的情况下，半导体芯片201可以通过窗层206和功能层207接收外部的光。
图2B示出了显示根据发明构思的示例实施例的半导体封装件的剖视图。
为了简化描述，与参照图1A、图1B和图2A所讨论的组件相同或基本相似的组件分配了与参照图1A、图1B和图2A所讨论的组件的附图标记相同的附图标记，并且将省略它们的重复说明。
参照图2B，半导体封装件1000”可以包括封装件基底101、外部端子105、第一半导体芯片201、第二半导体芯片209、结合布线203、模制坝204、窗层206和功能层207。
第一半导体芯片201可以设置在封装件基底101的第一顶表面1上。第一半导体芯片201可以通过第一粘合层202粘附到封装件基底101的第一顶表面1上。例如，第一半导体芯片201可以是半导体逻辑芯片、半导体存储器芯片、芯片上系统(SOC)或芯片上实验室(LOC)。第一半导体芯片201和封装件基底101可以通过设置在第一半导体芯片201与封装件基底101之间的结合布线203而彼此电连接。
第二半导体芯片209可以设置在第一半导体芯片201的顶表面上。第二半导体芯片209可以通过第二粘合层210粘附到第一半导体芯片201的顶表面。例如，第二半导体芯片209可以是发光芯片、光学传感器芯片或芯片上实验室(LOC)。第二半导体芯片209和封装件基底101可以通过设置在第二半导体芯片209与封装件基底101之间的结合布线203而彼此电连接。
虽然未示出，但半导体封装件1000”还可以包括位于第一半导体芯片201与第二半导体芯片209之间的其它半导体芯片。
图3A示出了显示根据发明构思的示例实施例的半导体模块的剖视图。
为了简化描述，与参照图1A和图1B所讨论的组件相同或基本相似的组件分配了与参照图1A和图1B所讨论的组件的附图标记相同的附图标记，并且将省略它们的重复说明。
参照图3A，半导体模块2000可以包括模块基底300以及位于模块基底300上的第一半导体芯片401a、第二半导体芯片401b、第三半导体芯片401c、组件411和功能层207。第一半导体芯片401a、第二半导体芯片401b、第三半导体芯片401c和组件411可以被统称为多个电子组件。
模块基底300可以是具有电路图案的印刷电路板(PCB)，或者可以包括具有电路图案的印刷电路板(PCB)。第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c可以设置在模块基底300上。第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c可以具有彼此不同的高度。第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c中的每个可以是半导体逻辑芯片、半导体存储器芯片、芯片上系统(SOC)或芯片上实验室(LOC)。
多个焊球407可以设置在模块基底300与第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c中的每个之间。焊球407可以电连接在模块基底300与第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c中的每个之间。第一底部填充树脂层409可以设置在模块基底300与第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c中的每个之间的间隙内。第一底部填充树脂层409可以围绕焊球407的表面。例如，第一底部填充树脂层409可以包括底部填充材料。
组件411可以设置在模块基底300上。例如，组件411可以设置在第一半导体芯片401a与第三半导体芯片401c之间。组件411的位置不限于以上所述，而是可以被各种改变。组件411可以通过粘合层413附着到模块基底300上。在一些示例实施例中，可以利用电阻器、电感器、变压器、无源器件或其它电子器件来替代组件411。组件411的高度可以与第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c的高度不同。第二底部填充树脂层415可以设置在组件411与模块基底300之间，并且可以围绕粘合层413。
功能层207可以在覆盖多个第一底部填充树脂层409的侧表面、第二底部填充树脂层415的侧表面、第一半导体芯片401a、第二半导体芯片401b、第三半导体芯片401c和组件411的同时延伸到模块基底300的顶表面上。例如，功能层207可以覆盖第一半导体芯片401a的顶表面和侧表面、第二半导体芯片401b的顶表面和侧表面、第三半导体芯片401c的顶表面和侧表面、多个第一底部填充树脂层409的表面和第二底部填充树脂层415的表面。功能层207也可以覆盖组件411的顶表面和侧表面。
功能层207可以延伸到模块基底300的暴露于第一空间S1的顶表面上并延伸到模块基底300的暴露于第二空间S2的顶表面上，第一空间S1位于第一半导体芯片401a与第二半导体芯片401b之间，第二空间S2位于组件411与第一半导体芯片401a之间。功能层207可以延伸到模块基底300的暴露于第三空间S3的顶表面上，第三空间S3位于第三半导体芯片401c与组件411之间。功能层207可以包括：多个上部，位于多个电子组件的各个顶表面上；多个第一侧部分，位于多个电子组件的各个侧表面上；多个第二侧部分，位于多个底部填充树脂层的各个侧表面上；以及多个下部，位于模块基底300的顶表面上。多个第一侧部分中的一个第一侧部分与多个第二侧部分中的一个第二侧部分的竖直连接对可以使多个上部中的相应一个上部与多个下部中的相应一个下部连接。功能层207可以包括导电聚合物207a和粘合剂聚合物207b，如图1B中所示。功能层207还可以包括导电填料207c，如图1B中所示。
功能层207的覆盖模块基底300的顶表面的部分的厚度可以与功能层207的覆盖第一半导体芯片401a、第二半导体芯片401b、第三半导体芯片401c、多个第一底部填充树脂层409、组件411和第二底部填充树脂层415的每个部分的厚度相同或基本相似。例如，功能层207可以具有等于或小于大约40μm的厚度。第一空间S1、第二空间S2和第三空间S3中的每个可以具有等于或小于大约5的高宽比。高宽比可以与通过将第一空间S1、第二空间S2和第三空间S3中的每个的深度(或高度)除以第一空间S1、第二空间S2和第三空间S3中的每个的宽度获得的值对应。
图3B示出了显示根据发明构思的示例实施例的半导体模块的剖视图。
为了简化描述，与参照图1A、图1B和图3A所讨论的组件相同或基本相似的组件分配了与参照图1A、图1B和图3A所讨论的组件的附图标记相同的附图标记，并且将省略它们的重复说明。
参照图3B，半导体模块2000’可以包括模块基底300、第一半导体芯片401a、第二半导体芯片401b、第三半导体芯片401c、组件411、功能层207、模制坝422和窗层421。
第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c可以设置在模块基底300上。第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c中的每个可以是发光芯片、光学传感器芯片或芯片上实验室(LOC)。
组件411可以设置在模块基底300上。
模制坝422可以设置在模块基底300上。模制坝422可以从模块基底300的顶表面向上延伸。模制坝422可以与组件411间隔开并与第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c间隔开。当在平面图中观看时，模制坝422可以围绕组件411、第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c。
窗层421可以设置在模制坝422、组件411、第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c上。模制坝422可以支撑窗层421。窗层421可以与组件411间隔开并与第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c间隔开。窗层421可以是透明的。例如，窗层421可以包括玻璃。
模制坝422和窗层421可以被功能层207覆盖，功能层207延伸到模块基底300的边缘的顶表面上。例如，功能层207可以覆盖窗层421的顶表面、模制坝422的侧表面和模块基底300的边缘的顶表面。
图4A至图4E示出了显示根据发明构思的示例实施例的制造半导体封装件的方法的剖视图。
为了简化描述，与参照图1A和图1B所讨论的组件相同或基本相似的组件分配了与参照图1A和图1B所讨论的组件的附图标记相同的附图标记，并且将省略它们的重复说明。
参照图4A，封装件基底101可以包括第一顶表面1和底表面2。封装件基底101可以是具有电路图案的印刷电路板(PCB)，或者可以包括具有电路图案的印刷电路板(PCB)。封装件基底101可以包括接地层103。可以在封装件基底101内设置接地层103。接地层103可以包括导电材料。例如，导电材料可以包括金属材料(例如，银(Ag)、金(Au)或铜(Cu))、金属合金(例如，铜-银(Cu-Ag)、钛-银-铜(Ti-Ag-Cu)或铜-锌(Cu-Zn))或其它导电材料。
可以在封装件基底101的第一顶表面1上设置多个半导体芯片201，同时多个半导体芯片201例如以规则的间距彼此间隔开。每个半导体芯片201可以通过粘合层202粘附到封装件基底101上。例如，半导体芯片201可以是半导体逻辑芯片、半导体存储器芯片、芯片上系统(SOC)或芯片上实验室(LOC)。
可以在封装件基底101与每个半导体芯片201之间设置多条结合布线203。结合布线203可以使半导体芯片201电连接到封装件基底101。例如，结合布线203可以由金(Au)、银(Ag)、铂(Pt)、铝(Al)、铜(Cu)、钯(Pd)、镍(Ni)、钴(Co)、铬(Cr)和钛(Ti)中的一种或更多种形成。
可以在封装件基底101的第一顶表面1上形成模制层205。模制层205可以覆盖半导体芯片201。例如，模制层205可以由环氧模制化合物(EMC)或底部填充材料形成。可以在封装件基底101的底表面2上形成多个外部端子105。在外部端子105为焊球的情况下，可以在封装件基底101的底表面2上执行焊接工艺以形成外部端子105。
参照图4B，可以对模制层205和封装件基底101执行切割工艺。切割工艺可以部分地切割位于半导体芯片201之间的模制层205以及位于半导体芯片201之间的封装件基底101。切割工艺可以部分地切割模制层205的边缘以及封装件基底101的与模制层205的所述边缘叠置的边缘。切割工艺可以在一对相邻的半导体芯片201之间形成凹槽H。切割工艺可以在模制层205的第一边缘与半导体芯片201中的最左边的半导体芯片201的边缘之间形成凹槽H。切割工艺可以在模制层205的第二边缘与半导体芯片201中的最右边的半导体芯片201的边缘之间形成凹槽H，模制层205的第二边缘与模制层205的第一边缘相对。一对相邻的凹槽H可以在它们之间限定单元半导体封装件占据的区域。凹槽H可以具有比封装件基底101的第一顶表面1低的底板表面。例如，凹槽H可以具有等于或小于大约5的高宽比。高宽比可以与通过将凹槽H的深度(或高度)除以凹槽H的宽度获得的值对应。切割工艺可以将模制层205分成多块。切割工艺可以继续直到使接地层103暴露。在切割工艺之后，接地层103可以部分地暴露于凹槽H。
可以在模制层205上设置功能层207，并且可以在功能层207上设置垫层208。
功能层207可以是电磁屏蔽层。功能层207可以包括导电聚合物207a和粘合剂聚合物207b，如图1B中所示。功能层207还可以包括导电填料207c，如图1B中所示。
下面描述形成功能层207的方法。可以将导电聚合物207a、粘合剂聚合物207b和导电填料207c溶解在溶剂中以形成液化复合物。例如，溶剂可以包括乙醇。可以对液化复合物进行湿式涂覆以具有适合的厚度，然后在烘箱中进行干燥以从液化复合物中蒸发溶剂。因此，功能层207可以形成为具有处于固态下的导电聚合物207a、粘合剂聚合物207b和导电填料207c。例如，功能层207可以具有等于或小于大约40μm的厚度。
垫层208可以具有在大约50μm以至大约400μm范围内的厚度。垫层208可以包括聚乙烯类聚合物或聚氨酯类聚合物。例如，聚乙烯类聚合物可以包括聚甲基戊烯(PMP)、聚氯乙烯(PVC)或聚对苯二甲酸丁二醇酯(PBT)。例如，聚氨酯类聚合物可以包括热塑性聚氨酯(TPU)。
参照图4C，可以对功能层207和垫层208进行处理以覆盖模制层205并填充凹槽H。例如，功能层207可以共形地覆盖模制层205的顶表面和侧表面以及凹槽H的底板表面。垫层208可以覆盖功能层207并填充凹槽H。可以执行压制工艺以使功能层207和垫层208覆盖模制层205的表面并填充凹槽H。可以执行压制工艺，使得在功能层207和垫层208设置在模制层205上的状态下，对功能层207和垫层208进行加热并压靠在封装件基底101上大约5分钟至大约15分钟。可以在大约2MPa至大约10MPa范围内的压强下、在大约50℃至大约150℃范围内的温度下执行压制工艺。
垫层208可以由于热和压强而具有减小的弹性模量，使得凹槽H可以容易地被垫层208填充。功能层207可以共形地覆盖凹槽H的底板表面以及模制层205的侧表面。
参照图4D，可以从功能层207去除垫层208。压制工艺可以使垫层208扩展，并减小垫层208的弹性模量，因此外部物理力可以将垫层208与功能层207容易地分离。功能层207可以保留在模制层205的表面和凹槽H的底板表面上。在去除垫层208之后，可以对功能层207执行固化工艺。固化工艺可以使功能层207固化。固化工艺可以将紫外线照射到功能层207。紫外线可以具有在大约100mJ至大约1000mJ范围内的强度。可以照射紫外线大约1秒至大约5分钟。在固化工艺中，粘合剂聚合物的光引发剂(见图1B的207b)可以加速粘合剂聚合物207b的交联过程。当使用波长范围在大约300nm至大约600nm内的紫外线照射光引发剂时，可以加速交联过程。
根据发明构思的一些示例实施例，功能层207可以共形地覆盖模制层205的顶表面，同时，可以共形地覆盖凹槽H的底板表面和侧壁。可以在诸如切锯工艺或分选工艺的封装件切单工艺(package singulation process)之前执行功能层207的形成。因此，与在封装件切单工艺(切锯或分选)之后在每个半导体封装件上形成功能层207的情况相比，可以减少工艺时间。
参照图4E，可以在凹槽H内执行封装件切单工艺(切锯或分选)，从而形成多个半导体封装件。如果在执行切割工艺时封装件基底101具有非切割部分，则封装件切单工艺(切锯或分选)可以完全切割封装件基底101的非切割部分。例如，封装件切单工艺(切锯或分选)可以沿划线(具有小于凹槽H的宽度的宽度)来切割封装件基底101，从而减轻或防止形成在模制层205的侧表面上的功能层207被去除。
图5A至图5E示出了显示根据发明构思的示例实施例的制造半导体封装件的方法的剖视图。
为了简化描述，与参照图4A至图4E所讨论的组件相同或基本相似的组件分配了与参照图4A至图4E所讨论的组件的附图标记相同的附图标记，并且将省略它们的重复说明。
参照图5A，封装件基底101可以包括第一顶表面1和底表面2。封装件基底101可以包括接地层103。
可以在封装件基底101的第一顶表面1上形成多个半导体芯片201，同时多个半导体芯片201以规则的间距彼此间隔开。每个半导体芯片201可以通过粘合层202粘附到封装件基底101上。例如，半导体芯片201可以是发光芯片、光学传感器芯片或芯片上实验室(LOC)。可以在封装件基底101与每个半导体芯片201之间设置多条结合布线203。
可以在封装件基底101的第一顶表面1上形成模制坝204。模制坝204可以从第一顶表面1的边缘向上延伸。模制坝204可以与每个半导体芯片201间隔开。当在平面图中观看时，模制坝204可以围绕每个半导体芯片201。
可以在模制坝204和半导体芯片201上设置窗层206。模制坝204可以支撑窗层206。窗层206可以与每个半导体芯片201间隔开。窗层206可以是透明的。例如，窗层206可以包括玻璃。
多个腔C可以由第一顶表面1、模制坝204和窗层206限定。例如，腔C可以是由第一顶表面1、模制坝204和窗层206围绕的空的空间。每个腔C可以在其中容纳一个半导体芯片201。
可以在封装件基底101的底表面2上形成多个外部端子105。
参照图5B，可以对模制坝204、窗层206和封装件基底101执行切割工艺。切割工艺可以切割模制坝204、窗层206和封装件基底101中的每个的定位在半导体芯片201之间的部分。切割工艺可以部分地切割模制坝204和窗层206中的每个的边缘，并且也部分地切割封装件基底101的与模制坝204和窗层206的边缘叠置的边缘。切割工艺可以在一对相邻的半导体芯片201之间形成凹槽H，并且一对相邻的凹槽H可以在它们之间限定单元半导体封装件占据的区域。切割工艺可以将模制坝204和窗层206中的每个分成多块。
可以在窗层206上设置功能层207以及位于功能层207上的垫层208。
功能层207可以是电磁屏蔽层。功能层207可以包括导电聚合物207a和粘合剂聚合物207b，如图1B中所示。功能层207还可以包括导电填料207c，如图1B中所示。可以将导电聚合物207a、粘合剂聚合物207b和导电填料207c不规则地布置在功能层207中。
参照图5C，可以对功能层207和垫层208进行处理以填充凹槽H并覆盖模制坝204和窗层206。例如，功能层207可以共形地覆盖窗层206的顶表面、模制坝204的侧表面和凹槽H的底板表面。垫层208可以覆盖功能层207并填充凹槽H。可以执行压制工艺以使功能层207和垫层208填充凹槽H并覆盖窗层206和模制坝204的表面。
参照图5D，可以从功能层207去除垫层208。功能层207可以保留在凹槽H的底板表面上以及窗层206和模制坝204的表面上。在去除垫层208之后，可以对功能层207执行固化工艺。
参照图5E，可以在凹槽H内执行封装件切单工艺(切锯或分选)，从而形成多个半导体封装件。如果在执行切割工艺时封装件基底101具有非切割部分，则封装件切单工艺(切锯或分选)可以完全切割封装件基底101的非切割部分。
图6示出了显示根据发明构思的示例实施例的制造半导体封装件的方法的剖视图。
为了简化描述，与参照图4A至图4E以及图5A至图5E所讨论的组件相同或基本相似的组件分配了与参照图4A至图4E以及图5A至图5E所讨论的组件的附图标记相同的附图标记，并且将省略它们的重复说明。
参照图6，可以在封装件基底101的第一顶表面1上设置多个第一半导体芯片201，同时多个半导体芯片201以规则的间距彼此间隔开。可以通过第一粘合层202将每个第一半导体芯片201粘附到封装件基底101上。例如，第一半导体芯片201可以是半导体逻辑芯片、半导体存储器芯片、芯片上系统(SOC)或芯片上实验室(LOC)。可以在封装件基底101与每个第一半导体芯片201之间设置多条结合布线203。
可以在第一半导体芯片201的顶表面上设置多个第二半导体芯片209。可以通过第二粘合层210将每个第二半导体芯片209粘附到第一半导体芯片201的顶表面。例如，第二半导体芯片209可以是光发射芯片、光学传感器芯片或芯片上实验室(LOC)。可以在封装件基底101与每个第二半导体芯片209之间设置多条结合布线203。
虽然未示出，但还可以在第一半导体芯片201与第二半导体芯片209之间设置其它半导体芯片。
可以在封装件基底101的第一顶表面1上形成模制坝204。
可以在模制坝204以及第一半导体芯片201和第二半导体芯片209上设置窗层206。
与参照图5B至图5E所讨论的那些相同或相似，功能层207可以覆盖模制坝204的表面和窗层206的表面，并且可以制造多个半导体封装件。
图7A至图7C示出了显示根据发明构思的示例实施例的制造半导体模块的方法的剖视图。
为了简化描述，与参照图4A至图4E所讨论的组件相同或基本相似的组件分配了与参照图4A至图4E所讨论的组件的附图标记相同的附图标记，并且将省略它们的重复说明。
参照图7A，可以在模块基底300上设置组件411、第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c。模块基底300可以是具有电路图案的印刷电路板(PCB)，或者可以包括具有电路图案的印刷电路板(PCB)。在模块基底300上设置第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c可以包括：在第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c的有源表面上执行焊接工艺以形成焊球407；使模块基底300在其上接收第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c，在第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c上形成有焊球407；以及在模块基底300与第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c之间的空间中形成第一底部填充树脂层409。第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c可以具有彼此不同的高度。第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c中的每个可以是半导体逻辑芯片、半导体存储器芯片、芯片上系统(SOC)或芯片上实验室(LOC)。例如，可以由底部填充材料形成第一底部填充树脂层409。
可以利用设置在组件411与模块基底300之间的粘合层413使组件411附着到模块基底300。第二底部填充树脂层415可以在组件411与模块基底300之间的空间中围绕粘合层413。在一些示例实施例中，可以将组件411焊接到模块基底300上。组件411可以具有与第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c的高度不同的高度。组件411可以被电阻器、电感器、变压器、无源器件或其它电子器件取代。第二底部填充树脂层415可以由例如底部填充材料形成。
可以在模块基底300的顶表面、第一半导体芯片401a、第二半导体芯片401b、第三半导体芯片401c和组件411上设置功能层207和位于功能层207上的垫层208。
功能层207可以是电磁屏蔽层。功能层207可以包括导电聚合物207a和粘合剂聚合物207b，如图1B中所示。功能层207还可以包括导电填料207c，如图1B中所示。导电聚合物207a、粘合剂聚合物207b和导电填料207c可以被不规则地布置在功能层207中。
参照图7B，可以对功能层207和垫层208进行处理以覆盖第一半导体芯片401a、第二半导体芯片401b、第三半导体芯片401c、组件411、第一底部填充树脂层409和第二底部填充树脂层415，并且也填充第一空间S1、第二空间S2和第三空间S3。
例如，功能层207可以共形地覆盖第一半导体芯片401a的顶表面和侧表面、第二半导体芯片401b的顶表面和侧表面、第三半导体芯片401c的顶表面和侧表面、组件411的顶表面和侧表面、第一底部填充树脂层409的表面以及第二底部填充树脂层415的表面。功能层207也可以覆盖模块基底300的顶表面的暴露在第一半导体芯片401a与第二半导体芯片401b之间的部分(例如，第一空间S1)、模块基底300的顶表面的暴露在第一半导体芯片401a与组件411之间的部分(例如，第二空间S2)以及模块基底300的顶表面的暴露在组件411与第三半导体芯片401c之间的部分(例如，第三空间S3)。垫层208可以覆盖功能层207，并填充第一空间S1、第二空间S2和第三空间S3。
可以执行压制工艺以使功能层207和垫层208覆盖第一半导体芯片401a、第二半导体芯片401b、第三半导体芯片401c和组件411，并且也填充第一空间S1、第二空间S2和第三空间S3。第一空间S1、第二空间S2和第三空间S3中的每个可以具有等于或小于大约5的高宽比。
参照图7C，可以从功能层207去除垫层208。功能层207可以保留在第一半导体芯片401a的表面、第二半导体芯片401b的表面、第三半导体芯片401c的表面、组件411的表面、第一底部填充树脂层409的表面、第二底部填充树脂层415的表面以及模块基底300的暴露于第一空间S1、第二空间S2和第三空间S3的顶表面上。
根据发明构思的一些示例实施例，功能层207可以被形成为覆盖第一半导体芯片401a的表面、第二半导体芯片401b的表面、第三半导体芯片401c的表面以及组件411的表面，同时，共形地覆盖位于组件411与第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c之中的第一空间S1、第二空间S2和第三空间S3的底板表面，从而使处理时间减少。
图8示出了显示根据发明构思的示例实施例的制造半导体模块的方法的剖视图。
为了简化描述，与参照图4A至图4E以及图7A至图7C所讨论的组件相同或基本相似的组件分配了与参照图4A至图4E以及图7A至图7C所讨论的组件的附图标记相同的附图标记，并且将省略它们的重复说明。
参照图8，可以在模块基底300上设置组件411、第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c。第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c中的每个可以是发光芯片、光学传感器芯片或芯片上实验室(LOC)。
可以在模块基底300的顶表面上形成模制坝422。模制坝422可以从模块基底300的边缘的顶表面向上延伸。当在平面图中观看时，模制坝422可以围绕组件411、第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c。
可以在模制坝422、第一半导体芯片401a、第二半导体芯片401b、第三半导体芯片401c和组件411上设置窗层421。模制坝422可以支撑窗层421。窗层421可以与组件411间隔开，并且与第一半导体芯片401a、第二半导体芯片401b和第三半导体芯片401c间隔开。窗层421可以是透明的。例如，窗层421可以包括玻璃。
可以在模制坝422和窗层421上设置功能层207，并且可以在功能层207上设置垫层208。与参照图7B和图7C所讨论的那些相同或相似，功能层207可以覆盖模块基底300的顶表面、窗层421和模制坝422。
根据发明构思，半导体封装件可以包括功能层，该功能层屏蔽电磁波并且使半导体封装件以低成本制造且具有较小的厚度，从而减少环境和残留问题。
此外，功能层可以是透明的，使得可以可视地识别在半导体芯片上显示的标记。
虽然已经结合附图中示出的发明构思的一些示例实施例描述了本发明构思，但是本领域技术人员将理解的是，在不脱离发明构思的技术精神和必要特征的情况下，可以进行各种改变和修改。对于本领域技术人员而言将明显的是，在不脱离发明构思的范围和精神的情况下，可以对其进行各种替换、修改和改变。

Claims (20)

1.一种半导体封装件，所述半导体封装件包括：
封装件基底，包括绝缘层和接地层，接地层在绝缘层中纵向延伸，接地层的端部部分被绝缘层暴露；
半导体芯片，位于封装件基底上；
模制层，位于封装件基底上，并至少围绕半导体芯片的侧表面；以及
电磁屏蔽层，覆盖模制层和半导体芯片，电磁屏蔽层的端部部分与接地层的端部部分平行地延伸并与接地层的端部部分接触，电磁屏蔽层包括第一侧部分和第二侧部分，第一侧部分面对半导体芯片的侧表面，第二侧部分位于电磁屏蔽层的端部处并与第一侧部分水平地间隔开，电磁屏蔽层的第二侧部分与接地层的侧端部表面位于直线上并暴露于封装件基底的外部。
2.根据权利要求1所述的半导体封装件，其中，电磁屏蔽层是透明层。
3.根据权利要求1所述的半导体封装件，其中，电磁屏蔽层具有90％或更高的可见光透射率。
4.根据权利要求1所述的半导体封装件，其中，电磁屏蔽层包括导电聚合物和粘合剂聚合物。
5.根据权利要求4所述的半导体封装件，其中，导电聚合物具有在500S/cm与2000S/cm之间的导电率。
6.根据权利要求4所述的半导体封装件，其中，导电聚合物具有等于或高于90％的可见光透射率。
7.根据权利要求4所述的半导体封装件，其中，导电聚合物包括聚(3,4-乙撑二氧噻吩)、聚(3,4-乙撑二氧噻吩):聚苯乙烯磺酸钠和聚(4,4-二辛基环戊二噻吩)中的一种或更多种。
8.根据权利要求4所述的半导体封装件，其中，粘合剂聚合物包括丙烯酸聚合物类介孔和丙烯酸微乳液中的至少一种。
9.根据权利要求4所述的半导体封装件，其中，粘合剂聚合物包括光引发剂。
10.根据权利要求4所述的半导体封装件，其中，电磁屏蔽层还包括导电填料。
11.根据权利要求10所述的半导体封装件，其中，导电填料包括透明导电氧化物。
12.根据权利要求10所述的半导体封装件，其中，导电填料包括无机材料或包括有机材料，无机材料包括氧化铟锌、氧化铟锡和氧化铝锌中的至少一种，有机材料包括碳纳米管和石墨烯中的至少一种。
13.一种半导体封装件，所述半导体封装件包括：
封装件基底，包括绝缘层和接地层，接地层在绝缘层中纵向延伸，接地层的端部部分被绝缘层暴露；
半导体芯片，位于封装件基底上；
模制坝，从封装件基底的顶表面向上延伸，模制坝与半导体芯片水平地间隔开；
窗层，由模制坝支撑，窗层和模制坝包围封装件基底上的半导体芯片，窗层是透明的；以及
电磁屏蔽层，覆盖模制坝和窗层，电磁屏蔽层包括与接地层的暴露的端部部分平行地延伸并与接地层的暴露的端部部分接触的端部部分，电磁屏蔽层还包括第一侧部分和第二侧部分，第一侧部分面对半导体芯片的侧表面，第二侧部分位于电磁屏蔽层的端部处并与第一侧部分水平地间隔开，电磁屏蔽层的第二侧部分与接地层的侧端部表面位于直线上并暴露于封装件基底的外部。
14.根据权利要求13所述的半导体封装件，其中，模制坝的顶表面位于比半导体芯片的顶部高的位置处。
15.根据权利要求13所述的半导体封装件，其中，当在剖面中观看时，模制坝的宽度比封装件基底的宽度小，模制坝的宽度为模制坝的两个外侧壁之间的距离。
16.根据权利要求13所述的半导体封装件，其中，电磁屏蔽层是透明层，半导体芯片上的标记通过电磁屏蔽层是可见的。
17.根据权利要求16所述的半导体封装件，其中，电磁屏蔽层包括导电聚合物和粘合剂聚合物。
18.根据权利要求17所述的半导体封装件，其中，电磁屏蔽层还包括导电填料。
19.一种半导体模块，所述半导体模块包括：
模块基底；
多个电子组件，位于模块基底上，电子组件包括一个或更多个半导体芯片；
多个底部填充树脂层，位于模块基底与多个电子组件中的各个电子组件之间；以及
电磁屏蔽层，覆盖电子组件的顶表面和侧表面以及所述多个底部填充树脂层的侧表面，电磁屏蔽层包括：多个上部，位于所述多个电子组件的各个顶表面上；多个第一侧部分，位于所述多个电子组件的各个侧表面上；多个第二侧部分，位于所述多个底部填充树脂层的各个侧表面上；以及多个下部，位于模块基底的顶表面上，所述多个第一侧部分中的一个第一侧部分与所述多个第二侧部分中的一个第二侧部分的竖直连接对使所述多个上部中的相应一个上部与所述多个下部中的相应一个下部连接。
20.根据权利要求19所述的半导体模块，其中，所述多个电子组件中的各对电子组件之间的多个空间中的每个空间具有等于或小于5的高宽比，其中，高宽比指通过将所述多个空间中的每个空间的深度除以该空间的宽度而获得的值。
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