US20190281736A1 - Semiconductor package and semiconductor module - Google Patents
Semiconductor package and semiconductor module Download PDFInfo
- Publication number
- US20190281736A1 US20190281736A1 US16/131,596 US201816131596A US2019281736A1 US 20190281736 A1 US20190281736 A1 US 20190281736A1 US 201816131596 A US201816131596 A US 201816131596A US 2019281736 A1 US2019281736 A1 US 2019281736A1
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- US
- United States
- Prior art keywords
- layer
- semiconductor
- package substrate
- electromagnetic shield
- molding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- 239000004814 polyurethane Substances 0.000 description 2
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- 229910052719 titanium Inorganic materials 0.000 description 2
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- Inventive concepts relate to semiconductor packages and/or semiconductor modules, and more particularly, to semiconductor packages and/or a semiconductor modules that include a functional layer having transparency, adhesiveness, and high electrical conductivity.
- electromagnetic wave emission from semiconductor packages may cause problems with other nearby semiconductor packages.
- the electromagnetic interference may result in various malfunctions, operation abnormality, operation failure, etc.
- Some example embodiments of the inventive concepts provide semiconductor packages fabricated at a low cost, having a small thickness, and without environmental and residue issues.
- Some example embodiments of the inventive concepts provide semiconductor packages each including semiconductor chip, a mark on which has can be visually recognized.
- a semiconductor package may include a package substrate including an insulating layer and a ground layer, the ground layer longitudinally extending in the insulating layer, an end portion of the ground layer exposed by the insulating layer, a semiconductor chip on the package substrate, a molding layer on the package substrate and surrounding at least a side surface of the semiconductor chip, and an electromagnetic shield layer covering the molding layer and the semiconductor chip, an end portion of the electromagnetic shield layer running in parallel with and being in contact with the end portion of the ground layer, the electromagnetic shield layer including a first lateral portion and a second lateral portion, the first lateral portion facing the side surface of the semiconductor chip, a second lateral portion at an end of the electromagnetic shield layer and horizontally spaced apart from the first lateral portion, the second lateral portion of the electromagnetic shield layer and a lateral end surface of the ground layer being on a substantially straight line and exposed to outside of the package substrate
- a semiconductor package may include a package substrate including an insulating layer and a ground layer, the ground layer longitudinally extending in the insulating layer, an end portion of the ground layer exposed by the insulating layer, a semiconductor chip on the package substrate, a molding dam extending upward from a top surface of the package substrate, the molding dam horizontally spaced apart from the semiconductor chip, a window layer supported by the molding dam, the window layer and the molding dam enclosing the semiconductor chip on the package substrate, the window layer being transparent, and an electromagnetic shield layer covering the molding dam and the window layer, the electromagnetic shield layer including an end portion that runs in parallel with and is in contact with the exposed end portion of the ground layer, the electromagnetic shield layer further including a first lateral portion and a second lateral portion, the first lateral portion facing a side surface of the semiconductor chip, the second lateral portion at an end of the electromagnetic shield layer and horizontally spaced apart from the first lateral portion, the second lateral portion of the electromagnetic shield layer and a lateral end
- a semiconductor package may include a module substrate, a plurality of electronic components on the module substrate, the electronic components including one or more semiconductor chips, a plurality of under-fill resin layers between the module substrate and respective ones of the plurality of electronic components, and an electromagnetic shield layer covering top and side surfaces of the electronic components and lateral surface of the plurality of under-fill resin layers, the electromagnetic shield layer including a plurality of upper portions on respective top surfaces of the plurality of electronic components, a plurality of first lateral portions on respective side surfaces of the plurality of electronic components, a plurality of second lateral portions on respective lateral surface of the plurality of under-fill resin layers, and a plurality of lower portions on a top surface of the module substrate, a vertically connected pair of one of the plurality of first lateral portions and one of the plurality of second lateral portions connecting a corresponding one of the plurality of upper portions to a corresponding one of the plurality of lower portions.
- a semiconductor package prepared by a method may include providing a package substrate including an insulating layer and a ground layer longitudinally extending within the insulating layer, providing a plurality of semiconductor chips on a top surface of the package substrate to be spaced apart from each other, providing a molding layer on the package substrate to surround at least a side surface of the semiconductor chip and to have a substantially flat top surface, cutting a molding layer between the plurality of semiconductor chips until the ground layer in the package substrate is exposed such that a plurality of grooves are formed between neighboring ones of the plurality of semiconductor chips, sequentially providing an electromagnetic shield layer and a cushion layer on the molding layer and the semiconductor chips, processing the cushion layer and the electromagnetic shield layer (1) to cause the electromagnetic shield layer to conformally cover top and lateral surfaces of the molding layer and (2) to cause the cushion layer to fill the grooves, side and bottom surfaces of which are conformally covered by the electromagnetic shield layer, removing the cushion layer, and cutting the package substrate in the plurality of grooves to form individual semiconductor packages such that
- FIG. 1A illustrates a cross-sectional view showing a semiconductor package according to an example embodiment of the inventive concepts.
- FIG. 1B illustrates an enlarged view showing section A of FIG. 1A .
- FIG. 2A illustrates a cross-sectional view showing a semiconductor package according to an example embodiment of the inventive concepts.
- FIG. 2B illustrates a cross-sectional view showing a semiconductor package according to an example embodiment of the inventive concepts.
- FIG. 3A illustrates a cross-sectional view showing a semiconductor module according to an example embodiment of the inventive concepts.
- FIG. 3B illustrates a cross-sectional view showing a semiconductor module according to an example embodiment of the inventive concepts.
- FIGS. 4A to 4E illustrate cross-sectional views showing a method of fabricating a semiconductor package according to an example embodiment of the inventive concepts.
- FIGS. 5A to 5E illustrate cross-sectional views showing a method of fabricating a semiconductor package according to an example embodiment of the inventive concepts.
- FIG. 6 illustrates a cross-sectional view showing a method of fabricating a semiconductor package according to an example embodiment of the inventive concepts.
- FIGS. 7A to 7C illustrate cross-sectional views showing a method of fabricating a semiconductor module according to an example embodiment of the inventive concepts.
- FIG. 8 illustrates a cross-sectional view showing a method of fabricating a semiconductor module according to an example embodiment of the inventive concepts.
- FIG. 1A illustrates a cross-sectional view showing a semiconductor package according to an example embodiment of the inventive concepts.
- FIG. 1B illustrates an enlarged view showing section A of FIG. 1A .
- a semiconductor package 1000 may include a package substrate 101 , external terminals 105 , a semiconductor chip 201 , bonding wires 203 , a molding layer 205 , and a functional layer 207 .
- the package substrate 101 may be or include a printed circuit board (PCB) with a circuit pattern.
- the package substrate 101 may include a first region 10 and a second region 20 .
- the second region 20 of the package substrate 101 may surround the first region 10 of the package substrate 101 .
- the package substrate 101 may include a first top surface 1 , a second top surface 3 , and a bottom surface 2 .
- the package substrate 101 may be configured such that the first top surface 1 is positioned on the first region 10 and the second top surface 3 is positioned on the second region 20 .
- the second top surface 3 of the package substrate 101 may be located at a level different from that of the first top surface 1 of the package substrate 101 .
- the second top surface 3 of the package substrate 101 may be located at a level lower than that of the first top surface 1 of the package substrate 101 .
- the package substrate 101 may include a ground layer 103 and an insulating layer 107 .
- the ground layer 103 may longitudinally extend in the insulating layer 107 , and an end portion of the ground layer 103 may be exposed by the insulating layer 107 .
- the ground layer 103 may be disposed on both the first and second regions 10 and 20 of the package substrate 101 .
- the ground layer 103 may be disposed below first lateral surfaces 4 of the first region 10 of the package substrate 101 .
- the ground layer 103 may include a first segment RG 1 on the first region 10 and a second segment RG 2 on the second region 20 .
- the second segment RG 2 of the ground layer 103 may have a top surface (e.g., the second top surface 3 ) and second lateral surfaces 6 , which surfaces 3 and 6 may be exposed to outside the package substrate 101 .
- the second lateral surfaces 6 of the second segment RG 2 of the ground layer 103 may be exposed to outside the package substrate 101 , and the second top surface 3 of the second segment RG 2 of the ground layer 103 may not be exposed to outside the package substrate 101 .
- the second segment RG 2 of the ground layer 103 may be defined as a ground terminal.
- the ground layer 103 may include a conductive material.
- the conductive material may include a metallic material (e.g., silver (Ag), gold (Au), or copper (Cu)), a metal alloy (e.g., copper-silver (Cu-Ag), titanium-silver-copper (Ti-Ag-Cu), or copper-zinc (Cu-Zn)), or other electrically conductive materials.
- a metallic material e.g., silver (Ag), gold (Au), or copper (Cu)
- a metal alloy e.g., copper-silver (Cu-Ag), titanium-silver-copper (Ti-Ag-Cu), or copper-zinc (Cu-Zn)
- Cu-Zn copper-zinc
- the external terminals 105 may be disposed on the bottom surface 2 of the package substrate 101 .
- the external terminals 105 may be, but not limited to, a solder ball, a conductive bump, a conductive spacer, or a pin grid array.
- the ground layer 103 may be electrically connected to a specific one of the external terminals 105 .
- the specific external terminal 105 may be supplied with a ground voltage.
- the semiconductor chip 201 may be disposed on the first top surface 1 of the package substrate 101 .
- the semiconductor chip 201 may be placed on the first region 10 of the package substrate 101 .
- the semiconductor chip 201 may be adhered through an adhesive layer 202 onto the first top surface 1 of the package substrate 101 .
- the semiconductor chip 201 may be a semiconductor logic chip, a semiconductor memory chip, a system-on-chip (SOC), or a lab-on-chip (LOC).
- the semiconductor chip 201 and the package substrate 101 may be electrically connected to each other through the bonding wires 203 disposed therebetween.
- the bonding wires 203 may include, for example, one or more of gold (Au), silver (Ag), platinum (Pt), aluminum (Al), copper (Cu), palladium (Pd), nickel (Ni), cobalt (Co), chromium (Cr), and titanium (Ti).
- the semiconductor chip 201 may be mounted on the package substrate 101 in a flip-chip bonding manner or other possible manners.
- the molding layer 205 may be disposed on the first region 10 of the package substrate 101 .
- the molding layer 205 may cover the first top surface 1 of the first region 10 of the package substrate 101 .
- the molding layer 205 may have lateral surfaces aligned with the first lateral surfaces 4 of the first region 10 of the package substrate 101 .
- the molding layer 205 may surround at least a side surface of the semiconductor chip 201 .
- the molding layer may surround a side surface of the semiconductor chip 201 and cover a top surface of the semiconductor chip 201 .
- the molding layer 205 may have a width W 1 less than a width W 2 of the package substrate 101 (W 1 ⁇ W 2 ).
- the molding layer 205 may include an epoxy molding compound (EMC) or an under-fill material.
- EMC epoxy molding compound
- a mark (not shown) may be displayed on a top surface of the molding layer 205 .
- the mark may be or include one or more characters for expressing particular information.
- the molding layer 205 may be covered (coated) with the functional layer 207 that extends onto the first lateral surfaces 4 of the first region 10 of the package substrate 101 and onto the second top surface 3 of the second segment RG 2 of the ground layer 103 .
- the functional layer 207 may be in contact with the second top surface 3 of the second segment RG 2 of the ground layer 103 .
- the molding layer 205 may be covered with the functional layer 207 that extends onto the second lateral surfaces 6 of the second segment RG 2 of the ground layer 103 .
- the functional layer 207 may be in contact with the second lateral surfaces 6 of the second segment RG 2 of the ground layer 103 , while being not in contact with the second top surface 3 of the second segment RG 2 of the ground layer 103 .
- the functional layer 207 may have a uniform thickness.
- a portion of the functional layer 207 covering the molding layer 205 , a portion of the functional layer 207 covering the first lateral surfaces 4 of the first region 10 of the package substrate 101 , and a portion of the functional layer 207 covering the second top surface 3 of the second segment RG 2 of the ground layer 103 may have thicknesses that are substantially the same or substantially similar to each other.
- the functional layer 207 may have a thickness equal to or less than about 40 ⁇ m.
- the functional layer 207 may be an electromagnetic shield layer.
- the term “function layer” and “electromagnetic shield layer” may be interchangeably used throughout this disclosure.
- the functional layer 207 may cover the molding layer 205 and the semiconductor chip 201 .
- An end portion of the functional layer 207 may run in parallel with and is in contact with the end portion of the ground layer 103 .
- the functional layer 207 may include a first lateral portion that faces the side surface of the semiconductor chip 201 , and a second lateral portion that is provided at an end of the functional layer 207 and is horizontally spaced apart from the first lateral portion.
- the second lateral portion of the functional layer 207 and a lateral end surface of the ground layer 103 may be on a substantially straight line and exposed to outside of the package substrate.
- the functional layer 207 may be electrically connected to the ground layer 103 , and may provide an electrical path for grounding electromagnetic waves incident on the functional layer 207 .
- the functional layer 207 may include a conductive polymer 207 a and an adhesive polymer 207 b .
- the conductive polymer 207 a may have a relatively high electrical conductivity.
- the conductive polymer 207 a may have an electrical conductivity ranging from about 500 S/cm to about 2,000 S/cm.
- the conductive polymer 207 a may be transparent.
- the conductive polymer 207 a may have a visible light transmittance equal to or higher than about 90%.
- the conductive polymer 207 a may include one or more of poly(3,4-ethylenedioxythiophene) (PEDOT), poly(3,4-ethylenedioxythiophene) (PEDOT):sodium poly-styrenesulfonate (PSS), and poly(4,4-dioctyl cyclopentadithiophene).
- the adhesive polymer 207 b may have a relatively high adhesiveness.
- the adhesive polymer 207 b may be transparent.
- the adhesive polymer 207 b may have a visible light transmittance equal to or higher than about 90%.
- the adhesive polymer 207 b may include one or more of acrylic polymer based mesoporous or acrylic microemulsion.
- the adhesive polymer 207 b may include a photo-initiator. The photo-initiator may accelerate a cross-linking reaction of the adhesive polymer 207 b when a curing process is performed.
- the functional layer 207 may further include a conductive filler 207 c .
- the conductive filler 207 c may have an electrical conductivity greater than that of the conductive polymer 207 a .
- the conductive filler 207 c may have an electrical conductivity ranging from about 5,000 S/cm to about 20,000 S/cm.
- the conductive filler 207 c may be transparent.
- the conductive filler 207 c may have a visible light transmittance equal to or higher than about 90%.
- the conductive filler 207 c may include a transparent conductive oxide (TCO).
- the conductive filler 207 c may be an inorganic material including one or more of indium zinc oxide (IZO), indium tin oxide (ITO), and aluminum zinc oxide (AZO).
- the conductive filler 207 c may be an organic material including one or more of carbon nanotube (CNT) and graphene. Because the functional layer 207 further includes the conductive filler 207 c , the functional layer 207 may increase in electrical conductivity. In some example embodiments, the conductive filler 207 c may have a flake shape.
- the conductive polymer 207 a , the adhesive polymer 207 b , and the conductive filler 207 c may be irregularly arranged in the functional layer 207 .
- the functional layer 207 includes the conductive polymer 207 a , the adhesive polymer 207 b , and the conductive filler 207 c , electrical conductivity and adhesiveness of the functional layer 207 may increase.
- the functional layer 207 may serve as a ground path for electromagnetic waves, and may be adhered to the molding layer 205 and the ground layer 103 without separately providing an adhesive.
- the functional layer 207 may be transparent. Thus, even when the functional layer 207 covers the molding layer 205 , the mark printed on the top surface of the molding layer 205 may be visually recognized.
- the functional layer 207 may cause the semiconductor package 1000 to be fabricated at a lower cost and/or to have a smaller thickness.
- the semiconductor package 1000 may have no metallic material for shielding electromagnetic waves, thereby resulting in reduction of environmental and residue issues.
- FIG. 2A illustrates a cross-sectional view showing a semiconductor package according to an example embodiment of the inventive concepts.
- a semiconductor package 1000 may include a package substrate 101 , external terminals 105 , a semiconductor chip 201 , bonding wires 203 , a molding dam 204 , a window layer 206 , and a functional layer 207 .
- the package substrate 101 may be or include a printed circuit board (PCB) with a circuit pattern.
- the package substrate 101 may include a ground layer 103 and an insulating layer 107 .
- the ground layer 103 may longitudinally extend in the insulating layer 107 , and an end portion of the ground layer 103 may be exposed by the insulating layer 107 .
- the external terminals 105 may be disposed on a bottom surface 2 of the package substrate 101 .
- the semiconductor chip 201 may be disposed on a first top surface 1 of the package substrate 101 .
- the semiconductor chip 201 may be adhered through an adhesive layer 202 onto the first top surface 1 of the package substrate 101 .
- the semiconductor chip 201 may be a light emitting chip, an optical sensor chip, or a lab-on-chip (LOC).
- LOC lab-on-chip
- the semiconductor chip 201 and the package substrate 101 may be electrically connected to each other through the bonding wires 203 disposed therebetween.
- the molding dam 204 may be disposed on a first region 10 of the package substrate 101 .
- the molding dam 204 may be vertically under the functional layer 207 , and may be horizontally within the functional layer 207 .
- the molding dam 204 may extend upward from an edge of the first top surface 1 of the first region 10 of the package substrate 101 .
- the molding dam 204 may have lateral surfaces aligned with first lateral surfaces 4 of the first region 10 of the package substrate 101 .
- the molding dam 204 may be horizontally spaced apart from the semiconductor chip 201 . When viewed in plan, the molding dam 204 may surround a side surface of the semiconductor chip 201 .
- the molding dam 204 may have a width W 3 less than a width W 2 of the package substrate 101 (W 3 ⁇ W 2 ).
- a distance W 3 between a left outer wall and a right outer wall of the molding dam 204 when viewed in a cross-section, may be smaller than the width W 2 of the package substrate 101 .
- the top surface of the molding dam 204 may be at a higher level or position than a top of the semiconductor chip 201 .
- the window layer 206 may be disposed on the molding dam 204 and the semiconductor chip 201 .
- the molding dam 204 may support the window layer 206 .
- the window layer 206 may be spaced apart from the semiconductor chip 201 .
- the window layer 206 and the molding dam 204 may enclose the semiconductor chip 201 on the package substrate 101 .
- the window layer 206 may be transparent.
- the window layer 206 may include glass.
- a cavity C may be defined by the first top surface 1 , the molding dam 204 , and the window layer 206 .
- the cavity C may be an empty space surrounded by the first top surface 1 , the molding dam 204 , and the window layer 206 .
- the semiconductor chip 201 may be disposed in the cavity C.
- the molding dam 204 and the window layer 206 may be covered with the functional layer 207 that extends onto the first lateral surfaces 4 of the first region 10 of the package substrate 101 and onto a second top surface 3 of a second segment RG 2 of the ground layer 103 .
- the functional layer 207 may include an end portion that runs in parallel with and is in contact with the exposed end portion of the ground layer 103 .
- the functional layer 207 may include a first lateral portion that faces a side surface of the semiconductor chip 201 and a second lateral portion that is provided at an end of the functional layer 207 and is horizontally spaced apart from the first lateral portion.
- the second lateral portion of the functional layer 207 and a lateral end surface of the ground layer 103 may be on a substantially straight line and be exposed to outside of the package substrate 101 .
- the molding dam 204 and the window layer 206 may be covered with the functional layer 207 that extends onto second lateral surfaces 6 of the second segment RG 2 of the ground layer 103 while providing the functional layer 207 to be in contact with the ground layer 103 .
- the functional layer 207 may include a conductive polymer 207 a and an adhesive polymer 207 b , as illustrated in FIG. 1B .
- the functional layer 207 may further include a conductive filler 207 c , as illustrated in FIG. 1B .
- the functional layer 207 includes the conductive polymer 207 a , the adhesive polymer 207 b , and the conductive filler 207 c , electrical conductivity and adhesiveness of the functional layer 207 may increase.
- the functional layer 207 may serve as a ground path for electromagnetic waves, and may be adhered to the molding dam 204 , the window layer 206 , and the ground layer 103 without separately providing an adhesive.
- the window layer 206 and the functional layer 207 may be transparent. Therefore, in the case where the semiconductor chip 201 is a light emitting chip, light emitted from the semiconductor chip 201 may be radiated outward through the window layer 206 and the functional layer 207 . In the case where the semiconductor chip 201 is an optical sensor chip, the semiconductor chip 201 may receive external light through the window layer 206 and the functional layer 207 .
- FIG. 2B illustrates a cross-sectional view showing a semiconductor package according to an example embodiment of the inventive concepts.
- a semiconductor package 1000 may include a package substrate 101 , external terminals 105 , a first semiconductor chip 201 , a second semiconductor chip 209 , bonding wires 203 , a molding dam 204 , a window layer 206 , and a functional layer 207 .
- the first semiconductor chip 201 may be disposed on a first top surface 1 of the package substrate 101 .
- the first semiconductor chip 201 may be adhered through a first adhesive layer 202 onto the first top surface 1 of the package substrate 101 .
- the first semiconductor chip 201 may be a semiconductor logic chip, a semiconductor memory chip, a system-on-chip (SOC), or a lab-on-chip (LOC).
- the first semiconductor chip 201 and the package substrate 101 may be electrically connected to each other through the bonding wires 203 disposed therebetween.
- the second semiconductor chip 209 may be disposed on a top surface of the first semiconductor chip 201 .
- the second semiconductor chip 209 may be adhered through a second adhesive layer 210 to the top surface of the first semiconductor chip 201 .
- the second semiconductor chip 209 may be a light emitting chip, an optical sensor chip, or a lab-on-chip (LOC).
- LOC lab-on-chip
- the second semiconductor chip 209 and the package substrate 101 may be electrically connected to each other through the bonding wires 203 disposed therebetween.
- the semiconductor package 1000 may further include other semiconductor chips between the first and second semiconductor chips 201 and 209 .
- FIG. 3A illustrates a cross-sectional view showing a semiconductor module according to an example embodiment of the inventive concepts.
- a semiconductor module 2000 may include a module substrate 300 , and a first semiconductor chip 401 a , a second semiconductor chip 401 b , a third semiconductor chip 401 c , a component 411 , and a functional layer 207 on the module substrate 300 .
- the first semiconductor chip 401 a , the second semiconductor chip 401 b , the third semiconductor chip 401 c , and the component 411 may be collectively referred to as a plurality of electronic components.
- the module substrate 300 may be or include a printed circuit board (PCB) with a circuit pattern.
- the first, second, and third semiconductor chips 401 a , 401 b , and 401 c may be disposed on the module substrate 300 .
- the first, second, and third semiconductor chips 401 a , 401 b , and 401 c may have different heights from each other.
- Each of the first, second, and third semiconductor chips 401 a , 401 b , and 401 c may be a semiconductor logic chip, a semiconductor memory chip, a system-on-chip (SOC), or a lab-on-chip (LOC).
- SOC system-on-chip
- LOC lab-on-chip
- a plurality of solder balls 407 may be disposed between the module substrate 300 and each of the first, second, and third semiconductor chips 401 a , 401 b , and 401 c .
- the solder balls 407 may electrically connect between the module substrate 300 and each of the first, second, and third semiconductor chips 401 a , 401 b , and 401 c .
- a first under-fill resin layer 409 may be disposed within a gap between the module substrate 300 and each of the first, second, and third semiconductor chips 401 a , 401 b , and 401 c .
- the first under-fill resin layer 409 may surround surfaces of the solder balls 407 .
- the first under-fill resin layer 409 may include an under-fill material.
- the component 411 may be disposed on the module substrate 300 .
- the component 411 may be disposed between the first semiconductor chip 401 a and the third semiconductor chip 401 c .
- the position of the component 411 is not limited to the above, but may be variously changed.
- the component 411 may be adhered through an adhesive layer 413 onto the module substrate 300 .
- the component 411 may be replaced with a resistor, an inductor, a transformer, a passive device, or other electrical devices.
- the component 411 may have a height different from those of the first, second, and third semiconductor chips 401 a , 401 b , and 401 c .
- a second under-fill resin layer 415 may be disposed between the component 411 and the module substrate 300 , and may surround the adhesive layer 413 .
- the functional layer 207 may extend onto a top surface of the module substrate 300 , while covering the first, second, and third semiconductor chips 401 a , 401 b , and 401 c , lateral surfaces of a plurality of first under-fill resin layers 409 , the component 411 , and a lateral surface of the second under-fill resin layer 415 .
- the functional layer 207 may cover top and lateral surfaces of the first, second, and third semiconductor chips 401 a , 401 b , and 401 c , surfaces of the plurality of first under-fill resin layers 409 , and a surface of the second under-fill resin layer 415 .
- the functional layer 207 may also cover top and lateral surfaces of the component 411 .
- the functional layer 207 may extend onto a top surface of the module substrate 300 exposed to a first space S 1 between the first and second semiconductor chips 401 a and 401 b and onto a top surface of the module substrate 300 exposed to a second space S 2 between the component 411 and the first semiconductor chip 401 a .
- the functional layer 207 may extend onto a top surface of the module substrate 300 exposed to a third space S 3 between the third semiconductor chip 401 c and the component 411 .
- the functional layer 207 may include a plurality of upper portions on respective top surfaces of the plurality of electronic components, a plurality of first lateral portions on respective side surfaces of the plurality of electronic components, a plurality of second lateral portions on respective lateral surface of the plurality of under-fill resin layers, and a plurality of lower portions on a top surface of the module substrate.
- a vertically connected pair of one of the plurality of first lateral portions and one of the plurality of second lateral portions may connect a corresponding one of the plurality of upper portions to a corresponding one of the plurality of lower portions.
- the functional layer 207 may include a conductive polymer 207 a and an adhesive polymer 207 b , as illustrated in FIG. 1B .
- the functional layer 207 may further include a conductive filler 207 c , as illustrated in FIG. 1B .
- a thickness of a portion of the functional layer 207 covering the top surface of the module substrate 300 may be the same as or substantially similar to a thickness of each of portions of the functional layer 207 covering the first, second, and third semiconductor chips 401 a , 401 b , and to 401 c , the plurality of first under-fill resin layers 409 , the component 411 , and the second under-fill resin layer 415 .
- the functional layer 207 may have a thickness equal to or less than about 40 ⁇ m.
- Each of the first, second, and third spaces S 1 , S 2 , and S 3 may have an aspect ratio equal to or less than about 5.
- the aspect ratio may correspond to a value obtained by dividing a depth (or height) of each of the first, second, and third spaces S 1 , S 2 , and S 3 by a width of the each of the first, second, and third spaces S 1 , S 2 , and S 3 .
- FIG. 3B illustrates a cross-sectional view showing a semiconductor module according to an example embodiment of the inventive concepts.
- a semiconductor module 2000 may include a module substrate 300 , a first semiconductor chip 401 a , a second semiconductor chip 401 b , a third semiconductor chip 401 c , a component 411 , a functional layer 207 , a molding dam 422 , and a window layer 421 .
- the first, second, and third semiconductor chips 401 a , 401 b , and 401 c may be disposed on the module substrate 300 .
- Each of the first, second, and third semiconductor chips 401 a , 401 b , and 401 c may be a light emitting chip, an optical sensor chip, or a lab-on-chip (LOC).
- LOC lab-on-chip
- the component 411 may be disposed on the module substrate 300 .
- the molding dam 422 may be disposed on the module substrate 300 .
- the molding dam 422 may extend upward from a top surface of the module substrate 300 .
- the molding dam 422 may be spaced apart from the component 411 and from the first, second, and third semiconductor chips 401 a , 401 b , and 401 c .
- the molding dam 422 may surround the component 411 and the first, second, and third semiconductor chips 401 a , 401 b , and 401 c.
- the window layer 421 may be disposed on the molding dam 422 , the component 411 , and the first, second, and third semiconductor chips 401 a , 401 b , and 401 c .
- the molding dam 422 may support the window layer 421 .
- the window layer 421 may be spaced apart from the component 411 and from the first, second, and third semiconductor chips 401 a , 401 b , and 401 c .
- the window layer 421 may be transparent.
- the window layer 421 may include glass.
- the molding dam 422 and the window layer 421 may be covered with the functional layer 207 that extends onto a top surface of an edge of the module substrate 300 .
- the functional layer 207 may cover a top surface of the window layer 421 , a lateral surface of the molding dam 422 , and the top surface of an edge of the module substrate 300 .
- FIGS. 4A to 4E illustrate cross-sectional views showing a method of fabricating a semiconductor package according to an example embodiment of the inventive concepts.
- a package substrate 101 may include a first top surface 1 and a bottom surface 2 .
- the package substrate 101 may be or include a printed circuit board (PCB) with a circuit pattern.
- the package substrate 101 may include a ground layer 103 .
- the ground layer 103 may be disposed within the package substrate 101 .
- the ground layer 103 may include a conductive material.
- the conductive material may include a metallic material (e.g., silver (Ag), gold (Au), or copper (Cu)), a metal alloy (e.g., copper-silver (Cu-Ag), titanium-silver-copper (Ti-Ag-Cu), or copper-zinc (Cu-Zn)), or other electrically conductive materials.
- a plurality of semiconductor chips 201 may be provided on the first top surface 1 of the package substrate 101 , while being spaced apart from each other, for example, at a regular interval. Each of the semiconductor chips 201 may be adhered through an adhesive layer 202 onto the package substrate 101 .
- the semiconductor chips 201 may be a semiconductor logic chip, a semiconductor memory chip, a system-on-chip (SOC), or a lab-on-chip (LOC).
- a plurality of bonding wires 203 may be disposed between the package substrate 101 and each of the semiconductor chips 201 .
- the bonding wires 203 may electrically connect the semiconductor chip 201 to the package substrate 101 .
- the bonding wires 203 may be formed of one or more of gold (Au), silver (Ag), platinum (Pt), aluminum (Al), copper (Cu), palladium (Pd), nickel (Ni), cobalt (Co), chromium (Cr), and titanium (Ti).
- a molding layer 205 may be formed on the first top surface 1 of the package substrate 101 .
- the molding layer 205 may cover the semiconductor chips 201 .
- the molding layer 205 may be formed of an epoxy molding compound (EMC) or an under-fill material.
- EMC epoxy molding compound
- a plurality of external terminals 105 may be formed on the bottom surface 2 of the package substrate 101 . In the case where the external terminals 105 are solder balls, a soldering process may be performed to form the external terminals 105 on the bottom surface 2 of the package substrate 101 .
- a cutting process may be performed on the molding layer 205 and the package substrate 101 .
- the cutting process may partially cut the molding layer 205 between the semiconductor chips 201 and the package substrate 101 between the semiconductor chips 201 .
- the cutting process may partially cut an edge of the molding layer 205 and an edge of the package substrate 101 overlapping the edge of the molding layer 205 .
- the cutting process may form a groove H between a pair of neighboring semiconductor chips 201 .
- the cutting process may form a groove H between a first edge of the molding layer 205 and an edge of the leftmost one of the semiconductor chips 201 .
- the cutting process may form a groove H between a second edge of the molding layer 205 that is opposite to the first edge of the molding layer 205 and an edge of the rightmost one of the semiconductor chips 201 .
- a pair of neighboring grooves H may define therebetween a region where a unit semiconductor package occupies.
- the groove H may have a floor surface lower than the first top surface 1 of the package substrate 101 .
- the groove H may have an aspect ratio equal to or less than about 5.
- the aspect ratio may correspond to a value obtained by dividing a depth (or height) of the groove H by a width of the groove H.
- the cutting process may separate the molding layer 205 into a plurality of pieces. The cutting process may continue until the ground layer 103 is exposed. After the cutting process, the ground layer 103 may be partially exposed to the groove H.
- a functional layer 207 may be provided on the molding layer 205 , and a cushion layer 208 may be provided on the functional layer 207 .
- the functional layer 207 may be an electromagnetic shield layer.
- the functional layer 207 may include a conductive polymer 207 a and an adhesive polymer 207 b , as illustrated in FIG. 1B .
- the functional layer 207 may further include a conductive filler 207 c , as illustrate in FIG. 1B .
- the conductive polymer 207 a , the adhesive polymer 207 b , and the conductive filler 207 c may be melted in a solvent to form a liquefied composition.
- the solvent may include alcohol.
- the liquefied composition may be wet-coated to have a proper thickness, and then dried in an oven to evaporate the solvent from the liquefied composition. Therefore, the functional layer 207 may be formed to have the conductive polymer 207 a , the adhesive polymer 207 b , and the conductive filler 207 c that are in solid state.
- the functional layer 207 may have a thickness equal to or less than about 40 ⁇ m.
- the cushion layer 208 may have a thickness ranging from about 50 ⁇ m to about 400 ⁇ m.
- the cushion layer 208 may include a polyethylene-based polymer or a polyurethane-based polymer.
- the polyethylene-based polymer may include polymethylpentene (PMP), polyvinylchlodride (PVC), or polybutyleneterephthalate (PBT).
- the polyurethane-based polymer may include thermoplastic polyurethane (TPU).
- the functional layer 207 and the cushion layer 208 may be processed to cover the molding layers 205 and to fill the groove H.
- the functional layer 207 may conformally cover top and lateral surfaces of the molding layers 205 and the floor surface of the groove H.
- the cushion layer 208 may cover the functional layer 207 and fill the groove H.
- a press process may be performed to cause the functional layer 207 and the cushion layer 208 to cover the surfaces of the molding layers 205 and to fill the groove H.
- the press process may be performed such that the functional layer 207 and the cushion layer 208 are heated and pressed against the package substrate 101 for about 5 minutes to about 15 minutes in a state that the functional layer 207 and the cushion layer 208 are provided on the molding layers 205 .
- the press process may be performed under a pressure ranging from about 2 MPa to about 10 MPa at a temperature ranging from about 50° C. to about 150° C.
- the cushion layer 208 may have decreased elastic modulus due to the heat and pressure such that the groove H may be easily filled with the cushion layer 208 .
- the functional layer 207 may conformally cover the floor surface of the groove H and the lateral surfaces of the molding layers 205 .
- the cushion layer 208 may be removed from the functional layer 207 .
- the press process may expand the cushion layer 208 and reduce the elastic modulus of the cushion layer 208 , and therefore an external physical force may easily separate the cushion layer 208 from the functional layer 207 .
- the functional layer 207 may remain on the surfaces of the molding layers 205 and the floor surface of the groove H.
- a curing process may be performed on the functional layer 207 .
- the curing process may cure the functional layer 207 .
- the curing process may irradiate an ultraviolet ray to the functional layer 207 .
- the ultraviolet ray may have an intensity ranging from about 100 mJ to about 1,000 mJ.
- the ultraviolet ray may be irradiated for about 1 second to about 5 minutes.
- a photo-initiator of the adhesive polymer (see 207 b of FIG. 1B ) may accelerate a cross-linking process of the adhesive polymer 207 b .
- the cross-linking process may be accelerated when the photo-initiator is irradiated with an ultraviolet ray whose wavelength ranges from about 300 nm to about 600 nm.
- the functional layer 207 may conformally cover the top surfaces of the molding layers 205 , and at the same time, conformally cover the floor surface and sidewalls of the groove H.
- the formation of the functional layer 207 may be performed prior to a package singulation process, such as a sawing or sorting process. Therefore, a process tim may be reduced compared to the case where the functional layer 207 is formed on each of semiconductor packages after the package singulation process (sawing or sorting).
- a package singulation process may be performed within the groove H, thereby forming a plurality of semiconductor packages. If the package substrate 101 has a non-cut portion when the cutting process is performed, the package singulation process (sawing or sorting) may completely cut the non-cut portion of the package substrate 101 . For example, the package singulation process (sawing or sorting) may cut the package substrate 101 along a scribe line which has a width less than that of the groove H, thereby mitigating or preventing the functional layer 207 formed on the lateral surfaces of the molding layers 205 from being removed.
- FIGS. 5A to 5E illustrate cross-sectional views showing a method of fabricating a semiconductor package according to an example embodiment of the inventive concepts.
- a package substrate 101 may include a first top surface 1 and a bottom surface 2 .
- the package substrate 101 may include a ground layer 103 .
- a plurality of semiconductor chips 201 may be formed on the first top surface 1 of the package substrate 101 , while being spaced apart from each other at a regular interval. Each of the semiconductor chips 201 may be adhered through an adhesive layer 202 onto the package substrate 101 .
- the semiconductor chips 201 may be a light emitting chip, an optical sensor chip, or a lab-on-chip (LOC).
- LOC lab-on-chip
- a plurality of bonding wires 203 may be disposed between the package substrate 101 and each of the semiconductor chips 201 .
- a molding dam 204 may be formed on the first top surface 1 of the package substrate 101 .
- the molding dam 204 may extend upward from an edge of the first top surface 1 .
- the molding dam 204 may be spaced apart from each of the semiconductor chips 201 .
- the molding dam 204 may surround each of the semiconductor chips 201 .
- a window layer 206 may be disposed on the molding dam 204 and the semiconductor chips 201 .
- the molding dam 204 may support the window layer 206 .
- the window layer 206 may be spaced apart from each of the semiconductor chips 201 .
- the window layer 206 may be transparent.
- the window layer 206 may include glass.
- a plurality of cavities C may be defined by the first top surface 1 , the molding dam 204 , and the window layer 206 .
- the cavities C may be empty spaces surrounded by the first top surface 1 , the molding dam 204 , and the window layer 206 .
- Each of the cavities C may receive therein one semiconductor chip 201 .
- a plurality of external terminals 105 may be formed on the bottom surface 2 of the package substrate 101 .
- a cutting process may be performed on the molding dam 204 , the window layer 206 , and the package substrate 101 .
- the cutting process may cut a portion of each of the molding dam 204 , the window layer 206 , and the package substrate 101 , which is positioned between the semiconductor chips 201 .
- the cutting process may partially cut an edge of each of the molding dam 204 and the window layer 206 , and also partially cut an edge of the package substrate 101 overlapping the edges of the molding dam 204 and the window layer 206 .
- the cutting process may form a groove H between a pair of neighboring semiconductor chips 201 , and a pair of neighboring grooves H may define therebetween a region where a unit semiconductor package occupies.
- the cutting process may separate each of the molding dam 204 and the window layer 206 into a plurality of pieces.
- the window layer 206 may be provided thereon with a functional layer 207 and a cushion layer 208 on the functional layer 207 .
- the functional layer 207 may be an electromagnetic shield layer.
- the functional layer 207 may include a conductive polymer 207 a and an adhesive polymer 207 b , as illustrated in FIG. 1B .
- the functional layer 207 may further include a conductive filler 207 c , as illustrated in FIG. 1B .
- the conductive polymer 207 a , the adhesive polymer 207 b , and the conductive filler 207 c may be irregularly arranged in the functional layer 207 .
- the functional layer 207 and the cushion layer 208 may be processed to fill the groove H and to cover the molding dams 204 and the window layer 206 .
- the functional layer 207 may conformally cover top surfaces of the window layer 206 , lateral surfaces of the molding dams 204 , and a floor surface of the groove H.
- the cushion layer 208 may cover the functional layer 207 and fill the groove H.
- a press process may be performed to cause the functional layer 207 and the cushion layer 208 to fill the groove H and to cover the surfaces of the window layer 206 and the molding dams 204 .
- the cushion layer 208 may be removed from the functional layer 207 .
- the functional layer 207 may remain on the floor surface of the groove H and on the surfaces of the window layer 206 and the molding dams 204 .
- a curing process may be performed on the functional layer 207 .
- a package singulation process may be performed within the groove H, thereby forming a plurality of semiconductor packages. If the package substrate 101 has a non-cut portion when the cutting process is performed, the package singulation process (sawing or sorting) may completely cut the non-cut portion of the package substrate 101 .
- FIG. 6 illustrates a cross-sectional view showing a method of fabricating a semiconductor package according to an example embodiment of the inventive concepts.
- a plurality of first semiconductor chips 201 may be provided on a first top surface 1 of a package substrate 101 , while spaced apart from each other at a regular interval. Each of the first semiconductor chips 201 may be adhered through a first adhesive layer 202 onto the package substrate 101 .
- the first semiconductor chips 201 may be a semiconductor logic chip, a semiconductor memory chip, a system-on-chip (SOC), or a lab-on-chip (LOC).
- a plurality of bonding wires 203 may be disposed between the package substrate 101 and each of the first semiconductor chips 201 .
- a plurality of second semiconductor chips 209 may be disposed on top surfaces of the first semiconductor chip 201 . Each of the second semiconductor chips 209 may be adhered through a second adhesive layer 210 to the top surfaces of the first semiconductor chips 201 .
- the second semiconductor chips 209 may be a light emitting chip, an optical sensor chip, or a lab-on-chip (LOC).
- LOC lab-on-chip
- a plurality of bonding wires 203 may be disposed between the package substrate 101 and each of the second semiconductor chips 209 .
- semiconductor chips may further be disposed between the first and second semiconductor chips 201 and 209 .
- a molding dam 204 may be formed on the first top surface 1 of the package substrate 101 .
- a window layer 206 may be disposed on the molding dam 204 and the first and second semiconductor chips 201 and 209 .
- a functional layer 207 may cover surfaces of the molding dams 204 and surfaces of the window layer 206 , and a plurality of semiconductor packages may be fabricated
- FIGS. 7A to 7C illustrate cross-sectional views showing a method of fabricating a semiconductor module according to an example embodiment of the inventive concepts.
- a component 411 and first, second, and third semiconductor chips 401 a , 401 b , and 401 c may be provided on a module substrate 300 .
- the module substrate 300 may be or include a printed circuit board (PCB) with a circuit pattern.
- PCB printed circuit board
- the providing of the first, second, and third semiconductor chips 401 a , 401 b , and 401 c on the module substrate 300 may include performing a soldering process to form solder balls 407 on active surfaces of the first, second, and third semiconductor chips 401 a , 401 b , and 401 c , allowing the module substrate 300 to receive thereon the first, second, and third semiconductor chips 401 a , 401 b , and 401 c on which the solder balls 407 are formed, and forming first under-fill resin layers 409 in spaces between the module substrate 300 and the first, second, and third semiconductor chips 401 a , 401 b , and 401 c .
- the first, second, and third semiconductor chips 401 a , 401 b , and 401 c may have different heights from each other.
- Each of the first, second, and third semiconductor chips 401 a , 401 b , and 401 c may be a semiconductor logic chip, a semiconductor memory chip, a system-on-chip (SOC), or a lab-on-chip (LOC).
- the first under-fill resin layers 409 may be formed of an under-fill material.
- the component 411 may be attached to the module substrate 300 using an adhesive layer 413 provided therebetween.
- a second under-fill resin layer 415 may surround the adhesive layer 413 in a space between the components 411 and the module substrate 300 .
- the component 411 may be soldered onto the module substrate 300 .
- the component 411 may have a height different from those of the first, second, and third semiconductor chips 401 a , 401 b , and 401 c .
- the component 411 may be replaced with a resistor, an inductor, a transformer, a passive device, or other electrical devices.
- the second under-fill resin layer 415 may be formed of, for example, an under-fill material.
- a functional layer 207 and a cushion layer 208 on the functional layer 207 may be disposed on the first, second, and third semiconductor chips 401 a , 401 b , and 401 c , the component 411 , and a top surface of the module substrate 300 .
- the functional layer 207 may be an electromagnetic shield layer.
- the functional layer 207 may include a conductive polymer 207 a and an adhesive polymer 207 b , as illustrated in FIG. 1B .
- the functional layer 207 may further include a conductive filler 207 c , as illustrated in FIG. 1B .
- the conductive polymer 207 a , the adhesive polymer 207 b , and the conductive filler 207 c may be irregularly arranged in the functional layer 207 .
- the functional layer 207 and the cushion layer 208 may be processed to cover the first, second, and third semiconductor chips 401 a , 401 b , and 401 c , the component 411 , the first under-fill resin layers 409 , and the second under-fill resin layer 415 , and also to fill first, second, and third spaces S 1 , S 2 , and S 3 .
- the functional layer 207 may conformally cover top and lateral surfaces of the first, second, and third semiconductor chips 401 a , 401 b , and 401 c , top and lateral surfaces of the component 411 , surfaces of the first under-fill resin layers 409 , and a surface of the second under-fill resin layer 415 .
- the functional layer 207 may also cover a portion (e.g., first space S 1 ) of a top surface of the module substrate 300 exposed between the first semiconductor chip 401 a and the second semiconductor chip 401 b , a portion (e.g., second space S 2 ) of a top surface of the module substrate 300 exposed between the first semiconductor chip 401 a and the component 411 , and a portion (e.g., third space S 3 ) of a top surface of the module substrate 300 exposed between the component 411 and third semiconductor chip 401 c .
- the cushion layer 208 may cover the functional layer 207 , and fill the first, second, and third spaces S 1 , S 2 , and S 3 .
- a press process may be performed to cause the functional layer 207 and the cushion layer 208 to cover the first, second, and third semiconductor chips 401 a , 401 b , and 401 c and the component 411 , and also to fill the first, second, and third spaces S 1 , S 2 , and S 3 .
- Each of the first, second, and third spaces S 1 , S 2 , and S 3 may have an aspect ratio equal to or less than about 5.
- the cushion layer 208 may be removed from the functional layer 207 .
- the functional layer 207 may remain on the surfaces of the first, second, and third semiconductor chips 401 a , 401 b , and 401 c , the surface of the component 411 , the surfaces of the first under-fill resin layers 409 , the surface of the second under-fill resin layer 415 , and the top surface of the module substrate 300 exposed to the first, second, and third spaces S 1 , S 2 , and S 3 .
- the functional layer 207 may be formed to cover the surfaces of the first, second, and third semiconductor chips 401 a to 401 c and the surface of the component 411 , and at the same time, to conformally cover floor surfaces of the first, second, and third spaces S 1 , S 2 , and S 3 among the component 411 and the first, second, and third semiconductor chips 401 a , 401 b , and 401 c , thereby resulting in a reduced process time.
- FIG. 8 illustrates a cross-sectional view showing a method of fabricating a semiconductor module according to an example embodiment of the inventive concepts.
- a component 411 and first, second, and third semiconductor chips 401 a , 401 b , and 401 c may be provided on a module substrate 300 .
- Each of the first, second, and third semiconductor chips 401 a , 401 b , and 401 c may be a light emitting chip, an optical sensor chip, or a lab-on-chip (LOC).
- LOC lab-on-chip
- a molding dam 422 may be formed on a top surface of the module substrate 300 .
- the molding dam 422 may extend upward from a top surface of an edge of the module substrate 300 .
- the molding dam 422 may surround the component 411 and the first, second, and third semiconductor chips 401 a , 401 b , and 401 c.
- a window layer 421 may be disposed on the molding dam 422 , the first, second, and third semiconductor chips 401 a , 401 b , and 401 c , and the component 411 .
- the molding dam 422 may support the window layer 421 .
- the window layer 421 may be spaced apart from the component 411 and from the first, second, and third semiconductor chips 401 a , 401 b , and 401 c .
- the window layer 421 may be transparent.
- the window layer 421 may include glass.
- a functional layer 207 may be provided on the molding dam 422 and the window layer 421 , and a cushion layer 208 may be provided on the functional layer 207 . Identically or similarly to those discussed with reference to FIGS. 7B and 7C , the functional layer 207 may cover the window layer 421 , the molding dam 422 , and the top surface of the module substrate 300 .
- a semiconductor package may include a functional layer that shields electromagnetic waves and causes the semiconductor package to be fabricated at a low cost and to have a smaller thickness, thereby reducing environmental and residue issues.
- the functional layer may be transparent such that a mark displayed on a semiconductor chip may be visually recognized.
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Abstract
Description
- This U.S. nonprovisional application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2018-0028026 filed on Mar. 9, 2018, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.
- Inventive concepts relate to semiconductor packages and/or semiconductor modules, and more particularly, to semiconductor packages and/or a semiconductor modules that include a functional layer having transparency, adhesiveness, and high electrical conductivity.
- As the mobile market expands, research on electromagnetic waves emitted from electronic devices is being actively conducted. For many kinds of electronic products, electromagnetic wave emission from semiconductor packages may cause problems with other nearby semiconductor packages. The electromagnetic interference may result in various malfunctions, operation abnormality, operation failure, etc.
- Various types of semiconductor packages have been developed to meet increasing demands for high speed and dense semiconductor packages, however the electromagnetic interference issues persist.
- Some example embodiments of the inventive concepts provide semiconductor packages fabricated at a low cost, having a small thickness, and without environmental and residue issues.
- Some example embodiments of the inventive concepts provide semiconductor packages each including semiconductor chip, a mark on which has can be visually recognized.
- According to an example embodiments of the inventive concepts, a semiconductor package may include a package substrate including an insulating layer and a ground layer, the ground layer longitudinally extending in the insulating layer, an end portion of the ground layer exposed by the insulating layer, a semiconductor chip on the package substrate, a molding layer on the package substrate and surrounding at least a side surface of the semiconductor chip, and an electromagnetic shield layer covering the molding layer and the semiconductor chip, an end portion of the electromagnetic shield layer running in parallel with and being in contact with the end portion of the ground layer, the electromagnetic shield layer including a first lateral portion and a second lateral portion, the first lateral portion facing the side surface of the semiconductor chip, a second lateral portion at an end of the electromagnetic shield layer and horizontally spaced apart from the first lateral portion, the second lateral portion of the electromagnetic shield layer and a lateral end surface of the ground layer being on a substantially straight line and exposed to outside of the package substrate
- According to an example embodiments of the inventive concepts, a semiconductor package may include a package substrate including an insulating layer and a ground layer, the ground layer longitudinally extending in the insulating layer, an end portion of the ground layer exposed by the insulating layer, a semiconductor chip on the package substrate, a molding dam extending upward from a top surface of the package substrate, the molding dam horizontally spaced apart from the semiconductor chip, a window layer supported by the molding dam, the window layer and the molding dam enclosing the semiconductor chip on the package substrate, the window layer being transparent, and an electromagnetic shield layer covering the molding dam and the window layer, the electromagnetic shield layer including an end portion that runs in parallel with and is in contact with the exposed end portion of the ground layer, the electromagnetic shield layer further including a first lateral portion and a second lateral portion, the first lateral portion facing a side surface of the semiconductor chip, the second lateral portion at an end of the electromagnetic shield layer and horizontally spaced apart from the first lateral portion, the second lateral portion of the electromagnetic shield layer and a lateral end surface of the ground layer being on a substantially straight line and exposed to outside of the package substrate.
- According to an example embodiments of the inventive concepts, a semiconductor package may include a module substrate, a plurality of electronic components on the module substrate, the electronic components including one or more semiconductor chips, a plurality of under-fill resin layers between the module substrate and respective ones of the plurality of electronic components, and an electromagnetic shield layer covering top and side surfaces of the electronic components and lateral surface of the plurality of under-fill resin layers, the electromagnetic shield layer including a plurality of upper portions on respective top surfaces of the plurality of electronic components, a plurality of first lateral portions on respective side surfaces of the plurality of electronic components, a plurality of second lateral portions on respective lateral surface of the plurality of under-fill resin layers, and a plurality of lower portions on a top surface of the module substrate, a vertically connected pair of one of the plurality of first lateral portions and one of the plurality of second lateral portions connecting a corresponding one of the plurality of upper portions to a corresponding one of the plurality of lower portions.
- According to an example embodiments of the inventive concepts, a semiconductor package prepared by a method may include providing a package substrate including an insulating layer and a ground layer longitudinally extending within the insulating layer, providing a plurality of semiconductor chips on a top surface of the package substrate to be spaced apart from each other, providing a molding layer on the package substrate to surround at least a side surface of the semiconductor chip and to have a substantially flat top surface, cutting a molding layer between the plurality of semiconductor chips until the ground layer in the package substrate is exposed such that a plurality of grooves are formed between neighboring ones of the plurality of semiconductor chips, sequentially providing an electromagnetic shield layer and a cushion layer on the molding layer and the semiconductor chips, processing the cushion layer and the electromagnetic shield layer (1) to cause the electromagnetic shield layer to conformally cover top and lateral surfaces of the molding layer and (2) to cause the cushion layer to fill the grooves, side and bottom surfaces of which are conformally covered by the electromagnetic shield layer, removing the cushion layer, and cutting the package substrate in the plurality of grooves to form individual semiconductor packages such that in each of the individual semiconductor packages, (1) an end portion of the electromagnetic shield layer runs in parallel with the end portion of the ground layer and is in contact with the end portion of the ground layer, (2) the electromagnetic shield layer includes a first lateral portion and a second lateral portion, the first lateral portion facing the side surface of the semiconductor chip, the second lateral portion at an end of the electromagnetic shield layer and horizontally spaced apart from the first lateral portion, the second lateral portion of the electromagnetic shield layer and a lateral end surface of the ground layer being on a substantially straight line and exposed to outside of the package substrate.
-
FIG. 1A illustrates a cross-sectional view showing a semiconductor package according to an example embodiment of the inventive concepts. -
FIG. 1B illustrates an enlarged view showing section A ofFIG. 1A . -
FIG. 2A illustrates a cross-sectional view showing a semiconductor package according to an example embodiment of the inventive concepts. -
FIG. 2B illustrates a cross-sectional view showing a semiconductor package according to an example embodiment of the inventive concepts. -
FIG. 3A illustrates a cross-sectional view showing a semiconductor module according to an example embodiment of the inventive concepts. -
FIG. 3B illustrates a cross-sectional view showing a semiconductor module according to an example embodiment of the inventive concepts. -
FIGS. 4A to 4E illustrate cross-sectional views showing a method of fabricating a semiconductor package according to an example embodiment of the inventive concepts. -
FIGS. 5A to 5E illustrate cross-sectional views showing a method of fabricating a semiconductor package according to an example embodiment of the inventive concepts. -
FIG. 6 illustrates a cross-sectional view showing a method of fabricating a semiconductor package according to an example embodiment of the inventive concepts. -
FIGS. 7A to 7C illustrate cross-sectional views showing a method of fabricating a semiconductor module according to an example embodiment of the inventive concepts. -
FIG. 8 illustrates a cross-sectional view showing a method of fabricating a semiconductor module according to an example embodiment of the inventive concepts. -
FIG. 1A illustrates a cross-sectional view showing a semiconductor package according to an example embodiment of the inventive concepts.FIG. 1B illustrates an enlarged view showing section A ofFIG. 1A . - Referring to
FIGS. 1A and 1B , asemiconductor package 1000 may include apackage substrate 101,external terminals 105, asemiconductor chip 201,bonding wires 203, amolding layer 205, and afunctional layer 207. - The
package substrate 101 may be or include a printed circuit board (PCB) with a circuit pattern. Thepackage substrate 101 may include afirst region 10 and asecond region 20. Thesecond region 20 of thepackage substrate 101 may surround thefirst region 10 of thepackage substrate 101. Thepackage substrate 101 may include a firsttop surface 1, a secondtop surface 3, and abottom surface 2. Thepackage substrate 101 may be configured such that the firsttop surface 1 is positioned on thefirst region 10 and the secondtop surface 3 is positioned on thesecond region 20. The secondtop surface 3 of thepackage substrate 101 may be located at a level different from that of the firsttop surface 1 of thepackage substrate 101. For example, the secondtop surface 3 of thepackage substrate 101 may be located at a level lower than that of the firsttop surface 1 of thepackage substrate 101. - The
package substrate 101 may include aground layer 103 and aninsulating layer 107. Theground layer 103 may longitudinally extend in theinsulating layer 107, and an end portion of theground layer 103 may be exposed by theinsulating layer 107. Theground layer 103 may be disposed on both the first andsecond regions package substrate 101. Theground layer 103 may be disposed below firstlateral surfaces 4 of thefirst region 10 of thepackage substrate 101. Theground layer 103 may include a first segment RG1 on thefirst region 10 and a second segment RG2 on thesecond region 20. For example, as illustrated, the second segment RG2 of theground layer 103 may have a top surface (e.g., the second top surface 3) and second lateral surfaces 6, whichsurfaces 3 and 6 may be exposed to outside thepackage substrate 101. In some example embodiments, the second lateral surfaces 6 of the second segment RG2 of theground layer 103 may be exposed to outside thepackage substrate 101, and the secondtop surface 3 of the second segment RG2 of theground layer 103 may not be exposed to outside thepackage substrate 101. The second segment RG2 of theground layer 103 may be defined as a ground terminal. Theground layer 103 may include a conductive material. For example, the conductive material may include a metallic material (e.g., silver (Ag), gold (Au), or copper (Cu)), a metal alloy (e.g., copper-silver (Cu-Ag), titanium-silver-copper (Ti-Ag-Cu), or copper-zinc (Cu-Zn)), or other electrically conductive materials. - The
external terminals 105 may be disposed on thebottom surface 2 of thepackage substrate 101. Theexternal terminals 105 may be, but not limited to, a solder ball, a conductive bump, a conductive spacer, or a pin grid array. - The
ground layer 103 may be electrically connected to a specific one of theexternal terminals 105. The specificexternal terminal 105 may be supplied with a ground voltage. - The
semiconductor chip 201 may be disposed on the firsttop surface 1 of thepackage substrate 101. Thesemiconductor chip 201 may be placed on thefirst region 10 of thepackage substrate 101. Thesemiconductor chip 201 may be adhered through anadhesive layer 202 onto the firsttop surface 1 of thepackage substrate 101. For example, thesemiconductor chip 201 may be a semiconductor logic chip, a semiconductor memory chip, a system-on-chip (SOC), or a lab-on-chip (LOC). - The
semiconductor chip 201 and thepackage substrate 101 may be electrically connected to each other through thebonding wires 203 disposed therebetween. Thebonding wires 203 may include, for example, one or more of gold (Au), silver (Ag), platinum (Pt), aluminum (Al), copper (Cu), palladium (Pd), nickel (Ni), cobalt (Co), chromium (Cr), and titanium (Ti). Although not shown, thesemiconductor chip 201 may be mounted on thepackage substrate 101 in a flip-chip bonding manner or other possible manners. - The
molding layer 205 may be disposed on thefirst region 10 of thepackage substrate 101. Themolding layer 205 may cover the firsttop surface 1 of thefirst region 10 of thepackage substrate 101. Themolding layer 205 may have lateral surfaces aligned with the firstlateral surfaces 4 of thefirst region 10 of thepackage substrate 101. Themolding layer 205 may surround at least a side surface of thesemiconductor chip 201. In some example embodiments, the molding layer may surround a side surface of thesemiconductor chip 201 and cover a top surface of thesemiconductor chip 201. Themolding layer 205 may have a width W1 less than a width W2 of the package substrate 101 (W1<W2). For example, themolding layer 205 may include an epoxy molding compound (EMC) or an under-fill material. A mark (not shown) may be displayed on a top surface of themolding layer 205. The mark may be or include one or more characters for expressing particular information. - The
molding layer 205 may be covered (coated) with thefunctional layer 207 that extends onto the firstlateral surfaces 4 of thefirst region 10 of thepackage substrate 101 and onto the secondtop surface 3 of the second segment RG2 of theground layer 103. Thefunctional layer 207 may be in contact with the secondtop surface 3 of the second segment RG2 of theground layer 103. In some example embodiments, themolding layer 205 may be covered with thefunctional layer 207 that extends onto the second lateral surfaces 6 of the second segment RG2 of theground layer 103. In such example embodiments, thefunctional layer 207 may be in contact with the second lateral surfaces 6 of the second segment RG2 of theground layer 103, while being not in contact with the secondtop surface 3 of the second segment RG2 of theground layer 103. - The
functional layer 207 may have a uniform thickness. For example, a portion of thefunctional layer 207 covering themolding layer 205, a portion of thefunctional layer 207 covering the firstlateral surfaces 4 of thefirst region 10 of thepackage substrate 101, and a portion of thefunctional layer 207 covering the secondtop surface 3 of the second segment RG2 of theground layer 103 may have thicknesses that are substantially the same or substantially similar to each other. For example, thefunctional layer 207 may have a thickness equal to or less than about 40 μm. - The
functional layer 207 may be an electromagnetic shield layer. Thus, the term “function layer” and “electromagnetic shield layer” may be interchangeably used throughout this disclosure. Referring again toFIG. 1A , thefunctional layer 207 may cover themolding layer 205 and thesemiconductor chip 201. An end portion of thefunctional layer 207 may run in parallel with and is in contact with the end portion of theground layer 103. Thefunctional layer 207 may include a first lateral portion that faces the side surface of thesemiconductor chip 201, and a second lateral portion that is provided at an end of thefunctional layer 207 and is horizontally spaced apart from the first lateral portion. The second lateral portion of thefunctional layer 207 and a lateral end surface of theground layer 103 may be on a substantially straight line and exposed to outside of the package substrate. Thus thefunctional layer 207 may be electrically connected to theground layer 103, and may provide an electrical path for grounding electromagnetic waves incident on thefunctional layer 207. - Referring back to
FIG. 1B , thefunctional layer 207 may include aconductive polymer 207 a and anadhesive polymer 207 b. Theconductive polymer 207 a may have a relatively high electrical conductivity. For example, theconductive polymer 207 a may have an electrical conductivity ranging from about 500 S/cm to about 2,000 S/cm. Theconductive polymer 207 a may be transparent. For example, theconductive polymer 207 a may have a visible light transmittance equal to or higher than about 90%. For example, theconductive polymer 207 a may include one or more of poly(3,4-ethylenedioxythiophene) (PEDOT), poly(3,4-ethylenedioxythiophene) (PEDOT):sodium poly-styrenesulfonate (PSS), and poly(4,4-dioctyl cyclopentadithiophene). Theadhesive polymer 207 b may have a relatively high adhesiveness. Theadhesive polymer 207 b may be transparent. For example, theadhesive polymer 207 b may have a visible light transmittance equal to or higher than about 90%. For example, theadhesive polymer 207 b may include one or more of acrylic polymer based mesoporous or acrylic microemulsion. Theadhesive polymer 207 b may include a photo-initiator. The photo-initiator may accelerate a cross-linking reaction of theadhesive polymer 207 b when a curing process is performed. - The
functional layer 207 may further include aconductive filler 207 c. Theconductive filler 207 c may have an electrical conductivity greater than that of theconductive polymer 207 a. For example, theconductive filler 207 c may have an electrical conductivity ranging from about 5,000 S/cm to about 20,000 S/cm. Theconductive filler 207 c may be transparent. For example, theconductive filler 207 c may have a visible light transmittance equal to or higher than about 90%. For example, theconductive filler 207 c may include a transparent conductive oxide (TCO). For example, theconductive filler 207 c may be an inorganic material including one or more of indium zinc oxide (IZO), indium tin oxide (ITO), and aluminum zinc oxide (AZO). In some example embodiments, theconductive filler 207 c may be an organic material including one or more of carbon nanotube (CNT) and graphene. Because thefunctional layer 207 further includes theconductive filler 207 c, thefunctional layer 207 may increase in electrical conductivity. In some example embodiments, theconductive filler 207 c may have a flake shape. Theconductive polymer 207 a, theadhesive polymer 207 b, and theconductive filler 207 c may be irregularly arranged in thefunctional layer 207. - Because the
functional layer 207 includes theconductive polymer 207 a, theadhesive polymer 207 b, and theconductive filler 207 c, electrical conductivity and adhesiveness of thefunctional layer 207 may increase. Thus, thefunctional layer 207 may serve as a ground path for electromagnetic waves, and may be adhered to themolding layer 205 and theground layer 103 without separately providing an adhesive. Thefunctional layer 207 may be transparent. Thus, even when thefunctional layer 207 covers themolding layer 205, the mark printed on the top surface of themolding layer 205 may be visually recognized. - The
functional layer 207 may cause thesemiconductor package 1000 to be fabricated at a lower cost and/or to have a smaller thickness. Thesemiconductor package 1000 may have no metallic material for shielding electromagnetic waves, thereby resulting in reduction of environmental and residue issues. -
FIG. 2A illustrates a cross-sectional view showing a semiconductor package according to an example embodiment of the inventive concepts. - For brevity of description, constituents the same as or substantially to those discussed with reference to
FIGS. 1A and 1B are allocated the same reference numerals thereto, and a repetitive explanation thereof will be omitted. - Referring to
FIG. 2A , asemiconductor package 1000 may include apackage substrate 101,external terminals 105, asemiconductor chip 201,bonding wires 203, amolding dam 204, awindow layer 206, and afunctional layer 207. - The
package substrate 101 may be or include a printed circuit board (PCB) with a circuit pattern. Thepackage substrate 101 may include aground layer 103 and an insulatinglayer 107. Theground layer 103 may longitudinally extend in the insulatinglayer 107, and an end portion of theground layer 103 may be exposed by the insulatinglayer 107. Theexternal terminals 105 may be disposed on abottom surface 2 of thepackage substrate 101. - The
semiconductor chip 201 may be disposed on a firsttop surface 1 of thepackage substrate 101. Thesemiconductor chip 201 may be adhered through anadhesive layer 202 onto the firsttop surface 1 of thepackage substrate 101. For example, thesemiconductor chip 201 may be a light emitting chip, an optical sensor chip, or a lab-on-chip (LOC). Thesemiconductor chip 201 and thepackage substrate 101 may be electrically connected to each other through thebonding wires 203 disposed therebetween. - The
molding dam 204 may be disposed on afirst region 10 of thepackage substrate 101. Themolding dam 204 may be vertically under thefunctional layer 207, and may be horizontally within thefunctional layer 207. Themolding dam 204 may extend upward from an edge of the firsttop surface 1 of thefirst region 10 of thepackage substrate 101. Themolding dam 204 may have lateral surfaces aligned with firstlateral surfaces 4 of thefirst region 10 of thepackage substrate 101. Themolding dam 204 may be horizontally spaced apart from thesemiconductor chip 201. When viewed in plan, themolding dam 204 may surround a side surface of thesemiconductor chip 201. Themolding dam 204 may have a width W3 less than a width W2 of the package substrate 101 (W3<W2). In other words, a distance W3 between a left outer wall and a right outer wall of themolding dam 204, when viewed in a cross-section, may be smaller than the width W2 of thepackage substrate 101. The top surface of themolding dam 204 may be at a higher level or position than a top of thesemiconductor chip 201. - The
window layer 206 may be disposed on themolding dam 204 and thesemiconductor chip 201. Themolding dam 204 may support thewindow layer 206. Thewindow layer 206 may be spaced apart from thesemiconductor chip 201. Thewindow layer 206 and themolding dam 204 may enclose thesemiconductor chip 201 on thepackage substrate 101. Thewindow layer 206 may be transparent. For example, thewindow layer 206 may include glass. - A cavity C may be defined by the first
top surface 1, themolding dam 204, and thewindow layer 206. For example, the cavity C may be an empty space surrounded by the firsttop surface 1, themolding dam 204, and thewindow layer 206. Thesemiconductor chip 201 may be disposed in the cavity C. - For example, as illustrated, the
molding dam 204 and thewindow layer 206 may be covered with thefunctional layer 207 that extends onto the firstlateral surfaces 4 of thefirst region 10 of thepackage substrate 101 and onto a secondtop surface 3 of a second segment RG2 of theground layer 103. Thefunctional layer 207 may include an end portion that runs in parallel with and is in contact with the exposed end portion of theground layer 103. Thefunctional layer 207 may include a first lateral portion that faces a side surface of thesemiconductor chip 201 and a second lateral portion that is provided at an end of thefunctional layer 207 and is horizontally spaced apart from the first lateral portion. The second lateral portion of thefunctional layer 207 and a lateral end surface of theground layer 103 may be on a substantially straight line and be exposed to outside of thepackage substrate 101. In some example embodiments, themolding dam 204 and thewindow layer 206 may be covered with thefunctional layer 207 that extends onto second lateral surfaces 6 of the second segment RG2 of theground layer 103 while providing thefunctional layer 207 to be in contact with theground layer 103. Thefunctional layer 207 may include aconductive polymer 207 a and anadhesive polymer 207 b, as illustrated inFIG. 1B . Thefunctional layer 207 may further include aconductive filler 207 c, as illustrated inFIG. 1B . - Because the
functional layer 207 includes theconductive polymer 207 a, theadhesive polymer 207 b, and theconductive filler 207 c, electrical conductivity and adhesiveness of thefunctional layer 207 may increase. Thus, thefunctional layer 207 may serve as a ground path for electromagnetic waves, and may be adhered to themolding dam 204, thewindow layer 206, and theground layer 103 without separately providing an adhesive. Thewindow layer 206 and thefunctional layer 207 may be transparent. Therefore, in the case where thesemiconductor chip 201 is a light emitting chip, light emitted from thesemiconductor chip 201 may be radiated outward through thewindow layer 206 and thefunctional layer 207. In the case where thesemiconductor chip 201 is an optical sensor chip, thesemiconductor chip 201 may receive external light through thewindow layer 206 and thefunctional layer 207. -
FIG. 2B illustrates a cross-sectional view showing a semiconductor package according to an example embodiment of the inventive concepts. - For brevity of description, constituents the same as or substantially similar to those discussed with reference to
FIGS. 1A, 1B, and 2A are allocated the same reference numerals thereto, and a repetitive explanation thereof will be omitted. - Referring to
FIG. 2B , asemiconductor package 1000 may include apackage substrate 101,external terminals 105, afirst semiconductor chip 201, asecond semiconductor chip 209,bonding wires 203, amolding dam 204, awindow layer 206, and afunctional layer 207. - The
first semiconductor chip 201 may be disposed on a firsttop surface 1 of thepackage substrate 101. Thefirst semiconductor chip 201 may be adhered through a firstadhesive layer 202 onto the firsttop surface 1 of thepackage substrate 101. For example, thefirst semiconductor chip 201 may be a semiconductor logic chip, a semiconductor memory chip, a system-on-chip (SOC), or a lab-on-chip (LOC). Thefirst semiconductor chip 201 and thepackage substrate 101 may be electrically connected to each other through thebonding wires 203 disposed therebetween. - The
second semiconductor chip 209 may be disposed on a top surface of thefirst semiconductor chip 201. Thesecond semiconductor chip 209 may be adhered through a secondadhesive layer 210 to the top surface of thefirst semiconductor chip 201. For example, thesecond semiconductor chip 209 may be a light emitting chip, an optical sensor chip, or a lab-on-chip (LOC). Thesecond semiconductor chip 209 and thepackage substrate 101 may be electrically connected to each other through thebonding wires 203 disposed therebetween. - Although not shown, the
semiconductor package 1000 may further include other semiconductor chips between the first andsecond semiconductor chips -
FIG. 3A illustrates a cross-sectional view showing a semiconductor module according to an example embodiment of the inventive concepts. - For brevity of description, constituents the same as or substantially similar to those discussed with reference to
FIGS. 1A and 1B are allocated the same reference numerals thereto, and a repetitive explanation thereof will be omitted. - Referring to
FIG. 3A , asemiconductor module 2000 may include amodule substrate 300, and afirst semiconductor chip 401 a, asecond semiconductor chip 401 b, athird semiconductor chip 401 c, acomponent 411, and afunctional layer 207 on themodule substrate 300. Thefirst semiconductor chip 401 a, thesecond semiconductor chip 401 b, thethird semiconductor chip 401 c, and thecomponent 411 may be collectively referred to as a plurality of electronic components. - The
module substrate 300 may be or include a printed circuit board (PCB) with a circuit pattern. The first, second, andthird semiconductor chips module substrate 300. The first, second, andthird semiconductor chips third semiconductor chips - A plurality of
solder balls 407 may be disposed between themodule substrate 300 and each of the first, second, andthird semiconductor chips solder balls 407 may electrically connect between themodule substrate 300 and each of the first, second, andthird semiconductor chips fill resin layer 409 may be disposed within a gap between themodule substrate 300 and each of the first, second, andthird semiconductor chips fill resin layer 409 may surround surfaces of thesolder balls 407. For example, the first under-fill resin layer 409 may include an under-fill material. - The
component 411 may be disposed on themodule substrate 300. For example, thecomponent 411 may be disposed between thefirst semiconductor chip 401 a and thethird semiconductor chip 401 c. The position of thecomponent 411 is not limited to the above, but may be variously changed. Thecomponent 411 may be adhered through anadhesive layer 413 onto themodule substrate 300. In some example embodiments, thecomponent 411 may be replaced with a resistor, an inductor, a transformer, a passive device, or other electrical devices. Thecomponent 411 may have a height different from those of the first, second, andthird semiconductor chips fill resin layer 415 may be disposed between thecomponent 411 and themodule substrate 300, and may surround theadhesive layer 413. - The
functional layer 207 may extend onto a top surface of themodule substrate 300, while covering the first, second, andthird semiconductor chips fill resin layers 409, thecomponent 411, and a lateral surface of the second under-fill resin layer 415. For example, thefunctional layer 207 may cover top and lateral surfaces of the first, second, andthird semiconductor chips fill resin layers 409, and a surface of the second under-fill resin layer 415. Thefunctional layer 207 may also cover top and lateral surfaces of thecomponent 411. - The
functional layer 207 may extend onto a top surface of themodule substrate 300 exposed to a first space S1 between the first andsecond semiconductor chips module substrate 300 exposed to a second space S2 between thecomponent 411 and thefirst semiconductor chip 401 a. Thefunctional layer 207 may extend onto a top surface of themodule substrate 300 exposed to a third space S3 between thethird semiconductor chip 401 c and thecomponent 411. Thefunctional layer 207 may include a plurality of upper portions on respective top surfaces of the plurality of electronic components, a plurality of first lateral portions on respective side surfaces of the plurality of electronic components, a plurality of second lateral portions on respective lateral surface of the plurality of under-fill resin layers, and a plurality of lower portions on a top surface of the module substrate. A vertically connected pair of one of the plurality of first lateral portions and one of the plurality of second lateral portions may connect a corresponding one of the plurality of upper portions to a corresponding one of the plurality of lower portions. Thefunctional layer 207 may include aconductive polymer 207 a and anadhesive polymer 207 b, as illustrated inFIG. 1B . Thefunctional layer 207 may further include aconductive filler 207 c, as illustrated inFIG. 1B . - A thickness of a portion of the
functional layer 207 covering the top surface of themodule substrate 300 may be the same as or substantially similar to a thickness of each of portions of thefunctional layer 207 covering the first, second, andthird semiconductor chips fill resin layers 409, thecomponent 411, and the second under-fill resin layer 415. For example, thefunctional layer 207 may have a thickness equal to or less than about 40 μm. Each of the first, second, and third spaces S1, S2, and S3 may have an aspect ratio equal to or less than about 5. The aspect ratio may correspond to a value obtained by dividing a depth (or height) of each of the first, second, and third spaces S1, S2, and S3 by a width of the each of the first, second, and third spaces S1, S2, and S3. -
FIG. 3B illustrates a cross-sectional view showing a semiconductor module according to an example embodiment of the inventive concepts. - For brevity of description, constituents the same as or substantially similar to those discussed with reference to
FIGS. 1A, 1B, and 3A are allocated the same reference numerals thereto, and a repetitive explanation thereof will be omitted. - Referring to
FIG. 3B , asemiconductor module 2000 may include amodule substrate 300, afirst semiconductor chip 401 a, asecond semiconductor chip 401 b, athird semiconductor chip 401 c, acomponent 411, afunctional layer 207, amolding dam 422, and awindow layer 421. - The first, second, and
third semiconductor chips module substrate 300. Each of the first, second, andthird semiconductor chips - The
component 411 may be disposed on themodule substrate 300. - The
molding dam 422 may be disposed on themodule substrate 300. Themolding dam 422 may extend upward from a top surface of themodule substrate 300. Themolding dam 422 may be spaced apart from thecomponent 411 and from the first, second, andthird semiconductor chips molding dam 422 may surround thecomponent 411 and the first, second, andthird semiconductor chips - The
window layer 421 may be disposed on themolding dam 422, thecomponent 411, and the first, second, andthird semiconductor chips molding dam 422 may support thewindow layer 421. Thewindow layer 421 may be spaced apart from thecomponent 411 and from the first, second, andthird semiconductor chips window layer 421 may be transparent. For example, thewindow layer 421 may include glass. - The
molding dam 422 and thewindow layer 421 may be covered with thefunctional layer 207 that extends onto a top surface of an edge of themodule substrate 300. For example, thefunctional layer 207 may cover a top surface of thewindow layer 421, a lateral surface of themolding dam 422, and the top surface of an edge of themodule substrate 300. -
FIGS. 4A to 4E illustrate cross-sectional views showing a method of fabricating a semiconductor package according to an example embodiment of the inventive concepts. - For brevity of description, constituents the same as or substantially similar to those discussed with reference to
FIGS. 1A and 1B are allocated the same reference numerals thereto, and a repetitive explanation thereof will be omitted. - Referring to
FIG. 4A , apackage substrate 101 may include a firsttop surface 1 and abottom surface 2. Thepackage substrate 101 may be or include a printed circuit board (PCB) with a circuit pattern. Thepackage substrate 101 may include aground layer 103. Theground layer 103 may be disposed within thepackage substrate 101. Theground layer 103 may include a conductive material. For example, the conductive material may include a metallic material (e.g., silver (Ag), gold (Au), or copper (Cu)), a metal alloy (e.g., copper-silver (Cu-Ag), titanium-silver-copper (Ti-Ag-Cu), or copper-zinc (Cu-Zn)), or other electrically conductive materials. - A plurality of
semiconductor chips 201 may be provided on the firsttop surface 1 of thepackage substrate 101, while being spaced apart from each other, for example, at a regular interval. Each of thesemiconductor chips 201 may be adhered through anadhesive layer 202 onto thepackage substrate 101. For example, thesemiconductor chips 201 may be a semiconductor logic chip, a semiconductor memory chip, a system-on-chip (SOC), or a lab-on-chip (LOC). - A plurality of
bonding wires 203 may be disposed between thepackage substrate 101 and each of the semiconductor chips 201. Thebonding wires 203 may electrically connect thesemiconductor chip 201 to thepackage substrate 101. For example, thebonding wires 203 may be formed of one or more of gold (Au), silver (Ag), platinum (Pt), aluminum (Al), copper (Cu), palladium (Pd), nickel (Ni), cobalt (Co), chromium (Cr), and titanium (Ti). - A
molding layer 205 may be formed on the firsttop surface 1 of thepackage substrate 101. Themolding layer 205 may cover the semiconductor chips 201. For example, themolding layer 205 may be formed of an epoxy molding compound (EMC) or an under-fill material. A plurality ofexternal terminals 105 may be formed on thebottom surface 2 of thepackage substrate 101. In the case where theexternal terminals 105 are solder balls, a soldering process may be performed to form theexternal terminals 105 on thebottom surface 2 of thepackage substrate 101. - Referring to
FIG. 4B , a cutting process may be performed on themolding layer 205 and thepackage substrate 101. The cutting process may partially cut themolding layer 205 between thesemiconductor chips 201 and thepackage substrate 101 between the semiconductor chips 201. The cutting process may partially cut an edge of themolding layer 205 and an edge of thepackage substrate 101 overlapping the edge of themolding layer 205. The cutting process may form a groove H between a pair of neighboring semiconductor chips 201. The cutting process may form a groove H between a first edge of themolding layer 205 and an edge of the leftmost one of the semiconductor chips 201. The cutting process may form a groove H between a second edge of themolding layer 205 that is opposite to the first edge of themolding layer 205 and an edge of the rightmost one of the semiconductor chips 201. A pair of neighboring grooves H may define therebetween a region where a unit semiconductor package occupies. The groove H may have a floor surface lower than the firsttop surface 1 of thepackage substrate 101. For example, the groove H may have an aspect ratio equal to or less than about 5. The aspect ratio may correspond to a value obtained by dividing a depth (or height) of the groove H by a width of the groove H. The cutting process may separate themolding layer 205 into a plurality of pieces. The cutting process may continue until theground layer 103 is exposed. After the cutting process, theground layer 103 may be partially exposed to the groove H. - A
functional layer 207 may be provided on themolding layer 205, and acushion layer 208 may be provided on thefunctional layer 207. - The
functional layer 207 may be an electromagnetic shield layer. Thefunctional layer 207 may include aconductive polymer 207 a and anadhesive polymer 207 b, as illustrated inFIG. 1B . Thefunctional layer 207 may further include aconductive filler 207 c, as illustrate inFIG. 1B . - The following describes a method of forming the
functional layer 207. Theconductive polymer 207 a, theadhesive polymer 207 b, and theconductive filler 207 c may be melted in a solvent to form a liquefied composition. For example, the solvent may include alcohol. The liquefied composition may be wet-coated to have a proper thickness, and then dried in an oven to evaporate the solvent from the liquefied composition. Therefore, thefunctional layer 207 may be formed to have theconductive polymer 207 a, theadhesive polymer 207 b, and theconductive filler 207 c that are in solid state. For example, thefunctional layer 207 may have a thickness equal to or less than about 40 μm. - The
cushion layer 208 may have a thickness ranging from about 50 μm to about 400 μm. Thecushion layer 208 may include a polyethylene-based polymer or a polyurethane-based polymer. For example, the polyethylene-based polymer may include polymethylpentene (PMP), polyvinylchlodride (PVC), or polybutyleneterephthalate (PBT). For example, the polyurethane-based polymer may include thermoplastic polyurethane (TPU). - Referring to
FIG. 4C , thefunctional layer 207 and thecushion layer 208 may be processed to cover the molding layers 205 and to fill the groove H. For example, thefunctional layer 207 may conformally cover top and lateral surfaces of the molding layers 205 and the floor surface of the groove H. Thecushion layer 208 may cover thefunctional layer 207 and fill the groove H. A press process may be performed to cause thefunctional layer 207 and thecushion layer 208 to cover the surfaces of the molding layers 205 and to fill the groove H. The press process may be performed such that thefunctional layer 207 and thecushion layer 208 are heated and pressed against thepackage substrate 101 for about 5 minutes to about 15 minutes in a state that thefunctional layer 207 and thecushion layer 208 are provided on the molding layers 205. The press process may be performed under a pressure ranging from about 2 MPa to about 10 MPa at a temperature ranging from about 50° C. to about 150° C. - The
cushion layer 208 may have decreased elastic modulus due to the heat and pressure such that the groove H may be easily filled with thecushion layer 208. Thefunctional layer 207 may conformally cover the floor surface of the groove H and the lateral surfaces of the molding layers 205. - Referring to
FIG. 4D , thecushion layer 208 may be removed from thefunctional layer 207. The press process may expand thecushion layer 208 and reduce the elastic modulus of thecushion layer 208, and therefore an external physical force may easily separate thecushion layer 208 from thefunctional layer 207. Thefunctional layer 207 may remain on the surfaces of the molding layers 205 and the floor surface of the groove H. After thecushion layer 208 is removed, a curing process may be performed on thefunctional layer 207. The curing process may cure thefunctional layer 207. The curing process may irradiate an ultraviolet ray to thefunctional layer 207. The ultraviolet ray may have an intensity ranging from about 100 mJ to about 1,000 mJ. The ultraviolet ray may be irradiated for about 1 second to about 5 minutes. In the curing process, a photo-initiator of the adhesive polymer (see 207 b ofFIG. 1B ) may accelerate a cross-linking process of theadhesive polymer 207 b. The cross-linking process may be accelerated when the photo-initiator is irradiated with an ultraviolet ray whose wavelength ranges from about 300 nm to about 600 nm. - According to some example embodiments of inventive concepts, the
functional layer 207 may conformally cover the top surfaces of the molding layers 205, and at the same time, conformally cover the floor surface and sidewalls of the groove H. The formation of thefunctional layer 207 may be performed prior to a package singulation process, such as a sawing or sorting process. Therefore, a process tim may be reduced compared to the case where thefunctional layer 207 is formed on each of semiconductor packages after the package singulation process (sawing or sorting). - Referring to
FIG. 4E , a package singulation process (sawing or sorting) may be performed within the groove H, thereby forming a plurality of semiconductor packages. If thepackage substrate 101 has a non-cut portion when the cutting process is performed, the package singulation process (sawing or sorting) may completely cut the non-cut portion of thepackage substrate 101. For example, the package singulation process (sawing or sorting) may cut thepackage substrate 101 along a scribe line which has a width less than that of the groove H, thereby mitigating or preventing thefunctional layer 207 formed on the lateral surfaces of the molding layers 205 from being removed. -
FIGS. 5A to 5E illustrate cross-sectional views showing a method of fabricating a semiconductor package according to an example embodiment of the inventive concepts. - For brevity of description, constituents the same as or substantially similar to those discussed with reference to
FIGS. 4A to 4E are allocated the same reference numerals thereto, and a repetitive explanation thereof will be omitted. - Referring to
FIG. 5A , apackage substrate 101 may include a firsttop surface 1 and abottom surface 2. Thepackage substrate 101 may include aground layer 103. - A plurality of
semiconductor chips 201 may be formed on the firsttop surface 1 of thepackage substrate 101, while being spaced apart from each other at a regular interval. Each of thesemiconductor chips 201 may be adhered through anadhesive layer 202 onto thepackage substrate 101. For example, thesemiconductor chips 201 may be a light emitting chip, an optical sensor chip, or a lab-on-chip (LOC). A plurality ofbonding wires 203 may be disposed between thepackage substrate 101 and each of the semiconductor chips 201. - A
molding dam 204 may be formed on the firsttop surface 1 of thepackage substrate 101. Themolding dam 204 may extend upward from an edge of the firsttop surface 1. Themolding dam 204 may be spaced apart from each of the semiconductor chips 201. When viewed in a plan view, themolding dam 204 may surround each of the semiconductor chips 201. - A
window layer 206 may be disposed on themolding dam 204 and the semiconductor chips 201. Themolding dam 204 may support thewindow layer 206. Thewindow layer 206 may be spaced apart from each of the semiconductor chips 201. Thewindow layer 206 may be transparent. For example, thewindow layer 206 may include glass. - A plurality of cavities C may be defined by the first
top surface 1, themolding dam 204, and thewindow layer 206. For example, the cavities C may be empty spaces surrounded by the firsttop surface 1, themolding dam 204, and thewindow layer 206. Each of the cavities C may receive therein onesemiconductor chip 201. - A plurality of
external terminals 105 may be formed on thebottom surface 2 of thepackage substrate 101. - Referring to
FIG. 5B , a cutting process may be performed on themolding dam 204, thewindow layer 206, and thepackage substrate 101. The cutting process may cut a portion of each of themolding dam 204, thewindow layer 206, and thepackage substrate 101, which is positioned between the semiconductor chips 201. The cutting process may partially cut an edge of each of themolding dam 204 and thewindow layer 206, and also partially cut an edge of thepackage substrate 101 overlapping the edges of themolding dam 204 and thewindow layer 206. The cutting process may form a groove H between a pair of neighboringsemiconductor chips 201, and a pair of neighboring grooves H may define therebetween a region where a unit semiconductor package occupies. The cutting process may separate each of themolding dam 204 and thewindow layer 206 into a plurality of pieces. - The
window layer 206 may be provided thereon with afunctional layer 207 and acushion layer 208 on thefunctional layer 207. - The
functional layer 207 may be an electromagnetic shield layer. Thefunctional layer 207 may include aconductive polymer 207 a and anadhesive polymer 207 b, as illustrated inFIG. 1B . Thefunctional layer 207 may further include aconductive filler 207 c, as illustrated inFIG. 1B . Theconductive polymer 207 a, theadhesive polymer 207 b, and theconductive filler 207 c may be irregularly arranged in thefunctional layer 207. - Referring to
FIG. 5C , thefunctional layer 207 and thecushion layer 208 may be processed to fill the groove H and to cover themolding dams 204 and thewindow layer 206. For example, thefunctional layer 207 may conformally cover top surfaces of thewindow layer 206, lateral surfaces of themolding dams 204, and a floor surface of the groove H. Thecushion layer 208 may cover thefunctional layer 207 and fill the groove H. A press process may be performed to cause thefunctional layer 207 and thecushion layer 208 to fill the groove H and to cover the surfaces of thewindow layer 206 and themolding dams 204. - Referring to
FIG. 5D , thecushion layer 208 may be removed from thefunctional layer 207. Thefunctional layer 207 may remain on the floor surface of the groove H and on the surfaces of thewindow layer 206 and themolding dams 204. After thecushion layer 208 is removed, a curing process may be performed on thefunctional layer 207. - Referring to
FIG. 5E , a package singulation process (sawing or sorting) may be performed within the groove H, thereby forming a plurality of semiconductor packages. If thepackage substrate 101 has a non-cut portion when the cutting process is performed, the package singulation process (sawing or sorting) may completely cut the non-cut portion of thepackage substrate 101. -
FIG. 6 illustrates a cross-sectional view showing a method of fabricating a semiconductor package according to an example embodiment of the inventive concepts. - For brevity of description, constituents the same as or substantially similar to those discussed with reference to
FIGS. 4A to 4E and 5A to 5E are allocated the same reference numerals thereto, and a repetitive explanation thereof will be omitted. - Referring to
FIG. 6 , a plurality offirst semiconductor chips 201 may be provided on a firsttop surface 1 of apackage substrate 101, while spaced apart from each other at a regular interval. Each of thefirst semiconductor chips 201 may be adhered through a firstadhesive layer 202 onto thepackage substrate 101. For example, thefirst semiconductor chips 201 may be a semiconductor logic chip, a semiconductor memory chip, a system-on-chip (SOC), or a lab-on-chip (LOC). A plurality ofbonding wires 203 may be disposed between thepackage substrate 101 and each of thefirst semiconductor chips 201. - A plurality of
second semiconductor chips 209 may be disposed on top surfaces of thefirst semiconductor chip 201. Each of thesecond semiconductor chips 209 may be adhered through a secondadhesive layer 210 to the top surfaces of thefirst semiconductor chips 201. For example, thesecond semiconductor chips 209 may be a light emitting chip, an optical sensor chip, or a lab-on-chip (LOC). A plurality ofbonding wires 203 may be disposed between thepackage substrate 101 and each of the second semiconductor chips 209. - Although not shown, other semiconductor chips may further be disposed between the first and
second semiconductor chips - A
molding dam 204 may be formed on the firsttop surface 1 of thepackage substrate 101. - A
window layer 206 may be disposed on themolding dam 204 and the first andsecond semiconductor chips - Identically or similarly to those discussed with reference to
FIGS. 5B to 5E , afunctional layer 207 may cover surfaces of themolding dams 204 and surfaces of thewindow layer 206, and a plurality of semiconductor packages may be fabricated -
FIGS. 7A to 7C illustrate cross-sectional views showing a method of fabricating a semiconductor module according to an example embodiment of the inventive concepts. - For brevity of description, constituents the same as or substantially similar to those discussed with reference to
FIGS. 4A to 4E are allocated the same reference numerals thereto, and a repetitive explanation thereof will be omitted. - Referring to
FIG. 7A , acomponent 411 and first, second, andthird semiconductor chips module substrate 300. Themodule substrate 300 may be or include a printed circuit board (PCB) with a circuit pattern. The providing of the first, second, andthird semiconductor chips module substrate 300 may include performing a soldering process to formsolder balls 407 on active surfaces of the first, second, andthird semiconductor chips module substrate 300 to receive thereon the first, second, andthird semiconductor chips solder balls 407 are formed, and forming first under-fill resin layers 409 in spaces between themodule substrate 300 and the first, second, andthird semiconductor chips third semiconductor chips third semiconductor chips fill resin layers 409 may be formed of an under-fill material. - The
component 411 may be attached to themodule substrate 300 using anadhesive layer 413 provided therebetween. A second under-fill resin layer 415 may surround theadhesive layer 413 in a space between thecomponents 411 and themodule substrate 300. In some example embodiments, thecomponent 411 may be soldered onto themodule substrate 300. Thecomponent 411 may have a height different from those of the first, second, andthird semiconductor chips component 411 may be replaced with a resistor, an inductor, a transformer, a passive device, or other electrical devices. The second under-fill resin layer 415 may be formed of, for example, an under-fill material. - A
functional layer 207 and acushion layer 208 on thefunctional layer 207 may be disposed on the first, second, andthird semiconductor chips component 411, and a top surface of themodule substrate 300. - The
functional layer 207 may be an electromagnetic shield layer. Thefunctional layer 207 may include aconductive polymer 207 a and anadhesive polymer 207 b, as illustrated inFIG. 1B . Thefunctional layer 207 may further include aconductive filler 207 c, as illustrated inFIG. 1B . Theconductive polymer 207 a, theadhesive polymer 207 b, and theconductive filler 207 c may be irregularly arranged in thefunctional layer 207. - Referring to
FIG. 7B , thefunctional layer 207 and thecushion layer 208 may be processed to cover the first, second, andthird semiconductor chips component 411, the first under-fill resin layers 409, and the second under-fill resin layer 415, and also to fill first, second, and third spaces S1, S2, and S3. - For example, the
functional layer 207 may conformally cover top and lateral surfaces of the first, second, andthird semiconductor chips component 411, surfaces of the first under-fill resin layers 409, and a surface of the second under-fill resin layer 415. Thefunctional layer 207 may also cover a portion (e.g., first space S1) of a top surface of themodule substrate 300 exposed between thefirst semiconductor chip 401 a and thesecond semiconductor chip 401 b, a portion (e.g., second space S2) of a top surface of themodule substrate 300 exposed between thefirst semiconductor chip 401 a and thecomponent 411, and a portion (e.g., third space S3) of a top surface of themodule substrate 300 exposed between thecomponent 411 andthird semiconductor chip 401 c. Thecushion layer 208 may cover thefunctional layer 207, and fill the first, second, and third spaces S1, S2, and S3. - A press process may be performed to cause the
functional layer 207 and thecushion layer 208 to cover the first, second, andthird semiconductor chips component 411, and also to fill the first, second, and third spaces S1, S2, and S3. Each of the first, second, and third spaces S1, S2, and S3 may have an aspect ratio equal to or less than about 5. - Referring to
FIG. 7C , thecushion layer 208 may be removed from thefunctional layer 207. Thefunctional layer 207 may remain on the surfaces of the first, second, andthird semiconductor chips component 411, the surfaces of the first under-fill resin layers 409, the surface of the second under-fill resin layer 415, and the top surface of themodule substrate 300 exposed to the first, second, and third spaces S1, S2, and S3. - According to some example embodiments of inventive concepts, the
functional layer 207 may be formed to cover the surfaces of the first, second, andthird semiconductor chips 401 a to 401 c and the surface of thecomponent 411, and at the same time, to conformally cover floor surfaces of the first, second, and third spaces S1, S2, and S3 among thecomponent 411 and the first, second, andthird semiconductor chips -
FIG. 8 illustrates a cross-sectional view showing a method of fabricating a semiconductor module according to an example embodiment of the inventive concepts. - For brevity of description, constituents the same as or substantially similar to those discussed with reference to
FIGS. 4A to 4E and 7A to 7C are allocated the same reference numerals thereto, and a repetitive explanation thereof will be omitted. - Referring to
FIG. 8 , acomponent 411 and first, second, andthird semiconductor chips module substrate 300. Each of the first, second, andthird semiconductor chips - A
molding dam 422 may be formed on a top surface of themodule substrate 300. Themolding dam 422 may extend upward from a top surface of an edge of themodule substrate 300. When viewed in a plan view, themolding dam 422 may surround thecomponent 411 and the first, second, andthird semiconductor chips - A
window layer 421 may be disposed on themolding dam 422, the first, second, andthird semiconductor chips component 411. Themolding dam 422 may support thewindow layer 421. Thewindow layer 421 may be spaced apart from thecomponent 411 and from the first, second, andthird semiconductor chips window layer 421 may be transparent. For example, thewindow layer 421 may include glass. - A
functional layer 207 may be provided on themolding dam 422 and thewindow layer 421, and acushion layer 208 may be provided on thefunctional layer 207. Identically or similarly to those discussed with reference toFIGS. 7B and 7C , thefunctional layer 207 may cover thewindow layer 421, themolding dam 422, and the top surface of themodule substrate 300. - According to inventive concepts, a semiconductor package may include a functional layer that shields electromagnetic waves and causes the semiconductor package to be fabricated at a low cost and to have a smaller thickness, thereby reducing environmental and residue issues.
- Furthermore, the functional layer may be transparent such that a mark displayed on a semiconductor chip may be visually recognized.
- Although the present inventive concepts have been described in connection with some example embodiments of the inventive concepts illustrated in the accompanying drawings, it will be understood to those skilled in the art that various changes and modifications may be made without departing from the technical spirit and essential feature of the inventive concepts. It will be apparent to those skilled in the art that various substitution, modifications, and changes may be thereto without departing from the scope and spirit of the inventive concepts.
Claims (22)
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US11398424B2 (en) * | 2020-02-18 | 2022-07-26 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure |
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KR20190106479A (en) | 2019-09-18 |
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US10433469B1 (en) | 2019-10-01 |
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