CN110224018A - 半导体结构 - Google Patents

半导体结构 Download PDF

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Publication number
CN110224018A
CN110224018A CN201810488000.9A CN201810488000A CN110224018A CN 110224018 A CN110224018 A CN 110224018A CN 201810488000 A CN201810488000 A CN 201810488000A CN 110224018 A CN110224018 A CN 110224018A
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CN
China
Prior art keywords
layer
source
drain regions
side wall
metal
Prior art date
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Pending
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CN201810488000.9A
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English (en)
Inventor
郑宇彣
卢炜业
王毓萱
李弘贸
蔡彦明
陈泓旭
林威戎
张志维
蔡明兴
林圣轩
郑雅忆
林正堂
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN110224018A publication Critical patent/CN110224018A/zh
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Abstract

公开一种半导体结构。在一实施例中，结构包括具有源极/漏极区的主动区于基板上；介电层，位于主动区上并具有对准源极/漏极区的侧壁的侧壁；以及导电结构，沿着介电层的侧壁至源极/漏极区。源极/漏极区具有侧壁与自源极/漏极区的侧壁横向延伸的横向表面，且源极/漏极区还包含自源极/漏极区的侧壁横向延伸至源极/漏极区中的氮化区。导电结构包含沿着源极/漏极区的横向表面并沿着源极/漏极区的侧壁的至少一部分的硅化物区。

Description

半导体结构
技术领域
本发明实施例涉及半导体结构与其形成方法，更特别涉及表面处理工艺。
背景技术
随着半导体产业进展至纳米技术工艺节点，以达更高的装置密度、更高效能、与更低成本时，来自工艺与设计问题的挑战导致三维设计的发展，比如鳍状场效晶体管。鳍状场效晶体管装置通常包含高深宽比的半导体鳍状物，其中形成有通道区与源极/漏极区。栅极形成于鳍状结构上并沿着鳍状结构的侧壁(如包覆鳍状结构)，其优点为增加通道区的表面积，可产生更快、更可信、与更易控制的半导体晶体管装置。
鳍状场效晶体管装置通常包含用于形成源极区与漏极区的半导体区。接着形成金属硅化物于半导体区的表面上，以降低金属接点插塞(用于接触硅化物区)与半导体区之间的接点电阻。然而随着尺寸缩小，上述结构出现新的挑战。
发明内容
本发明一实施例提供的半导体结构，包括：主动区、介电层以及导电结构。主动区位于基板上，包括源极/漏极区，源极/漏极区具有侧壁与自源极/漏极区的侧壁横向延伸的横向表面，源极/漏极区还包含自源极/漏极区的侧壁横向延伸至源极/漏极区中的氮化区。介电层位于主动区上并具有对准源极/漏极区的侧壁的侧壁。导电结构沿着介电层的侧壁至源极/漏极区设置，导电结构包含硅化物区，且硅化物区沿着源极/漏极区的横向表面并沿着源极/漏极区的侧壁的至少一部分。
附图说明
图1为一些实施例中，用于制作半导体装置的例示性方法其流程图。
图2为一些实施例中，对应制作阶段的一的半导体装置其透视图。
图3A、图3B至图8A、图8B以及图11A、图11B至图12A、图12B为一些实施例中，依据图1的流程图制作的半导体装置于多种阶段的部分剖视图。
图9与图10为一些实施例中，源极/漏极区部分附图，其具有表面氮化物层或氮化部分。
图13为一些实施例中，图8A的剖视图部分的额外细节。
图14为一些实施例中，处理半导体装置的例示性方法的流程图。
图15与图16为一些实施例中，依据图14的流程图制作的半导体装置于多种阶段的部分剖视图。
其中，附图标记说明如下：
A-A、B-B 剖面
D1 第一尺寸
D2 第二尺寸
D3 第三尺寸
D4 第四尺寸
D5 第五尺寸
D6 第六尺寸
D7 第七尺寸
D8 第八尺寸
D9 第九尺寸
G1、G2、G3、G4、G5 尺寸
100、1400 流程图
102、104、106、108、110、112、114、116、118、1402、1404 步骤
210 金属层
211 表面处理
213 扩散阻挡层
214 硅化物层
215 表面氮化物层
217 氮化物区
219 阻挡层
220 界面介电层
221 导电材料
222、280 栅极介电层
224 顺应层
226 栅极
228a、228b 置换栅极结构
230 第二层间介电层
231 U型沟槽
232 源极/漏极接点开口
237 底部
239 侧壁
240 半导体装置
251 栅极结构
253 沟槽
270 半导体基板
274 鳍状物
278 隔离区
282 栅极层
284 掩模
286 栅极间隔物
292 源极/漏极区
296 接点蚀刻停止层
297 第一层间介电层
1502、1514 阻挡层
1504 第一层
1506 第二层
1508 氧化表面层
1509 表面
1510、1516 插图
1512 预清洁工艺
具体实施方式
下述公开内容提供许多不同实施例或实例以实施本发明的不同结构。下述特定构件与排列的实施例用以简化本发明而非局限本发明。举例来说，形成第一构件于第二构件上的叙述包含两者直接接触，或两者之间隔有其他额外构件而非直接接触。此外，本发明的多个实例可采用重复标号及/或符号使说明简化及明确，但这些重复不代表多种实施例中相同标号的元件之间具有相同的对应关。
此外，空间性的相对用语如“下方”、“其下”、“较下方”、“上方”、“较上方”、或类似用语可用于简化说明某一元件与另一元件在附图中的相对关。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。元件还可转动90°或其他角度，因此方向性用语仅用以说明附图中的方向。
下述多种实施例提供的结构与方法，不需成长额外膜于接点开口中，即可形成有效金属扩散阻挡层于侧壁中，以避免接点开口露出的外延源极/漏极区的侧壁与接点金属反应产生不需要的金属硅化物。在额外或其他例子中，还可提供无损伤的清洁方法，以自形成于硅化物上的金属阻挡层移除氧化物。金属阻挡层可恢复至初始状态，经由后续处理即可再次使用。
上述内容概述了本发明中的一些实施例。可以预期的是，平面晶体管装置或三维晶体管装置如本发明实施例所述的半导体装置201可实施本发明实施例的概念。用于此处所述的实施例的一些例示性装置可包含鳍状场效晶体管、水平的全环绕式栅极场效晶体管、垂直的全环绕式栅极场效晶体管、纳米线通道场效晶体管、应变的半导体装置、绝缘层上硅装置、或其他装置，其可因预处理工艺减少负载效应及/或取决于基板的成长相关的问题而得利。
图1为多种实施例中，制作半导体装置240的例示性方法其流程图100。图2为半导体装置240的一例的三维图。图3A、图3B至图8A、图8B以及图11a、图11B至图12A、图12B，为依据图1的流程图的多种阶段制作的半导体装置240其部分的剖视图。值得注意的是，流程100可用于形成此处未述的任何其他半导体结构。本领域技术人员应认识到，用于形成半导体装置的完整工艺与其相关结构，并未图示或说明于此。虽然多种步骤已图示及说明于此，但这些步骤的顺序或步骤之间是否存在其他步骤并局限于此。此处所示或所述的步骤顺序除非特别说明，其仅用于解释目的而非排除实际上个别步骤同时或至少部分地同时进行的可能性。
流程100一开始的步骤102提供半导体装置240。半导体装置240具有鳍状物274形成于半导体基板270上。半导体基板270可为或可包含基体半导体基板、绝缘层上半导体基板、或类似物，且可未掺杂或掺杂有p型或n型掺质。在一些实施例中，半导体基板270的半导体材料可包含半导体元素如硅或锗；半导体化合物；半导体合金；或上述的组合。每一鳍状物274可提供主动区，即一或多个装置形成处。鳍状物274的制作方法可采用在半导体基板270上进行的合适工艺，其包含掩模、光光刻、及/或蚀刻工艺，以形成沟槽253至半导体基板270中，并保留自半导体基板270向上延伸的鳍状物。接着可将绝缘材料如氧化物(例如氧化硅)、氮化物、类似物、或上述的组合填入沟槽253。绝缘材料可凹陷以形成隔离区278，且凹陷方法可采用可接受的蚀刻工艺。绝缘材料凹陷后，鳍状物274可自相邻的隔离区278之间向上凸起。
半导体装置240具有栅极结构251形成于鳍状物274的上表面上。每一栅极结构251包含栅极介电层280、栅极层282于栅极介电层280上、与掩模284于栅极层282上，如图2所示。半导体装置240还包含源极/漏极区292于鳍状物274其相对于栅极结构251的两侧区中。图2还显示后续附图所用的参考剖面。剖面A-A可为沿着鳍状物274中两侧的源极/漏极区292之间的通道的平面。剖面B-B为垂直于剖面A-A的平面，且横越鳍状物274中的源极/漏极区292。后续附图对应这些参考剖面以清楚说明。下述附图中末尾为“A”的，指的是工艺的多种例子中对应剖面A-A的剖面图。下述附图中末尾为“B”的，指的是工艺的多种例子中对应剖面B-B的剖面图。
如图3A、图3B所示，形成栅极结构251于鳍状物274上。栅极结构251位于鳍状物274上，且延伸方向垂直于鳍状物274。栅极结构251可为栅极优先工艺中的可操作栅极堆叠，或者是置换栅极工艺中的虚置栅极堆叠。为简化说明，流程图100将以置换栅极工艺为基础进行说明。在置换栅极工艺中，栅极介电层280可为界面介电层，而栅极层282可为虚置栅极。用于栅极结构251的栅极介电层280、栅极层282、与掩模284可依序形成如个别的层状物，接着将这些层状物图案化成栅极结构251。举例来说，用于界面介电层的层状物可包含或可为氧化硅、氮化硅、类似物、或上述的多层。用于虚置栅极的层状物可包含或可为硅(如多晶硅)或另一材料。用于掩模的层状可包含或可为氮化硅、氮氧化硅、氮碳化硅、类似物、或上述的组合。上述层状物的形成方法或沉积方法可为任合适的沉积技术。举例来说，接着可图案化用于栅极介电层280、栅极层282、与掩模284的层状状物以形成栅极介电层280、栅极层282、与掩模284以用于每一栅极堆叠251，且其图案化方法可采用光光刻与一或多道蚀刻工艺。
步骤104沿着栅极结构251的侧壁(比如栅极介电层280、栅极层282、与掩模284的侧壁)形成栅极间隔物286，且栅极间隔物286还形成于鳍状物274上。举例来说，栅极间隔物286的形成方法可为顺应性地沉积用于栅极间隔物286的一或多个层状物，并非等向蚀刻一或多个层状物。用于栅极间隔物286的一或多个层状物包含的材料，可不同于用于栅极结构251的材料。在一些实施例中，栅极间隔物286可包含或可为介电材料如碳氧化硅、氮化硅、氮氧化硅、氮碳化硅、类似物、上述的多层、或上述的组合，且其沉积方法可为任何合适的沉积技术。接着可进行非等向的蚀刻工艺，移除间隔物层的部分以形成栅极间隔物286，如图4A、图4B所示。
在形成栅极间隔物286之后，可形成源极/漏极区292于鳍状物274中，如图4A、图4B所示。在一些例子中，可采用栅极结构251与栅极间隔物286作为朝罩，并蚀刻凹陷至鳍状物中(比如形成凹陷于栅极结构251的两侧上)。接着可外延成长材料于凹陷中，以形成源极/漏极区292。源极/漏极区292的形成方法可改用或额外注入掺质至鳍状物274及/或外延的源极/漏极区292中，且注入方法采用栅极结构251作为掩模，以形成源极/漏极区于栅极结构251的两侧上。
用于源极/漏极区292的材料取决于晶体管的导电型态，其可包含或可为硅锗(SixGe1-x，其中可介于约0至1之间)、碳化硅、磷化硅、碳磷化硅、纯锗或实质上纯锗、III-V族半导体化合物、II-VI族半导体化合物、或类似物。举例来说，用于III-V族半导体化合物的材料可包含砷化铟、砷化铝、砷化镓、磷化铟、氮化镓、砷化铟镓、砷化铟铝、锑化镓、锑化铝、磷化铝、磷化镓、或类似物。在一些例子中，用于p型装置的源极/漏极区292可包含硅锗，而用于n型装置的源极/漏极区292可包含碳磷化硅或磷化硅。如图4A、图4B所示，由于隔离区278的阻挡，源极/漏极区292中的材料先垂直地成长于凹陷中，此时源极/漏极区292不会水平地成长。在完全填入凹陷之后，用于源极/漏极区292的材料可垂直地与水平地成长以形成晶面，其可对应半导体基板270的结晶平面。在一些例子中，用于p型装置与n型装置的外延源极/漏极区的材料不同。凹陷工艺或外延成长时采用合适的掩模，可在不同装置中采用不同材料。
步骤106视情况依序形成接点蚀刻停止层296与第一层间介电层297于源极/漏极区292的表面、栅极间隔物286的侧壁与上表面、掩模284的上表面、与隔离区278的上表面上，且其形成方法采用任何合适的沉积技术。顺应性地沉积的接点蚀刻停止层296，可包含或可为氮化硅、氮碳化硅、碳氧化硅、氮化碳、类似物、或上述的组合。第一层间介电层297可包含或可为四乙氧基硅烷的氧化物、氧化硅、或低介电常数介电材料(比如介电常数低于氧化硅的材料)。接着可进行化学机械研磨工艺以平坦化第一层间介电层297与接点蚀刻停止层296，并移除栅极结构251的掩模284，使第一层间介电层297与接点蚀刻停止层296的上表面与栅极层282的上表面齐平。
栅极结构251的移除方法可用一或多道蚀刻工艺。移除栅极结构251后，形成凹陷于栅极间隔物286之间(即移除栅极结构251处)，并经由凹陷露出鳍状物274的通道区。接着形成置换栅极结构228a与228b于凹陷(即移除栅极结构251处)中。置换栅极结构228a与228b各自包含界面介电层220、栅极介电层222、一或多个视情况形成的顺应层224、与栅极226，如图5A所示。界面介电层220沿着通道区形成于鳍状物274的上表面上。界面介电层220可为热氧化或化学氧化鳍状物274所形成的氧化物如氧化硅，及/或采用任何合适沉积技术形成的氧化物(如氧化硅)、氮化物(如氮化硅)、及/或另一介电层。
栅极介电层222可顺应性地沉积于凹陷(即移除栅极堆叠处)中，比如沉积于界面介电层220上与栅极间隔物286的侧壁上。栅极介电层222还可顺应性地沉积于第一层间介电层297、接点蚀刻停止层296、与栅极间隔物286上。栅极介电层222可为或包含氧化硅、氮化硅、高介电常数介电材料、上述的多层、或其他介电材料。高介电常数介电材料的介电常数可大于约4.0，且可包含铪、铝、锆、镧、镁、钡、钛、或铅的金属氧化物或今属硅酸盐、上述的多层、或上述的组合。
一或多个顺应层224可包含一或多个阻挡及/或盖层，与一或多个功函数调整层。一或多个阻挡及/或盖层可包含氮化钽、氮化钛、类似物、或上述的组合。一或多个功函数调整层可包含或可为碳化铝钛、氧化铝钛、氮化铝钛、类似物、或上述的组合。用于一或多个功函数调整层、阻挡层、及/或盖层的材料选择，可使晶体管如p型场效晶体管或n型场效晶体管达到所需的临界电压。用于栅极226的层状物形成于一或多个顺应层224(若实施)上，及/或形成于栅极介电层222上。用于栅极226的层状物可填入剩余的凹陷(即移除栅极堆叠处)。用于栅极226的层状物可为或可包括含金属材料，比如钨、钴、铝、钌、铜、上述的多层、上述的组合、或类似物。
平坦化工艺如化学机械研磨，可移除用于栅极226、一或多个顺应层224、与栅极介电层222的层状物其高于第一层间介电层297、接点蚀刻停止层296、与栅极间隔物286的上表面的部分。如此一来，可形成含有栅极226、一或多个顺应层224、栅极介电层222、与界面介电层220的置换栅极结构228a与228b，如图5A所示。
步骤108形成第二层间介电层230于栅极226、一或多个顺应层224、栅极介电层222、第一层间介电层297、栅极间隔物286、与接点蚀刻停止层296上，如图6A所示。第二层间介电层230可包含或可为氧化硅、低介电常数介电材料(如氮氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、硼磷硅酸盐玻璃、未掺杂的硅酸盐玻璃、氟化硅酸盐玻璃、有机硅酸盐玻璃、碳氧化硅、旋转涂布玻璃、旋转涂布聚合物、硅碳材料、上述的化合物、上述的复合物、类似物、或上述的组合。
在形成第二层间介电层230之后，形成源极/漏极接点开口232穿过第二层间介电层230、第一层间介电层297、与接点蚀刻停止层296以达源极/漏极区292，并露出源极/漏极区292的至少部分，如图6A所示的例子。举例来说，图案化第二层间介电层230、第一层间介电层297、与接点蚀刻停止层296以具有源极/漏极接点开口232的方法，可采用光光刻与一或多道蚀刻工艺。一或多道蚀刻工艺可为干蚀刻工艺、深反应离子性蚀刻工艺、或任何合适的非等向蚀刻工艺。在一例中，干蚀刻工艺采用感应耦合等离子体或电容耦合等离子体，其包含氧、氩、与一或多种氟为主的化学剂(如六氟丁二烯、八氟环丁烷、或四氟化碳)，以形成源极/漏极接点开口232。如此一来，源极/漏极接点开口232的侧壁垂直，虽然其可具有小倾斜角度。源极/漏极接点开口232可用于形成电性接点至晶体管的源极/漏极区292。
在形成源极/漏极接点开口232之后，可进行硅化物的预清洁工艺，以自露出的源极/漏极区292的表面移除原生氧化物(如氧化硅)。原生氧化物的形成原因形成源极/漏极接点开口232时，源极/漏极区292暴露至多种蚀刻剂。例示性的硅化物的预清洁工艺可包含采用稀氢氟酸水相溶液的湿式清洁、采用等离子体(如三氟化氮与氨等离子体)的干式清洁、或上述的组合。硅化物的预清洁采用的化学剂，可移除原生氧化物如源极/漏极区292的上侧部分，以形成U型沟槽231于源极/漏极区292的上表面。U型沟槽231具有底部237与侧壁239，如图6A所示。
步骤110形成顺应性的金属层210于露出的源极/漏极区292其表面上(比如U型沟槽231其侧壁239与底部237)，以及第二层间介电层230、第一层间介电层297、与接点蚀刻停止层296的表面上，如图7A图7B示。金属层210在U型沟槽231的底部237的厚度，大于金属层210在U型沟槽231的侧壁239、第二层间介电层230、第一层间介电层297、与接点蚀刻停止层296的表面上的厚度。举例来说，U型沟槽231的底部237的金属层210其厚度，以及U型沟槽231的侧壁239上、第二层间介电层230、第一层间介电层297、与接点蚀刻停止层296的表面上的金属层210其厚度之间的比例，可介于约2:1至约10:1之间，例如约4:1至约6:1之间。金属层210可为单层或多层堆叠。当金属层210采用单层时，金属层210可为或可包含钛、钽、或类似物。当金属层210采用多层堆叠(如双层)时，第一层可为或可包含钛、钽、或类似物，而第二层可为或可包含氮化钛、氧化钛、氮化钽、氧化钽、或类似物。第一层可形成于第二层上，反之亦然。不论情况为何，第一层的厚度可介于约至约之间，比如约至约之间，例如约而第二层的厚度可介于约至约之间，比如约至约之间，例如约金属层210的沉积方法可为原子层沉积、物理气相沉积、化学气相沉积、或任何合适的沉积技术。在采用双层的一些例子中，第一层的形成方法可为物理气相沉积，而第二层的形成方法可为原子层沉积。在一些实施例中，金属层210为钛层。在另一实施例中，金属层210为钛层与氮化钛层的堆叠。
步骤112使源极/漏极区292的上侧部分与金属层210反应，以形成硅化物层214于源极/漏极区292上，如图8A、图8B所示。举例来说，接着进行退火工艺以加热基板，使接触源极/漏极区292的金属层210产生硅化反应。硅化反应可产生于源极/漏极区292与金属层210之间的界面，以及源极/漏极区292与金属层210之间的界面周围及/或的外的区域。在金属层210采用层状物堆叠(如钛与氮化钛)的一些例子中，底层(如钛)可与源极/漏极区292反应并完全转变为硅化物层，而顶层(如氮化钛)的部分转变为硅化物层。举例来说，退火工艺可为快速热退火，其温度可介于约400℃至约650℃之间(比如约500℃)，且历时约10秒至约60秒之间。接着以攻击未反应的金属层210但不攻击硅化物层214的选择性蚀刻工艺，移除未反应的金属层210。由于底部237的金属层210其厚度可能大于侧壁296、第二层间介电层230、第一层间介电层297、与接点蚀刻停止层296的表面上的金属层210其厚度，在一些例子中的选择性蚀刻工艺(比如自第二层间介电层230、第一层间介电层297、与接点蚀刻停止层296的表面上移除未反应的金属层210)之后，未反应的金属层210(如钛与氮化钛堆叠中的氮化钛层)的部分仍可保留于硅化物层214上。保留于硅化物层214上的金属层210具有一些优势，因为其可作为阻挡层以避免后续工艺氧化硅化物层214。如图9、图10所示的例子，硅化物层214具有金属层210保留其上。
选择性蚀刻工艺可为任何合适的湿蚀刻或干蚀刻工艺。合适的湿蚀刻工艺可采用去离子水、氢氟酸为主的蚀刻化学剂、过氧化氢、氯化氢、或上述的组合，以选择性地移除未反应的金属层210。合适的干蚀刻工艺可采用含氧气体(如氧)与氟为主或碳氟或主的蚀刻化学剂的混合物，以选择性地移除未反应的金属层210。图8A、图8B还显示自第二层间介电层230、第一层间介电层297、与接点蚀刻停止层296的露出表面移除金属层210。
由于源极/漏极接点开口232的高深宽比(大于或等于约3:1)，因此硅化物层214会明显地形成于U型沟槽231的底部237，而最小化地或不形成于侧壁239的上侧部分。金属层210在侧壁239的上侧部分的覆盖率不良，可能造成退火之后只有少量或没有硅化物形成于侧壁239的上侧部分。换言的，硅化物层214并未覆盖侧壁239的上侧部分，且在硅化工艺后经由源极/漏极接点开口232露出源极/漏极区292的部分，如图9、图10所示。此例所述的用语“露出的源极/漏极区”或“源极/漏极区的露出表面”通常指的是源极/漏极接点开口232露出且硅化物层214未覆盖的源极/漏极区292其表面区，或者源极/漏极接点开口232露出且硅化物层214未物理接触或最小化地物理接触的源极/漏极区292其表面区。
在侧壁的上侧部分的露出的源极/漏极区292可能具有问题，因为后续填入源极/漏极接点开口232中的接点金属可能扩散穿过后续沉积的金属阻挡层(在硅化工艺之后，形成于接点金属与源极/漏极区292之间)，并与露出的源极/漏极区292反应。如此一来，不想要的金属硅化物可能形成于侧壁239的上侧部分及/或靠近侧壁239的上侧部分，这将导致装置的可信度问题。虽然较厚的金属阻挡层(比如大于或等于约2nm)可用以避免接点金属扩散并与露出的源极/漏极区292反应，但这会使后续的接点金属具有不良的的填隙能力。下述的多种实施例包含表面处理，其包含将源极/漏极区292的表面层转变成阻挡层。表面处理形成有效金属扩散阻挡层于源极/漏极区的露出表面，而不牺牲接点金属的填隙能力。
用于源极/漏极区的自对准扩散阻挡层
步骤114对露出的源极/漏极区292进行表面处理211，以形成扩散阻挡层213于露出的源极/漏极区292的表面，如图8A所示。扩散阻挡层213避免后续填入源极/漏极接点开口232中的接点金属，经由硅化物层214未覆盖的侧壁239其上侧部分扩散至下方的源极/漏极区292并与其反应。在多种实施例中，表面处理211为氮化工艺。氮化工艺可包括将露出的源极/漏极区292暴露至含氮等离子体或含氮环境，使氮原子与位于源极/漏极区292的露出表面的原子反应，形成氮化物层或氮化物区于源极/漏极区292的上侧部分。因此氮化工艺形成自对准的侧壁组障层于源极/漏极区292的露出表面。氮化工艺可额外或改为包含将露出的源极/漏极区292的表面暴露至氮分子或原子态的氮自由基与离子，以将氮注入至露出的源极/漏极区292的表面中，因此源极/漏极区292的上侧部分其表面或区域与氮反应形成氮化的源极/漏极区(如注入工艺的结果)。
图9、图10为实施例中，图8A的源极/漏极区在表面处理之后的部分放大图。图9、图10显示氮化后的源极/漏极区292其露出区域或表面层。特别的是，氮化反应发生在硅化物层214未覆盖的露出的源极/漏极区292中。露出的源极/漏极区292的氮化反应的深度，可依应用与进行的表面处理变化。图9为一实施例中，在U形沟槽231的侧壁239其上侧部分，氮扩散至源极/漏极区292的露出表面中，使源极/漏极区292其至少表面层转变为表面氮化物层215。在多种实施例中，表面氮化物层215其厚度(自侧壁239的表面算起)介于约0.1nm至约5nm之间，比如约0.5nm至约1.8nm之间，例如约0.8nm至约1.5nm之间。图10显示另一实施例，在完成表面处理后，氮扩散穿过源极/漏极区292的露出表面，并将源极/漏极区292的整个上侧部分转变为氮化物区217。图10还显示氮可延伸穿过源极/漏极区292的整个上侧部分(比如自侧壁239的表面延伸至图8A所示的源极/漏极区292与栅极间隔物286之间的界面)，并向下传递至低于硅化物层214的顶部。
氮化物区271可具有自氮化物区217的上表面(可与源极/漏极区292的顶部共平面)至氮化区的底部的尺寸G1。源极/漏极区292可具有自源极/漏极区292的顶部至源极/漏极区292的底部的尺寸G2。在多种实施例中，尺寸G1与尺寸G2之间的比例可介于约1:3至约1:20之间，比如约1:5至约1:8之间，例如约1:6至约1:7之间。上述比例变化可取决于氮化工艺所用的参数以及源极/漏极区292的尺寸。保留于硅化物层214上的金属层210可具有自金属层210的顶部至金属层210的底部的尺寸G3。硅化物层214可具有自硅化物层214的顶部至硅化物层214的底部的尺寸G4。在多种实施例中，尺寸G3与尺寸G4之间的比例可介于约1:2至约1:6之间，比如约1:3至1:5之间，例如约1:4。侧壁239可具有自侧壁239的顶部(其可与源极/漏极区292共平面)至侧壁239的底部(其可与硅化物层214的底部共平面)之间的尺寸G5。在多种实施例中，尺寸G1与尺寸G5之间的比例可介于约1:2至约1:10之间，比如约1:4至约1:8之间，例如约1:5至1:6之间。在一些例子中，侧壁239不必延伸至硅化物层214的所有深度。尺寸G4与尺寸G5之间的比例可介于约1:1至约8:1之间，比如约2:1至约6:1之间，例如约3:1至约5:1之间。在氮化物区(如表面氮化物层215及/或氮化物区217)中，氮原子密度可介于1×1021cm-3至3×1021cm-3之间，而氮原子％可介于0％至60％之间。
氮化表面层或源极/漏极区的整个上侧部分具有一些优势，因为可形成有效金属扩散阻挡层于露出的表面之中及/或露出的源极/漏极区292之中，而不需成长额外阻挡层以用于阻挡接点金属扩散。因此可减少源极/漏极接点开口232中的阻挡层总厚度，进而提供更多空间给后续形成的接点金属。如此一来，可增加接点金属填隙工艺的容忍度。
氮化工艺可为等离子体氮化工艺，其采用电容耦合等离子体或感应耦合等离子体。可在半导体基板270所在的工艺腔室中原位产生氮等离子体，或者在远端等离子体腔室中形成氮等离子体，之后再使氮等离子体流入半导体基板270所在的工艺腔室中。露出的源极/漏极区292可暴露至射频等离子体，且射频等离子体可由工艺气体形成。工艺气体由下述物质组成，或基本上由下述物质组成，或包括：含氮气体如氮气、氨、一氧化氮、一氧化二氮、氮与氢的组合气体、及/或上述的任何混合物。工艺腔室的压力可维持于约1mTorr至约20Torr之间，比如约10mTorr至约10Torr之间，比如约60mTorr至约1Torr之间。可视情况将钝气如氩、氦、或氖气加入工艺气体。在一例中，工艺气体包含氮与氩。在另一例中，工艺气体包含氨与氩。在又一实施例中，工艺气体包括氮与氦。在一些实施例中，含氮气体以第一体积流速流入工艺腔室中，钝气以第二体积流速流入工艺腔室中，且第一体积流速与第二体积流速之间的比例可控制于约1:2至约1:10之间，比如约1:3至1:8之间，例如约1:4至约1:6之间。对300mm的基板而言，含氮气体的流速可介于约50sccm至约6000sccm之间，比如约200sccm至约2000sccm之间，例如约600sccm至约1000sccm之间。若采用钝气，则钝气的流速可介于约25sccm至约12000sccm之间，比如约400sccm至约8000sccm之间，例如约800sccm至约5000sccm之间。依据应用与工艺腔室的设置，可采用其他气体组成及/或流速。半导体基板270的温度可维持于约20℃至约600℃之间，比如约50℃至约450℃之间，例如约80℃至约200℃之间。在将工艺气体导入工艺腔室之后，可将射频源耦接至工艺气体以形成等离子体。射频源功率可介于约20W至约5000W之间，比如约50W至约1000W之间，例如约100W至约300W之间。射频源功率可具有任何合适的射频频率，比如介于约2MHz至约60MHz之间，例如约13.56MHz。等离子体可脉冲地或连续地施加，且高达约1200W的有效功率。举例来说，可连续施加高达约400W的等离子体，其历时约10秒至约300秒之间，比如约20秒至约120秒之间，例如约40秒至约90秒之间。可调整射频源功率的时间，以控制扩散或并入源极/漏极区其露出表面的氮量。在采用脉冲等离子体的例子中，等离子体的脉冲频率可介于约2kHz至约20kHz之间，比如约4kHz至约15kHz之间。等离子体在高达3000W的峰值功率下，其占空比可介于约2％至约50％之间，比如约6％至约30％之间，例如约20％。类似地，可调整占空比及/或射频源功率，以控制氮扩散或并入源极/漏极区292的露出表面中。在一些例子中，脉冲等离子体在高达2000W的峰值功率下，其占空比可介于约5％至20％之间。
在等离子体氮化工艺时，可不对半导体基板270施加偏压。在此例中，可由等离子体电位加速离子化的氮物种，接着将其注入或合并到源极/漏极区292的露出表面中。可额外地或改为施加偏压至半导体基板270，以进一步加速来自等离子体的离子，使其较深地注入或合并至源极/漏极区292的露出表面中。偏压还有助于氮离子与第二层间介电层230、第一层间介电层297、与接点蚀刻停止层296的介电材料之间的反应最小化。直流电流或射频偏压均可用于提供偏压至半导体基板270。偏压可介于约10W至约500W之间，比如约50W至约300W之间，例如约100W至约250W；而频率可介于约10MHz至约30MHz，例如约13.56MHz。在一些例子中，可自等离子体过滤或移除氮离子，因此只有含氮自由基如N、NH、或NH2导向源极/漏极区292的露出表面。
在任何情况下，等离子体产生的含氮自由基及/或氮离子可并入露出的源极/漏极区292，以将源极/漏极区的表面或至少上侧部分转变为氮化的源极/漏极区，比如图9、图10所示的表面氮化物层215或氮化物区217。在露出的源极/漏极区292包含硅锗的例子中，氮化工艺可将硅锗的至少部分转变为氮化的硅锗。
上述内容为等离子体氮化工艺，但氮化工艺可为任何其他合适技术如热氮化工艺、离子注入工艺、或可产生氮物种或自由基的任何合适工艺。举例来说，一些实施例进行热氮化，而半导体装置240可位于具有氮环境的热工艺腔室中。热工艺腔室可为炉或快速热工艺腔室。氮环境的形成方法可为提供工艺气体，其可由下列物质组成、基本上由下列物质组成、或包括含氮气体如氮、氨、一氧化氮、一氧化二氮、氮与氢的组合气体、及/或上述的任何混合物。热工艺腔室中的温度可维持于约650℃至约1200℃之间，比如约750℃至约1000℃之间。在一例中，露出的源极/漏极区292包含硅锗，而热氮化可将硅锗的至少部分转换成氮化硅锗。
又一实施例进行离子注入工艺，可将氮离子注入至源极/漏极区292的露出表面中，以形成氮化物层如氮化硅锗层于露出的源极/漏极区292其表面。在离子注入工艺中，工艺气体可由下述物质组成、基本上由下述物质组成、或包括含氮气体，比如氮、氨、一氧化氮、一氧化二氮、氮与氢的组合气体、及/或上述的任何混合物，其可形成氮离子以提供至半导体基板270位于其中的工艺腔室。接着能量化工艺气体以形成氮离子，并将氮离子注入至露出的源极/漏极区292中。注入氮离子的离子注入能量可介于约5eV至约650eV之间，比如约20eV至约250eV之间，例如约50eV至约150eV之间。
步骤116视情况顺应性地沉积阻挡层219于硅化物层214上的源极/漏极接点开口232中、扩散阻挡层213(比如图9、图10所示的表面氮化物层215与氮化物区217)的露出表面上、以及第二层间介电层230、第一层间介电层297、与接点蚀刻停止层296上，如图11A、图11B所示。阻挡层219的厚度可为约2nm或更小，比如约1.9nm或更小，或比如约1.6nm。在一些实施例中，阻挡层219的厚度介于约1.30nm至约1.87nm之间。阻挡层219可为或包含氮化钛、氧化钛、氮化钽、氧化钽、任何合适的过渡金属氮化物或氧化物、类似物、或上述的任何组合，且其沉积方法可为原子层沉积、化学气相沉积、等离子体增强化学气相沉积、高密度等离子体化学气相沉积、低压化学气相沉积、物理气相沉积、或任何合适的沉积技术。在一例子中，阻挡层为氮化钛，且其沉积方法为原子层沉积。
由于扩散阻挡层213(如图9、图10所示的表面氮化物层215或氮化物区217)形成于露出的源极/漏极区292之中及/或表面区中，阻挡层219的厚度可小于现有技术阻挡层(形成于露出的源极/漏极区292上而无扩散阻挡层213形成其间)的厚度。举例来说，阻挡层219的厚度可比现有技术的阻挡层厚度缩小约18％至约23％，比如缩小约20％。阻挡层219与扩散阻挡层213一起形成于源极/漏极区292的露出表面，可提供有效阻挡于源极/漏极区292的上侧部分(比如U形沟槽231的侧壁239其上侧部分)，以避免后续填入源极/漏极接点开口232中的接点金属扩散穿过阻挡层219，并与下方的源极/漏极区292反应形成任何不想要的金属硅化物。不想要的金属硅化物将造成装置的可信度问题。当阻挡层的总厚度保持在低于2nm时，阻挡层219与扩散阻挡层213可具有良好的阻挡特性，其可确保良好的填隙能力以用于后续沉积的金属接点。此外，扩散阻挡层213(如图9所示的表面氮化物层215或氮化物区217)包含氮，可确保后续沉积于源极/漏极区292的氮化物表面上的层状物具有优异的顺应性，使后续沉积于源极/漏极接点开口232中的层状物其填隙能力的影响最小化。在后续形成的阻挡层219其沉积方法为原子层沉积时，含氮的扩散阻挡层213可促进其与原子层沉积的一或多个前驱物之间的反应，以形成阻挡层219如过渡金属氮化物(例如氮化钛)，以缩短扩散阻挡层213上的阻挡层219其完成时间。
步骤118可沉积导电材料221(如接点金属)于阻挡层219(若形成)上，并填入源极/漏极接点开口232。导电材料221可为或包含钴、钨、铜、钌、铝、金、银、上述的合金、类似物、或上述的组合，且其沉积方法可为化学气相沉积、原子层沉积、物理气相沉积、电化学镀制、或任何合适的沉积技术。举例来说，在沉积导电材料221之后，可采用平坦化工艺如化学机械研磨移除多余的导电材料221与阻挡层219。平坦化工艺可移除高于第一层间介电层297其上表面的多余导电材料221与阻挡层219。因此导电材料221、阻挡层219、与第一层间介电层297的上表面可共平面。
图13为一些实施例中，图8A的剖视图的一部分，以进一步说明额外细节。源极/漏极接点开口232穿过第二层间介电层230、第一层间介电层297、与接点蚀刻停止层296以达源极/漏极区292。源极/漏极接点开口232在第二层间介电层230的上表面的平面中，以及在自一置换栅极结构垂直延伸至相邻的置换栅极结构的方向上具有第一尺寸D1。源极/漏极接点开口232还具有自第二层间介电层230的上表面的平面至源极/漏极区292的上表面的第二尺寸D2。源极/漏极接点开口232在沿着源极/漏极区292的上表面，以及在自一置换栅极结构垂直延伸至相邻的置换栅极结构的方向上具有第三尺寸D3。第一尺寸可介于约10nm至约30nm之间，第二尺寸D2可介于约30nm至约100nm之间，而第三尺寸D3可介于约8nm至约30nm之间。第二尺寸D3与第一尺寸D1之间的比例(如深宽比)可大于2，比如介于约3至约10之间。第二尺寸D2与第三尺寸D3之间的比例可介于约2至约10之间。
硅化物层214沿着源极/漏极区292的上表面横向地延伸，且在自一置换栅极结构垂直地延伸至相邻的置换栅极结构的方向上具有第四尺寸D4。硅化物层214具有自硅化物层214的上表面延伸至硅化物层214的下表面的第五尺寸D5。扩散阻挡层213具有自源极/漏极区292的上表面至硅化物层214的上表面的第六尺寸D6。扩散阻挡层213具有自源极/漏极区292的侧壁表面延伸至源极/漏极区292中的第七尺寸D7。源极/漏极区292具有自源极/漏极区292的上表面至源极/漏极区292的底部的第八尺寸D8。第四尺寸D4可介于约8nm至约40nm之间，第五尺寸D5可介于约3nm至约20nm之间，第六尺寸D6可介于约0.5nm至约10nm之间，第七尺寸D7可介于约0.1nm至约5nm之间(比如约0.2nm至约3nm之间，例如约1nm)，第八尺寸D8可介于约20nm至约70nm之间，且第九尺寸D9可介于约1nm至约6nm之间(比如约1nm至约4nm之间，例如3nm)。第四尺寸D4与第三尺寸D3之间的比例可大于1，比如介于约1至约1.3之间。第四尺寸D4与第五尺寸D5之间的比例可大于1，比如介于约1至约5之间。第六尺寸D6与第七尺寸D7之间的比例可大于1，比如介于约1至3之间。第四尺寸D4与第七尺寸D7之间的比例可大于3，比如介于约5至20之间，例如约8至12之间。第六尺寸D6与第八尺寸D8之间的比例，可小于约0.8，比如介于约0.1至约0.6之间，例如约0.3至约0.5之间。第九尺寸D9与第七尺寸D7之间的比例可大于1，比如介于约2至15之间，例如约12。在一些例子中，第七尺寸D7可横向地延伸至源极/漏极区292中，以达源极/漏极区292的边缘(比如源极/漏极区292与栅极间隔物286之间的界面)。
保留于硅化物层上的金属层210可具有自金属层210的顶部到金属层210的底部的第九尺寸D9。在一些例子中，第九尺寸D9与第五尺寸D5之间的比例可介于约1:2至约1:6之间，比如介于约1:3至约1:5之间，例如约1:4。
依据流程图100制作半导体装置240，可进行后续工艺以形成多种结构与区域。举例来说，后续工艺可形成多种接点/通孔/线路与内连线结构的多层(如金属层与层间介电层或金属间介电层)于包含半导体装置240的基板270上，其设置以连接多种结构以形成功能电路。功能电路可包含一或多个装置如一或多个半导体装置240。多种内连线结构可采用多种导电材料，其包含铜、钨、及/或硅化物。在一例中，可采用镶嵌及/或双镶嵌工艺，以形成铜相关的多层内连线结构。此外，可在流程图100之前、之中、与之后实施额外工艺步骤，且可依应用置换或省略一些上述步骤。
用于移除氧化物及钝化氧化的金属阻挡层的等离子体处理
如前述的步骤112，选择性的蚀刻工艺可用于移除源极/漏极接点开口232中残留的未反应金属层210。然而源极/漏极接点开口232的高深宽比，因此金属层210在底部237的厚度较大，且在侧壁239、第二层间介电层230、第一层间介电层297、与接点蚀刻停止层296的表面上的厚度较小。如此一来，一些例子在自侧壁239、第二层间介电层230、第一层间介电层297、与接点蚀刻停止层296的表面完全移除未反应的金属层210之后，仍可保留未反应的金属层210其一部分(比如钛层与氮化钛层堆叠中的氮化钛层)于硅化物层214上。由于保留于硅化物层214上的未反应金属层210可作为阻挡层以避免氧化硅化物层214，在硅化工艺与形成接点金属的工艺之间及/或之中的多种工艺可能使阻挡层大幅氧化。举例来说，在采用双层金属层210(比如钛层与氮化钛层的堆叠)时，选择性蚀刻工艺可移除氮化钛层的表面部分，并使氮化钛层的底部(以及一些例子中下方的钛层)保持完整。由于氮化钛层暴露至选择性蚀刻工艺所用的蚀刻剂(在前述的步骤112中用以移除未反应的金属层210)，及/或暴露至再沉积阻挡层219所用的前驱物(在前述的步骤116中阻挡层219采用过渡金属氧化物时)，保留于硅化物层214上的氮化钛层(特别是氮化钛层的表面层)将大幅氧化。硅化物层214上大幅氧化的阻挡层，可能大幅增加硅化物层与接点金属区之间的接点电阻。如此一来，可能劣化或危及装置可信度。
下述的多种实施例提供有效且无损伤的方法，以自形成于硅化物层上的阻挡层移除氧化物。特别的是，阻挡层可恢复成初始状态，处理之后可再次使用。图14多种实施例中，处理半导体装置(如半导体装置240)的例示性方法其流程图1400。图15、图16为一些实施例中，依据图14的流程图制作的半导体装置240于多种阶段的部分剖视图(沿着通道方向)。
流程图1400一开始的步骤1402提供半导体装置(如半导体装置240)到工艺腔室(如化学气相沉积腔室、等离子体增强化学气相沉积腔室、或任何合适的等离子体腔室)中。图15为形成硅化物(步骤112)与表面处理(步骤114)之间的中间阶段内的半导体装置240。图15所示的半导体装置240与图8A所示的半导体装置240实质上一样，差别在硅化物层214具有大幅氧化的阻挡层1502形成其上。如上所述，由于金属层210暴露至选择性蚀刻工艺(步骤112)及/或再沉积阻挡层219(步骤116)所用的蚀刻剂与前驱物，因此可大幅氧化阻挡层1502。如前所述，金属层210可为双层，其中第一层可为或可包括钛、钽、或类似物，而第二层可为或可包括氮化钛、氧化钛、氮化钽、氧化钽、或类似物。在图15所示的例子中，大幅氧化的阻挡层1502包含钛的第一层1504与氮化钛的第二层。在一些例子中，第一层1504不存在于硅化物层214于第二层1506之间。举例来说，硅化工艺可消耗源极/漏极区292的所有第一层1504，以形成硅化物层214。图15中的1510为图15中虚线圈部分局部放大图，其显示钛的第一层1504位于硅化物层214与氮化钛的第二层1506之间，其中氮化钛的第二层1506具有氧化表面层1508。氧化表面层1508的形成方法为大幅氧化第二层1506。虽然此处以钛进行说明，但此概念可等效应用于任何金属或介电材料。
步骤1404将半导体装置240置入工艺腔室中，以进行预清洁工艺1512。预清洁工艺1512可包含采用第一等离子体处理对金属阻挡氧化物进行还原工艺，接着采用第二等离子体处理对还原的金属阻挡层进行钝化工艺，以避免金属阻挡层进一步氧化。在还原工艺中，可将还原剂导入真空腔室，并将频率功率耦接至还原剂以起始等离子体。等离子体可激发还原剂至能量化的离子状态。能量化的离子可与金属氧化物进行化学反应，以自氧化表面层1508移除氧，并还原金属氧化物为金属。
在多种实施例中，还原剂可为氢原子(如氢分子解离而成的氢原子)、氢自由基、及/或能量激发的氢之中性物种，其可由原位的含氢气体所产生，或由远端等离子体反应中的含氢气体所产生。远端等离子体反应器与半导体装置240置于其中的工艺腔室分开。合适的含氢气体可包括氢、氨、联胺、或上述的任何组合。
当第二层1506为氮化钛时，氧化表面层1508可具有Ti-O-N键结/或Ti-O键结于晶格的表面部分。在第一等离子体处理时，来自还原剂的氢的能量化的离子、自由基、及/或中性物种，可破坏氧化表面层1508其表面部分中的Ti-O-N键结及/或Ti-O键结，以与氧化表面层1508进行化学反应。自氧化表面层1508离去的氧可与氢反应，产生副产物如水并在晶格中留下氧空缺。第一等离子体处理可移除氧，而不损伤阻挡层1502其表面部分的晶格。如此一来，可保留阻挡层的晶格与厚度。
在减少氧化表面层1508之后，可对半导体装置240进行第二等离子体处理(如氮等离子体)，以将氮并入自晶格移除氧所产生的氧空缺。氮与钛键结以形成氮化钛于阻挡层1502的表面中。如此一来，阻挡层1502的表面部分可恢复至其初始状态(如氮化钛)。氮等离子体还以氮钝化阻挡层1502的表面，以避免在后续工艺中再氧化阻挡层1502。氮等离子体可由原位的含氮气体形成，或由远端等离子体反应器中的含氮气体形成。远端等离子体反应器与半导体装置240位于其中的工艺腔室分开。合适的含氮气体可包含氮、氨、或上述的组合。
除了采用两种不同的等离子体工艺，一些实施例中的预清洁工艺1512为单一等离子体处理，其可采用含氢与氮的反应剂以进行化学还原，并在预清洁工艺中钝化氧化表面层1508。在此例中，反应剂可为上述含氢气体及/或含氮气体的一或多种的气体或气体混合物。在一些实施例中，反应剂为氨。在一些实施例中，反应剂为氢与氮。在一些实施例中，反应剂为氢与氨。在一些实施例中，反应剂为氮与氨。在一些实施例中，反应剂为氢。在一些实施例中，反应剂为氮。
在任何情况下，可不施加偏压至半导体基板270。此例可由等离子体电位加速离子化的氢及/或氮物种，接着在预清洁工艺1512中将离子化的氢及/或氮物种并入氧化表面层1508中。偏压可额外地或改为施加至半导体基板270，以进一步加速来自等离子体的离子，并将离子更深地注入或并入氧化表面层1508中。偏压还有助于氢及/或氮离子与第二层间介电层230、第一层间介电层297、与接点蚀刻停止层296的介电材料之间的反应最小化。直流电流或射频偏压均可用于提供偏压至半导体基板270。若需要的话，可在一或多个处理循环中进行预清洁工艺，并在循环之间清除预清洁工艺。
在至少一些实施例中，采用氢与氮还原氧化表面层1508(如氧化钛)时，例示性工艺参数包含基板温度与腔室压力。基板温度可维持在介于约室温至约450℃之间，比如约150℃至约350℃之间，例如约200℃。而腔室压力可维持在介于约1mTorr至约10Torr之间，比如约1.5mTorr至约10mTorr之间，例如约2mTorr至约5mTorr之间。产生等离子体的方法可为自双频射频功率源施加功率，其中第一射频功率的频率介于约1MHz至约60MHz之间，例如约13.56MHz；而功率介于约200W至约1000W之间，比如约600W至约950W之间，例如约900W。第二射频功率的频率介于约10kHz至约20MHz之间，例如约100kHz至约500kHz之间；而功率介于约1W至约200W之间，例如约150W。等离子体的功率密度可介于约1W/cm2至约10W/cm2之间，比如约2W/cm2至约8W/cm2之间，例如约4W/cm2至约6W/cm2之间。提供的偏压可介于约10W至约500W之间，比如约50W至约300W之间，例如约100W至约250W之间，且其频率可介于约10MHz至约30MHz之间，例如约13.56MHz。电极之间的空间(如基板与喷洒头之间的距离)可介于约200密耳(mil)至约1000密耳之间，例如约280密耳至约300密耳之间。提供至工艺腔室中的氢气其第一流速可介于约100sccm至约12000sccm之间，而提供至工艺腔室中的氮气其第二流速可介于约100sccm至约8000sccm之间。第一流速与第二流速之间的比例，可控制到介于约1:1至约6:1之间，比如约2.5:1至约5:1之间，例如约3:1至约4:1之间。此外，承载气体可结合上述的工艺参数，以助稳定气流与等离子体反应。承载气体如氦、氩、或氮的流速可介于约0sccm至2000sccm之间。预清洁工艺可历时约25秒至约180秒之间，比如约50秒至约80秒之间，例如约60秒至约70秒之间。可以预期的是这些参数可依应用、工艺腔室的设置、与所欲处理的材料调整。
不论预清洁工艺1512为单一步骤或双重步骤的等离子体处理，均可还原、处理、或改质氧化表面层1508。在预清洁工艺1512之后，氧化表面层1508可恢复为初始状态(如氮化钛)。处理后的阻挡层1502在其表面中具有最小化的氧含量。举例来说，经由X光光电子光谱技术量测预清洁工艺处理后的阻挡层表面(比如图16所示的阻挡层1514其钝化表面1509)，可发现其氧浓度降低至6％或更低(比如3％或更低)。举例来说，在预清洁工艺采用氢与氮作为反应剂时，表面氧浓度可降低至2.42％。在预清洁工艺采用氨作为反应剂时，表面氧浓度可降低至2.48％。当预清洁工艺采用氢作为反应剂时，表面氧浓度可降低至5.76％。当预清洁工艺采用氮作为反应剂时，表面氧浓度可降低至3.45％。在任何情况下，均可降低硅化物层与接点金属的界面区的接点电阻，并改善装置的可信度。
流程图1400所述的工艺可合并至流程图100，并可依任何所需的顺序或结合进行。举例来说，流程1400所述的工艺可在步骤112与步骤114之间进行。在一些实施例中，可省略或排除步骤114所述的表面处理。因此在步骤112之后，可进行流程1400所述的工艺，接着进行步骤步骤116。图16显示半导体装置240的一例，其依序形成阻挡层与导电材料(如阻挡层219与导电材料221)于处理的阻挡层1514(比如氮化钛层或钛层与氮化钛层的堆叠)上。图16中的1516为图16中虚线圈部分的局部放大图，即钛的第一层1504位于硅化物层214与氮化钛的第二层1506之间，并对氮化钛的第二层1506进行流程1400所述的预清洁工艺。在此例中，不提供扩散阻挡层(比如步骤114所述的扩散阻挡层213)于露出的源极/漏极区292其表面。因此第二层1506(如还原的阻挡层)可具有处理或钝化的表面1509。举例来说，虽然图16显示第一层1504，一些例子在硅化物层214与第二层1506之间可不存在第一层1504，即硅化工艺可消耗源极/漏极区292的第一层1504以形成硅化物层214。
此处所述的多种实施例可提供多种优点。应理解的是，此处不需说明所有优点，任何实施例不需具有特定优点，且其他实施例可提供不同优点。举例来说，此处所述的实施例包含的方法与结构关于表面处理工艺，其氮化露出的源极/漏极区以形成有效金属扩散阻挡层于露出的源极/漏极区的表面，并形成阻挡层于氮化区上。上述工艺可避免后续填入源极/漏极接点开口中的接点金属扩散穿过阻挡层，并与下方的源极/漏极区反应形成不想要的金属硅化物。不想要的金属硅化物可能造成装置的可信度问题。阻挡层与金属扩散阻挡层在维持阻挡层的总厚度至小于2nm时，仍保证优良的阻挡特性，其可确保后续沉积的金属接点具有优良的填隙能力。
在另一例中，此处所述的实施例其方法为预清洁工艺，其包含采用第一等离子体处理对金属阻挡氧化物进行还原工艺，接着采用第二等离子体处理对还原的金属阻挡层进行钝化工艺，以避免金属阻挡层进一步氧化。预清洁工艺可自金属阻挡氧化物移除氧，而不会损伤金属阻挡层其表面部分的晶格。如此一来，可维持阻挡层的厚度。特别的是，可降低硅化物与后续沉积的接点金属之间的界面其接点电阻。较少氧化且纯化的界面还可增进硅化物与接点的粘着力以提高可信度。
在一实施例中，提供半导体结构。半导体结构包括主动区于基板上，主动区包括源极/漏极区，源极/漏极区具有侧壁与自源极/漏极区的侧壁横向延伸的横向表面，源极/漏极区还包含自源极/漏极区的侧壁横向延伸至源极/漏极区中的氮化区；介电层，位于主动区上并具有对准源极/漏极区的所述侧壁的侧壁；以及导电结构，沿着介电层的侧壁至源极/漏极区，导电结构包含硅化物区，且硅化物区沿着源极/漏极区的横向表面并沿着源极/漏极区的侧壁的至少一部分。
在一些实施例中，上述半导体结构的导电结构还包括阻挡层形成于硅化物区上，其中阻挡层为过渡金属氮化物或过渡金属氧化物。
在一些实施例中，上述半导体结构的导电结构还包括导电材料形成于阻挡层上，且阻挡层物理接触导电材料。
在一些实施例中，上述半导体结构的氮化区具有第一厚度，阻挡层具有第二厚度，且第一厚度与第二厚度之间的比例介于1:2至1:15之间。
在一些实施例中，上述半导体结构的氮化区具有自源极/漏极区的上表面至硅化物区的上表面的第一尺寸，而源极/漏极区具有自源极/漏极区的上表面至源极/漏极区的下表面的第二尺寸，且第一尺寸与第二尺寸之间的比例介于0.1至0.6之间。
在另一实施例中，提供的方法包括形成源极/漏极区于基板上的主动区中，形成介电层于主动区上，形成开口穿过介电层，且开口延伸至源极/漏极区中以形成沟槽于源极/漏极区中，且下表面与侧壁至少部分地定义沟槽，形成硅化物区于沟槽的下表面，经由沟槽的侧壁氮化源极/漏极区的至少部分，以及将导电材料填入开口。
在一些实施例中，上述方法经由沟槽的侧壁氮化源极/漏极区的至少部分的步骤，将硅化物区未覆盖的侧壁暴露至来自等离子体的氮离子。
在一些实施例中，上述方法经由沟槽的侧壁氮化源极/漏极区的至少部分的步骤，将硅化物未覆盖的侧壁暴露至自等离子体产生的含氮自由基。
在一些实施例中，上述方法在将导电材料填入开口之前，还包括形成顺应性的阻挡层于开口中，且顺应性的阻挡层覆盖源极/漏极区的氮化部分。
在一些实施例中，上述方法在经由沟槽的侧壁氮化源极/漏极区的至少部分时，还包括施加偏压至基板。
在一些实施例中，上述方法经由沟槽的侧壁氮化源极/漏极区的至少部分的步骤，采用离子注入将氮注入至硅化物区未覆盖的沟槽侧壁中。
在另一实施例中，提供的方法包括形成源极/漏极区于基板上的主动区中，使形成于源极/漏极区的表面上的金属阻挡层与源极/漏极区反应形成金属硅化物于源极/漏极区的表面上，金属阻挡层具有金属氧化物于金属阻挡层的表面上，以及对金属阻挡层进行预清洁工艺，且预清洁工艺包括对金属氧化物进行还原工艺以及对还原的金属阻挡层进行钝化工艺。
在一些实施例中，上述方法的金属阻挡层包括氮化钛，而金属氧化物形成于氮化钛上。
在一些实施例中，上述方法的还原工艺包括将金属氧化物暴露至包括含氢气体与含氮气体的等离子体。
在一些实施例中，上述方法的含氢气体以第一流速导入工艺腔室，含氮气体以第二流速导入工艺腔室，而第一流速与第二流速之间的比例介于约1:1至约6:1之间。
在一些实施例中，上述方法的钝化工艺包括将氮并入还原的金属阻挡层中。
在一些实施例中，上述方法的还原工艺包括将金属氧化物暴露至氢自由基或氢的中性物种。
在一些实施例中，上述方法的氢自由基或氢的中性物种，由包括氨的气体或包括氢与氮的气体所形成。
在一些实施例中，上述方法在预清洁工艺时还包括施加偏压至基板。
在又一实施例中，提供的半导体结构包括主动区于基板上，且主动区包括源极/漏极区；介电层位于主动区上；以及导电结构穿过介电层以达源极/漏极区，且导电结构包括硅化物区于源极/漏极区的表面；第一阻挡层，形成于硅化物区上，且第一阻挡层包括过渡金属氮化物层于硅化物区上；第二阻挡层，位于第一阻挡层上，其中第一阻挡层与第二阻挡层之间的界面其表面氧浓度小于或等于3％；以及导电材料，位于第二阻挡层上并接触第二阻挡层。
在一些实施例中，上述半导体结构的过渡金属氮化物层为氮化钛或氮化钽。
在一些实施例中，上述半导体结构的第二阻挡层为氮化钛、氮化钽、或上述的组合。
在一些实施例中，上述半导体结构的第一阻挡层还包括第二过渡金属层于硅化物区上，且第二过渡金属层位于硅化物区与过渡金属氮化物层之间。
在一些实施例中，上述半导体结构的第二过渡金属层为钛或钽。
上述实施例的特征有利于本领域技术人员理解本发明。本领域技术人员应理解可采用本发明实施例作基础，设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本领域技术人员还应理解，这些等效置换并未脱离本发明构思与范畴，并可在未脱离本发明的权利要求的构思与范畴的前提下进行改变、替换、或更动。

Claims (1)

1.一种半导体结构，其特征在于，包括：
一主动区，位于一基板上，所述主动区包括一源极/漏极区，所述源极/漏极区具有一侧壁与自所述源极/漏极区的所述侧壁横向延伸的一横向表面，所述源极/漏极区还包含自所述源极/漏极区的所述侧壁横向延伸至所述源极/漏极区中的一氮化区；
一介电层，位于所述主动区上并具有对准所述源极/漏极区的所述侧壁的一侧壁；以及
一导电结构，沿着所述介电层的所述侧壁至所述源极/漏极区设置，所述导电结构包含一硅化物区，且所述硅化物区沿着所述源极/漏极区的所述横向表面并沿着所述源极/漏极区的所述侧壁的至少一部分。
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