CN110120422B - 用于p-通道沟槽mosfet的源极镇流 - Google Patents

用于p-通道沟槽mosfet的源极镇流 Download PDF

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CN110120422B
CN110120422B CN201910045713.2A CN201910045713A CN110120422B CN 110120422 B CN110120422 B CN 110120422B CN 201910045713 A CN201910045713 A CN 201910045713A CN 110120422 B CN110120422 B CN 110120422B
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trench
contact
conductivity type
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CN110120422A (zh
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雷燮光
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Alpha and Omega Semiconductor Cayman Ltd
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Abstract

一种沟槽金属‑氧化物‑半导体场效应晶体管(MOSFET)器件，包括一个第一导电类型的衬底、一个第二导电类型的本体区、一个形成在栅极沟槽中的栅极电极，在本体区和衬底中延伸，形成在本体区中的一个轻掺杂源极区和一个重掺杂源极区，以及一个沟槽接头，延伸到形成在接触沟槽中的本体区。制备一个第二导电类型的接触注入物，包围着接触沟槽的底部以及接触沟槽的侧壁部分，在接触沟槽的侧壁部分，它与轻掺杂源极区相接触，形成一个PN结。

Description

用于P-通道沟槽MOSFET的源极镇流
技术领域
本发明主要涉及金属-氧化物-半导体场效应晶体管(MOMSFET)，更确切地说是一种带有源极镇流电阻器的改良型沟槽MOSFET结构及其制备方法。
背景技术
微处理器和存储器件等集成电路含有多个金属-氧化物-半导体场效应晶体管(MOSFET)，提供基本的开关功能，以配置逻辑门、数据存储、电源开关等类似原件。为了处理慢速开关应用中的大电流，当图1A所示的MOSFET并联时，MOSFET之间的参数失配(例如导通电阻、阈值电压、通道长度)导致动态电流失衡，从而引起电流混乱。当绝大部分的电流流经多个并联MOSFET中的其中一个时，由于较低的阈值电压或通道长度，就会发生电流混乱。由于特定的MOSFET会消耗器件绝大部分的功率，从而限制了热点的发生。高温会进一步降低MOSFET的阈值电压，消耗更多的功率。最终，会导致热击穿。
众所周知，源极镇流可以提供负反馈，以对抗电流混乱。因此，为了避免电流混乱，通常增加一个源极镇流电阻器与每个MOSFET串联，如图1B所示，以平衡并联MOSFET上的负载电流分布。正是在这样的背景下，提出了本发明的实施例。
发明内容
本发明公开了一种沟槽金属-氧化物-半导体场效应晶体管(MOSFET)器件，包括：a)一个第一导电类型的衬底，衬底包括第一导电类型的半导体外延层位于相同导电类型的重掺杂半导体晶圆上方；b)一个第二导电类型的本体区，第二导电类型与第一导电类型相反，本体区形成在衬底上方；c)一个栅极沟槽，形成在本体区和衬底中，其中栅极沟槽内衬电介质层，栅极电极形成在栅极沟槽中；d)一个轻掺杂源极区和一个重掺杂源极区，形成在本体区中，其中轻掺杂源极区延伸到本体区中比重掺杂源极区更深的地方；以及e)一个沟槽接头，形成在接触沟槽中，在本体区中延伸，其中第二导电类型的接触注入物形成在接触沟槽底部和接触沟槽的侧壁与轻掺杂源极区相接触的部分。
其中第一导电类型为p-型导电类型，第二导电类型为n-型导电类型。
其中镇流电阻器形成在重掺杂源极区和本体区之间的轻掺杂源极区处。
其中PN结形成在接触注入物和轻掺杂源极区之间的交接处。
其中接触沟槽位于两个相邻的栅极沟槽之间。
其中沟槽接头在接触沟槽的侧壁连接到本体区以及重掺杂源极区。
其中接触沟槽的宽度在0.2微米至1.5微米范围内。
其中，还包括一个表面接头，形成在重掺杂源极区上方的表面接触开口中。
其中接触沟槽的长度在0.5微米至5.0微米范围内，其中表面接触开口的宽度在0.2微米至1.5微米范围内。
本发明还一种沟槽MOSFET器件的制备方法，该方法包括：a)在衬底中制备一个本体区，其中衬底包括一个第一导电类型的外延半导体层，在相同导电类型的重掺杂半导体晶圆上方，其中本体区是第二导电类型，第二导电类型与第一导电类型相反；b)在栅极沟槽中制备一个栅极电极，其中栅极沟槽形成在本体区和衬底中，并且内衬一个电介质层；c)在本体区中制备一个轻掺杂的源极区和一个重掺杂的源极区，其中轻掺杂的源极区延伸到比重掺杂的源极区更深的本体区中；d)在接触沟槽中制备一个沟槽接头，延伸到本体区，并且制备一个第二导电类型的接触注入物，包围着接触沟槽的底部以及接触沟槽接触轻掺杂源极区的侧壁部分。
其中第一导电类型为p-型导电类型，第二导电类型为n-型导电类型。
其中由源极注入物形成的轻掺杂源极区和重掺杂源极区包括一个深源极注入物和一个浅源极注入物，其中用于深源极注入物和浅源极注入物的掺杂离子的导电类型，与衬底的导电类型相同。
其中接触注入物是利用很大的倾斜角4旋转注入而形成的。
其中所形成的接触沟槽延伸到两个相邻的栅极沟槽之间的本体区，并且其中沟槽接头在接触沟槽的侧壁接触到本体区以及重掺杂源极区。
其中，还包括利用第一掩膜制备一个表面接头，在重掺杂源极区上方的表面接触开口中，其中表面接头接触重掺杂源极区。
附图说明
附图的简要说明
阅读以下详细说明并参照附图之后，本发明的各个方面及优势将显而易见：
图1A表示并联的MOSFET的示意图。
图1B表示具有源极镇流电阻器与每个MOSFET串联的并联MOSFET的示意图。
图2表示带有源极镇流的一部分n-通道沟槽MOSFET器件的剖面示意图。
图3表示在z方向上，带有表面本体接头的源极镇流沟槽MOSFET器件的三维图。
图4表示依据本发明的各个方面，一部分沟槽MOSFET器件的剖面示意图。
图5A表示依据本发明的各个方面，一种沟槽MOSFET器件的三维图。
图5B表示图5A所示的一部分沟槽MOSFET器件的剖面示意图。
图6A-6H表示依据本发明的各个方面，用于图4所示的沟槽MOSFET器件制备方法的剖面示意图。
图7A-7H表示依据本发明的各个方面，用于图5A-5B所示的沟槽MOSFET器件的制备方法的剖面示意图。
图7E’和7F’表示对应图7E和7F所示的剖面示意图的三维图。
具体实施方式
在以下说明中，参照附图，该附图形成了本发明的一部分，并且在其中表示出了可以实施本发明的图示特定实施例的方式。为方便起见，在特定的导电或净杂质载流子类型(p或n)之后使用+或-，通常指的是半导体材料中指定类型的净杂质载流子的相对浓度。一般而言，n+材料具有比n材料更高的n型净掺杂物(例如，电子)浓度，并且n材料具有比n材料更高的载流子浓度。与之类似，p+材料具有比p材料更高的p型净掺杂物(例如空穴)浓度，并且p材料具有比p材料更高的浓度。要注意的是，相关的是载流子的净浓度，而不一定是掺杂物。例如，材料可以重掺杂n-型掺杂物，但是如果材料也充分反向掺杂p-型掺杂物，那么仍然具有相对低的净载流子浓度。此处所用的掺杂物浓度小于1016/cm3可以认为是“轻掺杂”，掺杂物浓度大于1017/cm3可以认为是“重掺杂”。
在以下详细说明中，栅极沟槽的深度方向是指y方向，因此栅极沟槽的深度方向的平面是x-y平面；并且器件的通道宽度方向是指z方向，因此通道宽度方向的平面是指y-z平面。
引言
Worley提出的美国专利号6,927,458的专利中，提出了镇流电阻器与MOSFET串联的设计，特此引用其全文以作参考，说明利用镇流结构用于CMOS设计中的源极和漏极区。Hsieh提出的美国专利号7,816,720和Hebert等人提出的美国专利号8.703,563特此引用其全文以作参考，都提到了利用源极镇流电阻器控制电路的增益，当沟槽MOSFET并联时，能给出更好的一致性。由于这些设计具有源极镇流电阻器与重掺杂的源极区水平串联在MOSFET中，因此这些设计中的源极镇流电阻器会占据很大的面积。另外，当需要改变电阻时，必须有一种新的布局/设计。
2017年4月26日存档的Lui等人提出的美国专利申请号15/498,289，提出了一种带有接触源极镇流结构的沟槽MOSFET器件的改良结构，特此引用其全文以作参考。图2复制的是美国专利申请号15/498,289中的图2A。确切地说，沟槽MOSFET器件200包括一个轻掺杂的源极区240，构成镇流结构，在重掺杂的源极区250和本体区230之间。通过改变重掺杂源极区的深度以及改变轻掺杂源极区的掺杂浓度，可以轻松调节沟槽MOSFET 200中的镇流电阻。电阻器宽度也可以通过改变接触宽度来调节，例如从上面看接触沟槽的宽度。当沟槽MOSFET器件200是一个n-通道器件时，肖特基二极管形成在轻掺杂源极区240和源极接头272之间的接头处。由于肖特基接头形成在轻掺杂源极区和源极本体短路之间，所以通道电子电流流经轻掺杂源极区，在流至源极接头272之前，流至重掺杂源极区，平行于沟槽的方向。
然而，当沟槽MOSFET器件200是一个p-通道器件时，没有肖特基二极管形成在轻掺杂源极区240和短路本体源极的源极接头272之间的接头处。与之相反，轻掺杂源极区240构成一个到源极接头272的欧姆接触。因此，通道空穴电流水平流至轻掺杂源极区240中的源极接头272，使得镇流效果不稳定。这个问题可以通过在z方向上(也就是器件的通道宽度方向上)制备一个表面本体接头290来解决，如图3所示。然而，这会减小器件的通道宽度，从而影响器件的尺寸。
本发明的各个方面提出了一种带有源极镇流结构的沟槽MOSFET器件的改良结构。确切地说，依据本发明的各个方面，该沟槽MOSFET器件包括一个第一导电类型的轻掺杂的源极区，在第一导电类型的重掺杂源极区和第二导电类型的本体区之间构成一个镇流结构。该器件还包括一个到本体区的侧壁沟槽接头，以及一个形成在沟槽接头侧壁上的PN二极管，在沟槽接头侧壁上，与轻掺杂的源极区相接触。
在本发明的一个方面中，沟槽MOSFET器件具有一个到本体区的侧壁沟槽接头，以及一个在x-y平面内的重掺杂源极区。在本发明的另一方面中，沟槽MOSFET器件具有一个到重掺杂源极区的表面接头，在x-y平面内，以及一个到本体区的侧壁沟槽接头，在z方向上(即y-z平面内)，也就是与栅极沟槽的深度方向正交。与图3所示的源极-镇流器件不同，依据本发明的各个方面，所提出的器件具有通道宽度的最小损耗，从而对器件的尺寸产生最小的影响。
在以下示例中，MOSFET器件是指一个p-通道沟槽MOSFET器件，其中器件晶胞的源极区和漏极区都具有p型导电类型，本体区具有n型导电类型。要注意的是，这些导电类型可以互换，以获得一种n-通道沟槽MOSFET。
实施例1
图4表示依据本发明的各个方面，一部分沟槽MOSFET器件的剖面示意图。如同所示的其他附图一样，元件的相对维度和尺寸不会影响实际的维度，仅用于解释说明。
沟槽MOSFET器件400从衬底410开始。衬底410包括一个第一导电类型的外延层，在相同导电类型的重掺杂的硅晶圆上方。作为示例，但不作为局限，外延层和硅晶圆可以用任意合适的p-型掺杂物(离子或原子)掺杂。与用于外延层的掺杂相比，硅晶圆可以是重掺杂的。衬底410用作沟槽MOSFET器件400的漏极。
第二导电类型的本体区430形成在衬底410上方。第二导电类型与第一导电类型相反。对于p-通道器件类似，第一导电类型为p-型，第二导电类型为n-型。本体区430可以用任意合适的n-型掺杂物掺杂，例如磷或砷。
栅极沟槽420形成在本体区430中，并且延伸到衬底410的顶部。栅极沟槽内衬电介质材料422，例如氧化硅。栅极电极424形成在栅极沟槽420中，并通过电介质材料与本体区430和衬底410绝缘，电介质材料422内衬栅极沟槽420。作为示例，但不作为局限，栅极电极424可以由多晶硅或其他任意导电材料制成。
轻掺杂的源极区440形成在本体区430的顶部，如图4所示。源极区440可以轻掺杂与衬底410相同导电类型的掺杂物。作为示例，但不作为局限，轻掺杂源极区440的掺杂浓度可以从5×1015/cm3至1×1018/cm3范围内变化。
重掺杂源极区450形成在轻掺杂的源极区440上方。源极区450可以重掺杂与衬底410相同导电类型的掺杂物。作为示例，但不作为局限，对于p型衬底410来说，这些源极区450可以用p+型掺杂。作为示例，但不作为局限，重掺杂源极区450的掺杂浓度可以从8×1019/cm3至1×1020/cm3范围内变化。在图4所示的配置中，重掺杂源极区450扩展到栅极沟槽420和接触沟槽470之间的区域宽度上。
电介质层460形成在重掺杂源极区450上方。具有源极接头472的接触沟槽470位于两个相邻的栅极沟槽420之间。源极金属垫480位于电介质层460和源极接头472上方。源极接头472将源极金属垫480连接到本体区430。源极金属垫480和源极接头472用作源极垫，提供到沟槽MOSFET器件400的源极区450的外部接头。
第二导电类型的重掺杂源极注入物445，形成在接触沟槽470及其侧壁的底部，在侧壁上，它与轻掺杂源极区440相接触。作为示例，但不作为局限，重掺杂的接触注入物可以通过反向掺杂轻掺杂源极区440构成。源极注入物445可以用任意合适的n-型掺杂物掺杂，例如磷或砷。作为示例，但不作为局限，重掺杂接触注入物445的掺杂浓度从5×1018/cm3至5×1019/cm3范围内变化，这对于反向掺杂重掺杂的源极区450来说并不足够。因此，在接触构成470的侧壁上形成一个PN二极管，在侧壁上，它与轻掺杂的源极区440相接触。随着PN二极管形成在轻掺杂源极区440和接触注入物445之间的交界面处，通道空穴电流被阻止水平流入轻掺杂源极区440中的源极接头472。换言之，通道空穴电流流经轻掺杂源极区440，在流至源极接头472之前，流至重掺杂源极区450，平行于沟槽方向。
如图4所示，沟槽MOSFET器件400具有一个侧壁沟槽，接触到本体区430上，以及一个侧壁沟槽，在x-y平面内接触到重掺杂源极区450上。依据上述结构，镇流结构形成在重掺杂的源极区450和本体区430之间的轻掺杂源极区440上。另外，PN二极管形成在轻掺杂源极区440和源极接头472之间的接头处，一个欧姆接头形成在重掺杂源极区450和源极接头472之间的接头处。随着PN二极管形成在轻掺杂源极区440和接触注入物445之间的交界面处，通道空穴电流被阻止水平流至轻掺杂源极区440中的源极接头472。换言之，通道空穴电流流经轻掺杂源极区440，在流至源极接头472之前，流至重掺杂源极区450，平行于沟槽的方向。依据本发明的各个方面，可以轻松调节沟槽MOSFET中的镇流电阻。确切地说，电阻器长度可以通过重掺杂源极区的深度来调节。电阻器宽度可以通过改变接头宽度来调节。另外，电阻可以通过改变轻掺杂源极区的掺杂浓度来调节。
当器件具有较小的间距时，相邻的栅极沟槽420和接触沟槽470之间的距离可以忽略。利用接触注入物445，通道和接触注入物之间的距离变得非常窄，从而影响器件的阈值电压。本发明的另一方面如图5A和5B所示，提供了一个沟槽MOSFET器件，具有到重掺杂源极区的表面接头，在x-y平面内，到本体区的侧壁沟槽接头在z方向上(即图5A中切线A-A’所示的y-z平面)，也就是说与栅极沟槽的深度方向正交。
实施例2
图5A表示依据本发明的各个方面，一种沟槽MOSFET器件的三维图。图5B表示图5A所示的一部分沟槽MOSFET器件的剖面示意图，包括x-y平面内的剖面图，以及沿图5A的A-A’线在y-z平面内的剖面图。图5A或5B所示的沟槽MOSFET器件在x-y平面内具有一个到重掺杂源极区550的表面接头，以及一个在y-z平面内到本体区530的侧壁沟槽接头。通道宽度方向与栅极沟槽的深度方向正交。
确切地说，一个第二导电类型的重掺杂接触注入物545形成在本体接触沟槽570b的底部，在其侧壁上与y-z平面内第一导电类型的轻掺杂源极区540相接触。作为示例，但不作为局限，重掺杂接触注入物可以通过反向掺杂轻掺杂源极区540构成。接触注入物545kyi用任意合适的n-型掺杂物类型掺杂，例如磷或砷。作为示例，但不作为局限，重掺杂接触注入物545的掺杂浓度在5×1018/cm3至1×1019/cm3范围内变化，这对于反向掺杂重掺杂源极区550并不足够。另外，源极接触开口570a形成在重掺杂源极区550上方，穿过电介质层560，并用导电材料填充，以便形成从上方的金属层580到x-y平面内的重掺杂源极区550的表面接头。也就是说，每个重掺杂源极区550和轻掺杂源极区540都在两个相邻的栅极沟槽520之间的区域宽度上延伸。除了源极接触开口570a、本体接触沟槽570b和形成在y-z平面内的接触注入物545之外，图5A和5B所示的MOSFET器件具有衬底510，包括一个第一导电类型的外延层在相同导电类型的重掺杂硅晶圆上方、一个第二导电类型的本体区530形成在衬底510上方、一个在栅极沟槽520中的栅极电极524形成在本体区530中、一个第一导电类型的轻掺杂源极区540形成在本体区530顶部以及一个第一导电类型的重掺杂源极区540形成在轻掺杂源极区540上方。由于图5A和5B所示的MOSFET器件500的结构与图4所示的MOSFET器件400的结构类似，因此，为了简便，这两种结构的共同特点在此不再赘述。
实施例1的制备工艺
图6A-6H表示用于制备图4所示的沟槽MOSFET 400的制备工艺剖面图，沟槽MOSFET器件400具有一个到本体区430的沟槽接头，以及一个到x-y平面内重掺杂源极区450的侧壁接头。
图6A表示进行本体扩散工艺之后器件的剖面图。确切地说，该工艺使用第一导电类型的半导体衬底610作为起始材料。对于p-通道器件来说，衬底610包括一个p-型外延层在重掺杂的p型(p+)硅晶圆上方。在衬底610上使用掩膜(图中没有表示出)，包括限定栅极沟槽多个位置的开口，用于MOSFET器件400的沟槽晶体管。进行刻蚀工艺，刻蚀掉相应的下方衬底610的那部分，以制备多个栅极沟槽620。一旦沟槽620形成并且除去掩膜之后，就可以生长一个牺牲氧化层(图中没有表示出)然后除去，以改善沟槽中的硅表面。沿栅极沟槽620的内表面制备一个绝缘层(例如栅极氧化物)622。然后在栅极氧化层622上方沉积导电材料。在某些实施例中，导电材料可以是原位掺杂的或未掺杂的多晶硅。在衬底610上方的导电材料上进行回刻工艺之后，如图6A所示，就可以为每个沟槽晶体管制备一个栅极电极624。进行本体注入，形成本体区630。掺杂离子的导电类型与衬底610的掺杂相反。对于p-通道器件来说，掺杂离子可以是磷或砷离子。对于n-通道器件来说，可以使用硼离子。此后，进行热扩散，激活掺杂原子，扩散掺杂物，制备本体区630，如图6A所示。
参见图6B，利用源极掩膜(图中没有表示出)进行源极注入。确切地说，源极注入可以是深硼(p-)注入和浅硼(p-)注入。然后通过源极区扩散，在本体区630中制备一个轻掺杂的源极区640，比重掺杂源极区650更深，如图6C所示。作为示例，但不作为局限，轻掺杂源极区640的掺杂浓度在5×1015/cm3至1×1018/cm3范围内变化。作为示例，但不作为局限，轻掺杂源极区640可以在本体区630和重掺杂源极区650之间延伸。本体区630的深度D可以在0.5T至0.8T之间，其中T为栅极沟槽620的深度。轻掺杂区640的深度可以在0.4D至0.5D之间。重掺杂源极区650的深度可以在0.1D至0.25D之间。不同区域的深度可以通过控制注入能量来控制，注入能量通常在10keV至500keV范围内。
然后，在衬底610上方沉积一个平整的电介质层660，如图6D所示。在某些实施例中，电介质层660的制备是通过低温氧化物沉积，然后沉积含有硼酸的硅玻璃(BPSG)来制成的。
然后，在电介质层660上使用光致抗蚀剂605，其图案在接触沟槽的位置上有开口。利用刻蚀工艺，除去未被覆盖的那部分电介质层660，形成接触沟槽670，穿过源极区(640和650)到本体区630中，如图6E所示。作为示例，但不作为局限，接触沟槽670的宽度在0.2微米至1.5微米范围内。
除去光致抗蚀剂605之后，利用注入工艺，制备接触注入物645，如图6F所示。作为示例，但不作为局限，接触注入物645可以在40-80KeV的能级下，利用很大的倾斜角4旋转注入形成。对于p-通道器件来说，掺杂离子可以是磷或砷离子。对于n-通道器件来说，可以使用硼离子。作为示例，但不作为局限，接触注入物645的掺杂浓度在5×1018/cm3至5×1019/cm3范围内变化，这对于反向掺杂重掺杂源极区650来说并不足够。因此，形成在接触沟槽670侧壁上的PN结，与轻掺杂源极区640相接触。
势垒金属可以沉积在接触沟槽670的表面上方。作为示例，但不作为局限，势垒金属可以是钛(Ti)，通过物理气相沉积(PVD)沉积Ti/TiN，或者也可以是一种合金，例如通过CVD或PVD沉积的TiN。沉积势垒金属之后，导电材料(钨)可以通过CVD或PVD沉积在接触沟槽670中，以形成源极接头672，如图6G所示。
然后，在电介质层660上方沉积一个金属层680，如图6H所示。金属层680可以由铝等导电材料制成。金属层680和源极接头672互联所有的源极区，形成沟槽MOSFET器件400。
用于实施例2的制备工艺
图7A-7H表示图5A-5B所示的沟槽MOSFET器件500的制备工艺的剖面图，沟槽MOSFET器件500具有一个源极接头到x-y平面内的重掺杂源极区，以及侧壁沟槽接头到y-z平面内的本体区。
图7A表示进行本体扩散工艺后，沿图5所示的A-A’剖面，x-y平面内器件的剖面图以及y-z平面内器件的剖面图。确切地说，该工艺使用第一导电类型的半导体衬底710作为初始材料。对于p-通道器件来说，衬底710可以包括一个p-型外延层，在重掺杂p型(p+)硅晶圆上方。在衬底710上使用一个掩膜(图中没有表示出)包括限定多个栅极沟槽位置的开口，用于MOSFET器件700的沟槽晶体管。利用刻蚀工艺，刻蚀掉下方衬底710的相应部分，以形成多个栅极沟槽720。一旦形成沟槽720并且除去掩膜之后，可以生长一个牺牲氧化层(图中没有表示出)并除去，以改良沟槽中的硅表面。然后，沿栅极沟槽720的内表面形成一个绝缘层(例如栅极氧化物)722。在栅极氧化层722上方沉积导电材料。在某些实施例中，导电材料可以是原位掺杂的或者未掺杂的多晶硅。因此，在衬底710上方进行导电材料的回刻工艺之后，如图7A所示，就为每个沟槽晶体管形成一个栅极电极724。进行本体注入，形成本体区730。掺杂离子的导电类型与衬底710的掺杂导电类型相反。对于p-通道器件来说，掺杂离子可以是磷或砷离子。对于n-通道器件来说，可以使用硼离子。此后，进行热扩散，激活掺杂原子，扩散掺杂物，形成本体区730，如图7A所示。
参见图7B，利用源极掩膜(图中没有表示出)进行源极注入。确切地说，源极注入是深硼(p-)注入和浅硼(p+)注入的组合。随后通过源极区扩散，在本体区730中比重掺杂源极区750更深的地方形成一个轻掺杂的源极区740，如图7C所示。作为示例，但不作为局限，轻掺杂源极区740的掺杂浓度在5×1018/cm3至1×1018/cm3范围内变化，而重掺杂源极区750的掺杂浓度在8×1019/cm3至1×1020/cm3范围内变化。作为示例，但不作为局限，轻掺杂源极区740可以在本体区730和重掺杂源极区750之间延伸。本体区730的深度D可以在0.5T至0.8T之间，其中T是栅极沟槽720的深度。轻掺杂区740的深度在0.4D至0.5D之间。重掺杂源极区750的深度可以在0.1D至0.25D之间。各个区域的深度可以通过注入能量来扩展，注入能量的范围在10keV至500keV之间。
此后，在衬底710上方沉积一个平整的电介质层760，如图7D所示。在某些实施例中，电介质层760可以通过低温氧化物沉积来形成，然后沉积含有硼酸的硅玻璃(BPSG)。
然后在电介质层760上使用光致抗蚀剂705，其图案在源极接触开口的位置上有一个开口。利用刻蚀工艺，除去电介质层760未被覆盖的部分，并在重掺杂源极区750上方形成源极接触开口770a，如图7E所示。图7E’表示除去剩余的光致抗蚀剂705之后，图7E的三维图。作为示例，但不作为局限，源极接触开口770a的宽度在0.2微米至1.5微米之间。
在电介质层760上使用另一个光致抗蚀剂715，裸露的重掺杂源极区750的图案在y-z平面内本体接触沟槽的位置上有一个开口。利用刻蚀工艺，除去裸露的硅，并形成本体接触沟槽770b，穿过源极区(740和750)，进入本体区730，如图7F所示。图7F’表示通过源极区(740和750)到本体区730中刻蚀之前，图7F的三维图。作为示例，但不作为局限，本体接触沟槽770b的长度在0.5微米至5.0微米范围内。如图7E、7E’、7F和7F’所示，源极表面接触开口770a与本体接触沟槽770b正交。
除去光致抗蚀剂715之后，利用注入工艺，制备接触注入物745，如图7G所示。作为示例，但不作为局限，接触注入物745可以利用很大的倾斜角4，在40-80keV的能级下旋转注入。在某些实施例中，对于p-通道器件来说，掺杂离子可以是磷或砷离子。在某些实施例中，对于n-通道器件来说，可以使用硼离子。作为示例，但不作为局限，接触注入物745的掺杂浓度在5×1018/cm3至5×1019/cm3范围内变化，这对于反向掺杂重掺杂源极区750来说并不足够。因此，要在本体接触沟槽770b的侧壁上制备一个PN结，在侧壁上，PN结在通道宽度方向的平面内与轻掺杂源极区740相接触。
如图7H所示，制备一个源极接头、一个本体接头和一个金属层。确切地说，源极接头772a形成在每个源极接触开口770a中，用导电材料填充接触开口。本体接头772b形成在每个本体接触沟槽770b中，用导电材料填充接触开口。金属层780沉积在电介质层760上方。金属层780可以由铝等导电材料制成。金属层780、源极接头772a和本体接头772b互联所有的源极区，以形成沟槽MOSFET器件700。
尽管本发明关于某些较佳的版本已经做了详细的叙述，但是仍可能存在各种不同的修正、变化和等效情况。因此，本发明的范围不应由上述说明决定，与之相反，本发明的范围应参照所附的权利要求书及其全部等效内容。任何可选件(无论首选与否)，都可与其他任何可选件(无论首选与否)组合。在以下权利要求中，除非特别声明，否则不定冠词“一个”或“一种”都指下文内容中的一个或多个项目的数量。除非用“意思是”明确指出限定功能，否则所附的权利要求书并不应认为是意义-加-功能的局限。没有明确指出“意思是”执行特定功能的权利要求书中的任意内容，都不应认为是35 USC§112,
Figure BDA0001949090490000091
中所述的“意思”或“步骤”。

Claims (13)

1.一种沟槽金属-氧化物-半导体场效应晶体管(MOSFET)器件，包括：
a)一个第一导电类型的衬底，衬底包括第一导电类型的半导体外延层位于相同导电类型的重掺杂半导体晶圆上方；
b)一个第二导电类型的本体区，第二导电类型与第一导电类型相反，本体区形成在衬底上方；
c)一个栅极沟槽，形成在本体区和衬底中，其中栅极沟槽内衬电介质层，栅极电极形成在栅极沟槽中；
d)一个轻掺杂源极区和一个重掺杂源极区，形成在本体区中，其中轻掺杂源极区延伸到本体区中比重掺杂源极区更深的地方；以及
e)一个沟槽接头，形成在接触沟槽中，在本体区中延伸，其中第二导电类型的接触注入物形成在接触沟槽底部和接触沟槽的侧壁与轻掺杂源极区相接触的部分；
其中镇流电阻器形成在重掺杂源极区和本体区之间的轻掺杂源极区处。
2.权利要求1所述的器件，其中第一导电类型为p-型导电类型，第二导电类型为n-型导电类型。
3.权利要求1所述的器件，其中PN结形成在接触注入物和轻掺杂源极区之间的交接处。
4.权利要求1所述的器件，其中接触沟槽位于两个相邻的栅极沟槽之间。
5.一种沟槽金属-氧化物-半导体场效应晶体管(MOSFET)器件，包括：
a)一个第一导电类型的衬底，衬底包括第一导电类型的半导体外延层位于相同导电类型的重掺杂半导体晶圆上方；
b)一个第二导电类型的本体区，第二导电类型与第一导电类型相反，本体区形成在衬底上方；
c)一个栅极沟槽，形成在本体区和衬底中，其中栅极沟槽内衬电介质层，栅极电极形成在栅极沟槽中；
d)一个轻掺杂源极区和一个重掺杂源极区，形成在本体区中，其中轻掺杂源极区延伸到本体区中比重掺杂源极区更深的地方；以及
e)一个沟槽接头，形成在接触沟槽中，在本体区中延伸，其中第二导电类型的接触注入物形成在接触沟槽底部和接触沟槽的侧壁与轻掺杂源极区相接触的部分；
其中接触沟槽位于两个相邻的栅极沟槽之间；其中沟槽接头在接触沟槽的侧壁连接到本体区以及重掺杂源极区。
6.权利要求5所述的器件，其中接触沟槽的宽度在0.2微米至1.5微米范围内。
7.权利要求6所述的器件，还包括一个表面接头，形成在重掺杂源极区上方的表面接触开口中。
8.权利要求7所述的器件，其中接触沟槽的长度在0.5微米至5.0微米范围内，其中表面接触开口的宽度在0.2微米至1.5微米范围内。
9.一种沟槽MOSFET器件的制备方法，该方法包括：
a)在衬底中制备一个本体区，其中衬底包括一个第一导电类型的外延半导体层，在相同导电类型的重掺杂半导体晶圆上方，其中本体区是第二导电类型，第二导电类型与第一导电类型相反；
b)在栅极沟槽中制备一个栅极电极，其中栅极沟槽形成在本体区和衬底中，并且内衬一个电介质层；
c)在本体区中制备一个轻掺杂的源极区和一个重掺杂的源极区，其中轻掺杂的源极区延伸到比重掺杂的源极区更深的本体区中；
d)在接触沟槽中制备一个沟槽接头，延伸到本体区，并且制备一个第二导电类型的接触注入物，包围着接触沟槽的底部以及接触沟槽接触轻掺杂源极区的侧壁部分；
其中所形成的接触沟槽延伸到两个相邻的栅极沟槽之间的本体区，并且其中沟槽接头在接触沟槽的侧壁接触到本体区以及重掺杂源极区。
10.权利要求9所述的方法，其中第一导电类型为p-型导电类型，第二导电类型为n-型导电类型。
11.权利要求9所述的方法，其中由源极注入物形成的轻掺杂源极区和重掺杂源极区包括一个深源极注入物和一个浅源极注入物，其中用于深源极注入物和浅源极注入物的掺杂离子的导电类型，与衬底的导电类型相同。
12.权利要求9所述的方法，其中接触注入物是利用倾斜角旋转注入而形成的。
13.一种沟槽MOSFET器件的制备方法，该方法包括：
a)在衬底中制备一个本体区，其中衬底包括一个第一导电类型的外延半导体层，在相同导电类型的重掺杂半导体晶圆上方，其中本体区是第二导电类型，第二导电类型与第一导电类型相反；
b)在栅极沟槽中制备一个栅极电极，其中栅极沟槽形成在本体区和衬底中，并且内衬一个电介质层；
c)在本体区中制备一个轻掺杂的源极区和一个重掺杂的源极区，其中轻掺杂的源极区延伸到比重掺杂的源极区更深的本体区中；
d)在接触沟槽中制备一个沟槽接头，延伸到本体区，并且制备一个第二导电类型的接触注入物，包围着接触沟槽的底部以及接触沟槽接触轻掺杂源极区的侧壁部分；
还包括利用第一掩膜制备一个表面接头，在重掺杂源极区上方的表面接触开口中，其中表面接头接触重掺杂源极区。
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