CN110112119A - 位线的制作方法 - Google Patents
位线的制作方法 Download PDFInfo
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- CN110112119A CN110112119A CN201810101479.6A CN201810101479A CN110112119A CN 110112119 A CN110112119 A CN 110112119A CN 201810101479 A CN201810101479 A CN 201810101479A CN 110112119 A CN110112119 A CN 110112119A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 62
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 56
- 239000010936 titanium Substances 0.000 claims abstract description 52
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 51
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 35
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 11
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 62
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 37
- 229910052710 silicon Inorganic materials 0.000 claims description 37
- 239000010703 silicon Substances 0.000 claims description 37
- 229910052757 nitrogen Inorganic materials 0.000 claims description 35
- 239000011261 inert gas Substances 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 239000013077 target material Substances 0.000 claims description 14
- 239000003990 capacitor Substances 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- -1 Nitrogen ion Chemical class 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 3
- 125000004433 nitrogen atom Chemical group N* 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
- 239000010410 layer Substances 0.000 description 143
- 238000000151 deposition Methods 0.000 description 9
- LCKIEQZJEYYRIY-UHFFFAOYSA-N Titanium ion Chemical compound [Ti+4] LCKIEQZJEYYRIY-UHFFFAOYSA-N 0.000 description 5
- 239000000203 mixture Substances 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- VGRFVJMYCCLWPQ-UHFFFAOYSA-N germanium Chemical compound [Ge].[Ge] VGRFVJMYCCLWPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002715 modification method Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
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- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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Abstract
本发明公开一种位线的制作方式,包含首先提供一基底,基底上覆盖有一非晶硅层,然后形成一氮化钛层覆盖并接触非晶硅层,之后形成一钛层覆盖氮化钛层,然后形成一导电层覆盖钛层,接着进行一加热制作工艺,将氮化钛层转化成一含氮硅化钛层并且将钛层转化为硅化钛层,然后再图案化导电层、硅化钛层、含氮硅化钛层和非晶硅层以形成一位线。
Description
技术领域
本发明涉及一种位线的制作方法,特别是涉及利用氮化钛阻挡钛原子扩散进入导电硅的方法。
背景技术
动态随机存取存储器(dynamic random access memory,DRAM)等电子存储装置一直以来都是用来保存数据的重要来源。现有的动态随机存取存储器通常是由电容与晶体管构成,其电容一般会根据其充电状态来暂时性地存储数据。
上述电容与晶体管结构一般被称为存储单元。存储单元会排列成存储器阵列形式。而这些存储单元会通过一字符线(word line)与一位线(bit line)来定址,其中一者定址该存储胞的行位(column),而另一者则定址该存储胞的列位(row)。
位线的制作方式包含形成多层的导电层相互堆叠,然而此多层的导电层却会在高温时发生金属原子扩散到另一导电层的现象,此扩散出去的金属原子在后续会造成位线的漏电问题。
发明内容
本发明的目的之一在于提供一种制作位线的改良方法,以解决上述现有技术的问题与缺点。
根据本发明的一优选实施例,一种用于动态随机处理存储器的位线,包含一导电硅层,一含氮硅化钛/硅化钛层接触导电硅层以及一导电层覆盖含氮硅化钛/硅化钛层。
根据本发明的另一优选实施例,一种半导体元件的制作方式,包含首先提供一基底,基底上覆盖有一非晶硅层,然后形成一氮化钛层覆盖并接触非晶硅层,之后形成一钛层覆盖氮化钛层,最后进行一加热制作工艺,将氮化钛层转化成一含氮硅化钛层。
根据本发明的另一优选实施例,一种位线的制作方法,包含首先提供一腔室,腔室内包含一钛靶材设置于腔室的上壁和一载台设置于腔室的底面,接着进行一预烧(burn-in)制作工艺,预烧制作工艺包含通入氮气以及惰性气体于腔室中,并且离子化氮气以及惰性气体以形成氮离子和惰性离子,使得氮离子和惰性离子撞击钛靶材,以在腔室的上壁和底面以及钛靶材上形成一第一氮化钛层,接续在预烧制作工艺后,将一基底,放入腔室的载台上,基底上覆有一导电硅层,之后在基底放入腔室后,进行一沉积制作工艺,沉积制作工艺包含通入惰性气体于腔室中,并且离子化惰性气体以形成惰性离子,然后惰性离子撞击第一氮化钛层以沉积一第二氮化钛层接触导电硅层,在形成第二氮化钛层后,惰性气体撞击钛靶材,以沉积一钛层覆盖第二氮化钛层,此时沉积制作工艺完成,接着形成一导电层覆盖钛层,最后进行一加热制作工艺,将第二氮化钛层和钛层与导电硅层反应,以形成一含氮硅化钛/硅化钛层。
附图说明
图1至图6为本发明的第一优选实施例所绘示的一种位线的制作方法的示意图;
图7是本发明的一种位线的制作方法的流程图;
图8为本发明的第二优选实施例所绘示的一种动态随机处理存储器的示意图。
主要元件符号说明
10 腔室 12 钛靶材
14 载台 16 第一氮化钛层
18 基底 20 导电硅层
22 第二氮化钛层 24 钛层
26 导电层 28 第三氮化钛层
30 金属硅化物层 32 金属层
34 保护层 36 含氮硅化钛/硅化钛层
38 位线 40 埋入式栅极
42 源极掺杂区 44 漏极掺杂区
46 埋入式晶体管 48 电容插塞
50 电容 100 动态随机处理存储器
具体实施方式
图1至图6为根据本发明的第一优选实施例所绘示的一种位线的制作方法,图7绘示的是本发明的一种位线的制作方法的流程图。如图1所示,首先提供一腔室10,腔室10内包含一钛靶材12设置于腔室10的上壁,一载台14设置于腔室10的底面,如图1和图8所示,进行一预烧(burn in)制作工艺,将氮气以及惰性气体(inert gas)通入腔室10中,并且离子化氮气以及惰性气体以形成氮离子和惰性离子,使得惰性离子撞击钛靶材12以形成钛离子,之后钛离子和氮离子结合以在腔室10的上壁、底面和一侧壁以及钛靶材12上形成一第一氮化钛层16,根据本发明的优选实施例,惰性气体较佳为氩气,惰性离子则为氩离子。此外,根据本发明的优选实施例,预烧制作工艺时氮气的流量介于80至120单位时间标准毫升数(standard-state cubiccentimeter per minute,sccm)之间,通入时间约为30秒。值得注意的是由于在预烧制作工艺时,腔室10中未放入任何基底,因此第一氮化钛层16也会沉积在载台14的表面。在另一实施例中,在预烧制作工艺时腔室10中可放入挡片(dummywafer),以避免第一氮化钛层16沉积在载台14的表面。
如图2所示,提供一基底18,然后在基底18上形成一导电硅层20直接接触基底10,导电硅层20较佳为非晶硅层,导电硅层20的厚度较佳介于270至330埃之间,本发明的基底18为一硅(Silicon)基底、一锗(Germanium)基底、一砷化镓(Gallium Arsenide)基底、一硅锗(Silicon Germanium)基底、一磷化铟(Indium Phosphide)基底、一氮化镓(GalliumNitride)基底、一碳化硅(Silicon Carbide)基底或是一硅覆绝缘(silicon oninsulator,SOI)基底。在基底18上形成一导电硅层20之前,基底18中可预先形成一些元件,例如埋入式字符线(buried word line)和隔离结构(isolation)等。如图3和图8所示,在进行预烧制作工艺之后,将基底18放入腔室10中的载台14上,基底18会覆盖住在载台14表面上的第一氮化钛层16,在基底18放入腔室10后,进行一沉积制作工艺,沉积制作工艺包含通入惰性气体于腔室10中,并且离子化惰性气体以形成惰性离子,但在沉积制作工艺时,并未于腔室10中通入氮气。
请同时参阅图1和图3,在沉积制作工艺时,惰性离子撞击靶材12与腔室10表面的第一氮化钛层16以形成钛离子和氮离子,接着钛离子和氮离子结合形成一第二氮化钛层22沉积并接触导电硅层20,在形成第二氮化钛层22的同时第一氮化钛层16也会逐渐被消耗,当第一氮化钛层16完全被消耗后,钛靶材12就会被曝露出来,然后惰性离子开始撞击钛靶材12将钛靶材离子化形成钛离子,之后钛离子形成一钛层24覆盖第二氮化钛层22,当钛层24沉积至一预定厚度后停止沉积制作工艺,钛层24的厚度较佳介于20至30埃之间。此外,值得注意的是第二氮化硅层22中的氮原子和钛原子的比值介于0.9至1.1之间,第二氮化硅层22的厚度和钛层24的厚度的比值小于三分之一,另外,在第二氮化硅层22的氮具有一第一氮浓度,第一氮浓度为梯度变化,第一氮浓度从靠近导电硅层20的方向朝向钛层24减少,也就是说较靠近钛层24的第二氮化硅层22中的第一氮浓度较低,而较靠近导电硅层20的第二氮化硅层22中的第一氮浓度较高。但最重要的是钛层24和导电硅层20之间,因为有第二氮化硅层22隔开,所以可以避免在后续形成加热制作工艺时,钛层24中的钛原子扩散进入导电硅层20。
如图4和图7所示,形成一导电层26覆盖钛层24,导电层26较佳包含一第三氮化钛层28、一金属硅化物层30和一金属层32由下至上堆叠,其中第三氮化钛层28可以继续在腔室10中制成,也就是说于腔室10中再度通入氮气和惰性气体,采用之前形成第二氮化钛层22的方式来形成第三氮化钛层28,之后再将基底18移出腔室10,接续形成金属硅化物层30和金属层32,金属硅化物层30较佳为硅化钨,而金属层32较佳为钨。
根据本发明的另一优选实施例,在完成钛层24后,可以将基底18移出腔室,放入另一腔室(图未示),在另一腔室中可利用物理气相沉积制作工艺或化学气相沉积制作工艺等方式形成第三氮化钛层28。若是第三氮化钛层28在和钛层24同一个腔室10制作时,后续下一片基底就不用进行预烧制作工艺,因为在形成第三氮化钛层28时已经在腔室10内壁和钛靶材12上形成了再度形成了氮化钛,因此下一片基底进入腔室10后就可以直接进行沉积制作工艺。
请继续参阅图4和图7,在完成导电层26之后,形成一保护层34覆盖导电层26,保护层34较佳为氮化硅。如图5和图7所示,进行一加热制作工艺,使得第二氮化钛层22与导电硅层20反应以将第二氮化钛层22转化成一含氮硅化钛层,并且也将钛层24与导电硅层20反应,并将钛层24转化为一硅化钛层,硅化钛层和含氮硅化钛层形成混合物,此混合物称为含氮硅化钛/硅化钛层36,也就是说含氮硅化钛层周边围绕着硅化钛层。含氮硅化钛/硅化钛层36中的含氮硅化钛层和硅化钛层是混合物,因此都接触导电硅层20,并且含氮硅化钛层和硅化钛层互相接触,此外,值得注意的是含氮硅化钛粒子具有一第二氮浓度,第二氮浓度为梯度变化,第二氮浓度朝向远离导电硅层20的方向减少,也就是说,靠近导电硅层20的含氮硅化钛层中的第二氮浓度较高,远离导电硅层20的含氮硅化钛层中的第二氮浓度较低。如图6和图7所示,图案化导电层20、含氮硅化钛/硅化钛层36、导电硅层20以形成一导电线,例如一位线38,本发明制作工艺所制作的位线较佳是用于一动态随机处理存储器。
图8为根据本发明的第二优选实施例所绘示的一种动态随机处理存储器的示意图,其中为了方便说明,与第一优选实施例相同元件使用相同符号标示,并且相同的部分将不重复赘述。如图8所示,基底18上设置有一埋入式栅极40,埋入式栅极40两侧分别设置有一源极掺杂区42和一漏极掺杂区44,埋入式栅极40、源极掺杂区42和漏极掺杂区44组成一埋入式晶体管46,位线38通过源极掺杂区42电连接埋入式晶体管46,漏极掺杂区44上电连接一电容插塞48,电容插塞48电连接一电容50,因此埋入式晶体管46电连接电容50,动态随机处理存储器100由晶体管46和电容50所组成。此外,本发明的位线38包含一导电硅层20、一含氮硅化钛/硅化钛层36接触导电硅层20以及一导电层26覆盖含氮硅化钛/硅化钛层36,值得注意的是含氮硅化钛/硅化钛层36是由一硅化钛层和一含氮硅化钛层所形成的混合物,导电层26包含一第三氮化硅层28、一金属硅化物层30和金属层32,在导电层26上覆盖有一保护层34。保护层34可以为氮化硅。
由于本发明在制作位线时特别在导电硅层和钛层之间额外增加一硅化钛层,如此一来钛层在加热制作工艺时就不会扩散到导电硅层中,若是钛层扩散到导电硅层中,后续图案化形成位线时,扩散到导电硅层中的钛层会被蚀刻掉,在导电硅层中留下多个孔洞,这些孔洞之后会造成漏电。因此本发明的位线的制作方法,可以避免位线发生漏电的问题。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。
Claims (17)
1.一种用于动态随机处理存储器的位线,其特征在于,包含:
导电硅层;
含氮硅化钛/硅化钛层,接触该导电硅层;
以及
导电层,覆盖该含氮硅化钛/硅化钛层。
2.如权利要求1所述的用于动态随机处理存储器的位线,另包含:
晶体管,电连接该位线;
电容插塞,电连接该晶体管;以及
电容,电连接该电容插塞。
3.如权利要求1所述的用于动态随机处理存储器的位线,其中该导电层包含:氮化钛层、金属硅化物层和金属层。
4.一种半导体元件的制作方式,其特征在于,包含:
提供一基底,该基底上覆盖有一非晶硅层;
形成一氮化钛层覆盖并接触该非晶硅层;
形成一钛层覆盖该氮化钛层;以及
进行一加热制作工艺,将该氮化钛层转化成一含氮硅化钛层。
5.如权利要求4所述的半导体元件的制作方式,其中在该加热制作工艺另包含将该钛层转化成一硅化钛层。
6.如权利要求5所述的半导体元件的制作方式,另包含形成一导电层覆盖该钛层。
7.如权利要求6所述的半导体元件的制作方式,另包含图案化该导电层、该硅化钛层、该含氮硅化钛层和该非晶硅层,以形成一导电线。
8.如权利要求7所述的半导体元件的制作方式,其中该导电线作为一动态随机处理存储器的一位线。
9.如权利要求4所述的半导体元件的制作方式,其中该氮化钛层具有一第一氮浓度,该第一氮浓度为梯度变化,该第一氮浓度从靠近该非晶硅层的方向朝向该钛层减少。
10.如权利要求4所述的半导体元件的制作方式,其中该含氮硅化钛层具有一第二氮浓度,该第二氮浓度为梯度变化,该第二氮浓度朝向远离该非晶硅层的方向减少。
11.一种位线的制作方法,其特征在于,包含:
提供一腔室,该腔室内包含:
钛靶材,设置于该腔室的上壁;
载台,设置于该腔室的底面;
进行一预烧(burn-in)制作工艺,该预烧制作工艺包含:
通入氮气以及惰性气体于该腔室中,并且离子化氮气以及惰性气体以形成氮离子和惰性离子,使得氮离子和惰性离子撞击该钛靶材,以在该腔室的该上壁和该底面以及该钛靶材上形成一第一氮化钛层;
在该预烧制作工艺后,将一基底,放入该腔室的该载台上,该基底上覆有一导电硅层;
在该基底放入该腔室后,进行一沉积制作工艺,该沉积制作工艺包含:
通入惰性气体于该腔室中,并且离子化该惰性气体以形成惰性离子;
惰性离子撞击该第一氮化钛层以沉积一第二氮化钛层接触该导电硅层;以及
在形成该第二氮化钛层后,该惰性气体撞击该钛靶材,以沉积一钛层覆盖该第二氮化钛层;
形成一导电层覆盖该钛层;以及
进行一加热制作工艺,将该第二氮化钛层和该钛层与该导电硅层反应,以形成一含氮硅化钛/硅化钛层。
12.如权利要求11所述的位线的制作方法,其中在该沉积制作工艺时,未在该腔室中通入氮气。
13.如权利要求11所述的位线的制作方法,其中在该预烧制作工艺时,该腔室中没有基底。
14.如权利要求11所述的位线的制作方法,其中该第二氮化硅层的厚度和该钛层的厚度的比值小于三分之一。
15.如权利要求11所述的位线的制作方法,其中该第二氮化硅中的氮原子和钛原子的比值介于0.9至1.1之间。
16.如权利要求11所述的位线的制作方法,其中在该预烧制作工艺时,该氮气的流量介于80至120单位时间标准毫升数(standard-state cubic centimeter per minute,sccm)之间,通入时间约为30秒。
17.如权利要求11所述的位线的制作方法,其中该导电层包含第三氮化钛层、金属硅化物层和金属层。
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