CN110048711A - A kind of digital signal processing circuit for resisting ground and power bounce noise - Google Patents
A kind of digital signal processing circuit for resisting ground and power bounce noise Download PDFInfo
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- CN110048711A CN110048711A CN201910400515.3A CN201910400515A CN110048711A CN 110048711 A CN110048711 A CN 110048711A CN 201910400515 A CN201910400515 A CN 201910400515A CN 110048711 A CN110048711 A CN 110048711A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
Abstract
A kind of digital signal processing circuit the present invention relates to resistance with power bounce noise, including the first current source, second current source, first PMOS tube, first NMOS tube, capacitor, second PMOS tube, second NMOS tube, third PMOS tube, 4th PMOS tube, 5th PMOS tube, third NMOS tube, 4th NMOS tube, 5th NMOS tube, phase inverter and voltage lock circuit, the input of phase inverter terminates signal input part, the first input end of the output termination voltage lock circuit of phase inverter, second input termination signal output end of voltage lock circuit, the output of voltage lock circuit terminates second voltage test point；Voltage lock circuit can lock the voltage of second voltage test point, to stably keep the logic level of signal output end output signal, this circuit can not only eliminate the channel transfer noise transmitted from signal input part, it is effective against the rebound noise of the positive and negative level pulse generated on ground wire and power supply line simultaneously, circuit cost is low, stable and reliable for performance.
Description
Technical field
The present invention relates to digital signal processing circuit technical field more particularly to one kind can with resisting and power bounce noise
Digital signal processing circuit.
Background technique
Currently, the transmission and processing of digital signal are represented by high level during Design of Digital Integrated Circuit
Come what is completed, the noise in circuit is likely to enter in the transmission process of signal, leads to number for " 0 " that " 1 " and low level represent
The error condition of signal, it is therefore desirable to increase support antimierophonic processing circuit in circuit.
As shown in Figure 1, commonly to support antimierophonic digital signal processing circuit, the signal waveform of each node of the circuit
As shown in Fig. 2, current source Id2 can slowly discharge to the capacitor of A point when input signal (IN) inputs a rising edge,
When the voltage of A point is lower than threshold voltage, the voltage of B point can just be overturn, and the signal of input signal IN to B point there is prolonging for t1
The slow time difference, as long as the time width of the positive pulse noise in signal transmission passage is less than t1, which can eliminate this
Noise.When input signal (IN) inputs a failing edge, current source Id1 can slowly charge to the capacitor of A point, when A point
Voltage be higher than threshold voltage when, the voltage of B point can just be overturn, when the signal of input signal IN to B point there is the delay of t2
Between it is poor, as long as the time width of the negative pulse noise in signal transmission passage is less than t2, which can eliminate the noise.
A point in the foregoing circuit process slowly varying there are voltage, to prevent PMOS tube P1 and NMOS tube N1 while leading
The case where perforation high current of the power supply to ground is generated when logical, P1 or N1(or N1 and P1) it can be designed to the metal-oxide-semiconductor of long channel,
I.e. its breadth length ratio W/L can be designed very small, and the size of channel length L can be designed very big.Utilize its biggish conducting
Resistance value come limit power supply when P1 and N1 is simultaneously turned on to ground perforation electric current size.
By taking N1 is designed to long channel as an example, when the rebound noise (Ground bounce) on ground wire is negative pulse, such as
Input signal IN is low level to fruit at this time, and the waveform diagram of each section is as shown in Figure 3 in circuit.Due to the conducting resistance of NMOS tube N1
Bigger, the voltage of B point cannot be with the negative arteries and veins noise quick response on (GND) everywhere in circuit, and B point is to can generate one between ground
The voltage difference of section delay time, NMOS tube N2 will have the turn on process of short time in difference this period, so circuit is defeated
A wrong low level signal output will occur in signal OUT out.Therefore existing noise canceller circuit is irresistibly on line
Negative pulse rebound noise.
Summary of the invention
The purpose of the present invention is to provide it is a kind of it is simple and reliable for structure being capable of positive and negative arteries and veins with being effective against and on power supply line
The digital signal processing circuit for resisting ground and power bounce noise of punching rebound noise.
To achieve the goals above, the technical solution adopted by the present invention is a kind of number for resisting ground and power bounce noise
Word signal processing circuit, including the first current source, the second current source, the first PMOS tube, the first NMOS tube, capacitor, the 2nd PMOS
Pipe, the second NMOS tube, third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS
Pipe, phase inverter and voltage lock circuit, the input terminal of the first current source connect power supply, the output end connection first of the first current source
The source electrode of PMOS tube, the first PMOS tube be connected with the grid of the first NMOS tube after as digital signal processing circuit signal input
End, the first PMOS tube are connected with the drain electrode of the first NMOS tube, and the source electrode of the first NMOS tube connects the input terminal of the second current source, the
The output end of two current sources is grounded, and one end of capacitor connects the drain electrode of the first NMOS tube, the other end ground connection of capacitor, the 2nd PMOS
The source electrode of pipe, third PMOS tube and the 4th PMOS tube is all connected with power supply, and the second PMOS tube is connected with the drain electrode of the second NMOS tube, the
Two PMOS tube connect one end of capacitor, the source electrode ground connection of the second NMOS tube, the 3rd PMOS after being connected with the grid of the second NMOS tube
Manage the signal output end after being connected with the drain electrode of third NMOS tube as digital signal processing circuit, third PMOS tube and third
The grid of NMOS tube connects the drain electrode of the second PMOS tube, the source electrode ground connection of third NMOS tube, the grid of the 4th PMOS tube after being connected
Connection signal input terminal, the source electrode of drain electrode the 5th PMOS tube of connection of the 4th PMOS tube, the 5th PMOS tube and the 4th NMOS tube
First voltage test point is drawn in the drain connections of the 5th PMOS tube and the 4th NMOS tube in one end of drain electrode connection capacitor, the
Five PMOS tube connect the drain electrode of the second NMOS tube with the grid of the 4th NMOS tube, in the grid of the 5th PMOS tube and the 4th NMOS tube
Second voltage test point is drawn in junction, and the source electrode of the 4th NMOS tube is connected with the drain electrode of the 5th NMOS tube, the 5th NMOS tube
Source electrode ground connection, the grid connection signal input terminal of the 5th NMOS tube, the input terminal connection signal input terminal of phase inverter, phase inverter
Output end connects the first input end of voltage lock circuit, the second input terminal connection signal output end of voltage lock circuit, electricity
The output end of lock-in circuit is pressed to connect second voltage test point；Voltage lock circuit can voltage to second voltage test point into
Row locking, to stably keep the logic level of signal output end output signal.
As an improvement of the present invention, the voltage lock circuit include the first metal-oxide-semiconductor and the second metal-oxide-semiconductor, first
The grid connection signal output end of metal-oxide-semiconductor, the drain electrode of the first metal-oxide-semiconductor connect second voltage test point, and the source electrode of the first metal-oxide-semiconductor connects
Connect the drain electrode of the second metal-oxide-semiconductor, the output end of the grid connection phase inverter of the second metal-oxide-semiconductor, the source electrode ground connection of the second metal-oxide-semiconductor.
As an improvement of the present invention, the phase inverter is realized using NOT gate, the input terminal connection signal input of NOT gate
End, the first input end of the output end connection voltage lock circuit of NOT gate.
As an improvement of the present invention, first metal-oxide-semiconductor and the second metal-oxide-semiconductor are all made of NMOS tube.
As an improvement of the present invention, the breadth length ratio W/L of first NMOS tube is designed as 0.01-0.1.
Compared with the existing technology, circuit overall construction design of the invention is ingenious, and simple and reasonable, cost of implementation is low,
Stable and reliable for performance, the circuit structure for the resistance rebound noise being composed by using phase inverter and voltage lock circuit is set
Meter, can resist the rebound noise generated on ground wire and power supply line well, and the noise that no matter rebounds is positive electricity flat pulse or bears
Level pulse signal, all-the-time stable reliably keep the logic level of signal output end output signal, to effectively increase number
The signal processing accuracy rate of word signal processing circuit.
Detailed description of the invention
Fig. 1 is existing to antimierophonic digital signal processing circuit figure.
Fig. 2 is the existing signal waveforms to each node of antimierophonic digital signal processing circuit.
Fig. 3 is respectively to save when generating negative pulse rebound noise on the existing ground wire to antimierophonic digital signal processing circuit
The signal waveforms of point.
Fig. 4 is the digital signal processing circuit figure for resisting ground and power bounce noise of the preferred embodiment of the present invention.
Fig. 5 is each node of digital signal processing circuit for resisting ground and power bounce noise of the preferred embodiment of the present invention
Signal waveforms.
Fig. 6 is on the ground wire for the digital signal processing circuit for resisting ground and power bounce noise of the preferred embodiment of the present invention
Generate the signal waveforms of each node when negative pulse rebound noise.
Specific embodiment
In order to deepen the understanding of the present invention and recognize, the invention will be further described below in conjunction with the accompanying drawings and introduces.
As shown in figure 4, a kind of resistance provided for the preferred embodiment of the present invention and power bounce noise digital signal
Processing circuit, including the first current source Id1, the second current source Id2, the first PMOS tube P0, the first NMOS tube N0, capacitor C1,
Two PMOS tube P1, the second NMOS tube N1, third PMOS tube P2, the 4th PMOS tube P3, the 5th PMOS tube P4, third NMOS tube N2,
The input terminal of 4th NMOS tube N3, the 5th NMOS tube N4, phase inverter and voltage lock circuit, the first current source Id1 connects power supply,
The output end of first current source Id1 connects the source electrode of the first PMOS tube P0, the grid of the first PMOS tube P0 and the first NMOS tube N0
Signal input part IN after being connected as digital signal processing circuit, the drain electrode phase of the first PMOS tube P0 and the first NMOS tube N0
Even, the source electrode of the first NMOS tube N0 connects the input terminal of the second current source Id2, the output end ground connection of the second current source Id2, capacitor
One end of C1 connects the drain electrode of the first NMOS tube N0, the other end ground connection of capacitor C1, the second PMOS tube P1, third PMOS tube P2 and
The source electrode of 4th PMOS tube P3 is all connected with power supply, and the drain electrode of the second PMOS tube P1 and the second NMOS tube N1 are connected, the second PMOS tube
The grid of P1 and the second NMOS tube N1 connect the input terminal of capacitor C1, the source electrode ground connection of the second NMOS tube N1, third after being connected
Signal output end OUT as digital signal processing circuit after PMOS tube P2 is connected with the drain electrode of third NMOS tube N2, third
PMOS tube P2 connects the drain electrode of the second PMOS tube P1 after being connected with the grid of third NMOS tube N2, the source electrode of third NMOS tube N2 connects
Ground, the source of the 5th PMOS tube P4 of drain electrode connection of grid connection signal the input terminal IN, the 4th PMOS tube P3 of the 4th PMOS tube P3
The input terminal of the drain electrode connection capacitor C1 of pole, the 5th PMOS tube P4 and the 4th NMOS tube N3, in the 5th PMOS tube P4 and the 4th
The drain connections of NMOS tube N3 draw the grid connection of first voltage test point A, the 5th PMOS tube P4 and the 4th NMOS tube N3
The drain electrode of second NMOS tube N1 draws second voltage test point in the grid junction of the 5th PMOS tube P4 and the 4th NMOS tube N3
The source electrode of B, the 4th NMOS tube N3 are connected with the drain electrode of the 5th NMOS tube N4, the source electrode ground connection of the 5th NMOS tube N4, the 5th NMOS
The grid connection signal input terminal IN of pipe N4, the input terminal connection signal input terminal IN of phase inverter, the output end connection of phase inverter
The first input end of voltage lock circuit, the second input terminal connection signal output end OUT of voltage lock circuit, voltage lockout electricity
The output end on road connects second voltage test point B；Voltage lock circuit can lock the voltage of second voltage test point B
It is fixed, to stably keep the logic level of signal output end OUT output signal.
Wherein, the phase inverter realizes the function of signal inversion using NOT gate INV1, and the input terminal of NOT gate INV1 connects letter
The first input end of the output end connection voltage lock circuit of number input terminal IN, NOT gate INV1.The voltage lock circuit is by
One metal-oxide-semiconductor N5 and the second metal-oxide-semiconductor N6 composition, the grid connection signal output end OUT of the first metal-oxide-semiconductor N5, the leakage of the first metal-oxide-semiconductor N5
Pole connects second voltage test point B, and the source electrode of the first metal-oxide-semiconductor N5 connects the drain electrode of the second metal-oxide-semiconductor N6, the grid of the second metal-oxide-semiconductor N6
Pole connects the output end of phase inverter, the source electrode ground connection of the second metal-oxide-semiconductor N6.
In addition, the first metal-oxide-semiconductor N5 and the second metal-oxide-semiconductor N6 are all made of NMOS tube.
In addition, the breadth length ratio W/L of the first NMOS tube is designed as 0.01-0.1, to prevent the second PMOS tube P1, second
Perforation high current of the generation power supply to ground when NMOS tube N1 is connected at the same time.The time span of delay time t1 and t2 are greater than logical
The pulse width of road transmitted noise, while the time span of delay time t1 and t2 are also less than signal input part IN input signal
Pulse width, the time span of delay time t1 and t2 can size by adjusting capacitor C1, the first current source Id1 and second
The size of current source Id2 is adjusted.
The signal waveform of each node is as shown in figure 5, when signal input part IN inputs one in the circuit of this preferred embodiment
When rising edge, the second current source Id2 can slowly discharge to the capacitor C1 at first voltage test point A, when first voltage is examined
When the voltage of measuring point A is lower than threshold voltage, the voltage of second voltage test point B can just be overturn, the electricity of signal input part IN to second
The signal of pressure test point B there is the delay-time difference of t1, as long as the time width of the positive pulse noise in signal transmission passage
Less than t1, then this circuit can eliminate the noise.When signal input part IN inputs a failing edge, the first current source Id1
It can slowly be charged to the capacitor C1 at first voltage test point A, when the voltage of first voltage test point A is higher than threshold voltage
When, the voltage of second voltage test point B can just be overturn, and the signal of signal input part IN to second voltage test point B there is t2
Delay-time difference, as long as the time width of the negative pulse noise in signal transmission passage is less than t2, this circuit can disappear
Except the noise.Make so this circuit still has the channel transfer noise transmitted from signal input part IN to eliminate well
With.
When in ground wire generate a negative electricity flat pulse rebound noise when, signal input part IN input signal be it is low
When level, signal output end OUT output signal is high level, so the first metal-oxide-semiconductor N5 and the second metal-oxide-semiconductor N6 keep it turning on shape
State, the voltage of second voltage test point B is locked into low level in circuit, when occurring negative pulse rebound noise on ground wire, the
The voltage of two voltage detecting point B can rapidly follow response.
As shown in fig. 6, this circuit can withstand ground rebound well when occurring negative pulse rebound noise on ground wire
The output signal of the influence of noise, signal output end OUT always remains as high level.
When the input signal of signal input part IN is high level, when the output signal of signal output end OUT is low level,
Because first voltage test point A is low level in circuit, the second PMOS tube P1 is opened, second voltage test point B in circuit
Voltage be locked in the high level of supply voltage, third NMOS tube N2 is kept it turned on, so signal output end OUT's is defeated
Signal will be the low level for following ground wire GND to fluctuate out.
Similarly, same mode can be used and analyze the positive and negative level pulse rebound noise generated on power supply line to this electricity
The influence of the logic level of road signal output end OUT output signal, by analyzing it is found that the circuit of this preferred embodiment can be very
The rebound noise generated on ground wire and power supply line is resisted well, and the noise that no matter rebounds is positive electricity flat pulse or negative electricity flat pulse letter
Number, the circuit structure for the resistance rebound noise being composed by phase inverter in this circuit and voltage lock circuit can to stablize
The logic level of signal output end OUT output signal is kept by ground.Circuit has the advantages of simple structure and easy realization, cost of implementation it is low and
Resist the stable and reliable for performance of the rebound noise generated on ground wire and power supply line.
The technical means disclosed in the embodiments of the present invention is not limited only to technological means disclosed in above embodiment, further includes
Technical solution consisting of any combination of the above technical features.It should be pointed out that for those skilled in the art
For, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also considered as
Protection scope of the present invention.
Claims (5)
1. a kind of digital signal processing circuit for resisting ground and power bounce noise, it is characterised in that: including the first current source, the
Two current sources, the first PMOS tube, the first NMOS tube, capacitor, the second PMOS tube, the second NMOS tube, third PMOS tube, the 4th PMOS
Pipe, the 5th PMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, phase inverter and voltage lock circuit, the first electric current
The input terminal in source connects power supply, and the output end of the first current source connects the source electrode of the first PMOS tube, the first PMOS tube and first
Signal input part after the grid of NMOS tube is connected as digital signal processing circuit, the leakage of the first PMOS tube and the first NMOS tube
Extremely it is connected, the source electrode of the first NMOS tube connects the input terminal of the second current source, and the output end of the second current source is grounded, and the one of capacitor
The drain electrode of the first NMOS tube of end connection, the other end ground connection of capacitor, the source of the second PMOS tube, third PMOS tube and the 4th PMOS tube
Pole is all connected with power supply, and the second PMOS tube is connected with the drain electrode of the second NMOS tube, the grid phase of the second PMOS tube and the second NMOS tube
One end of capacitor, the source electrode ground connection of the second NMOS tube are connected after even, third PMOS tube is made after being connected with the drain electrode of third NMOS tube
For the signal output end of digital signal processing circuit, third PMOS tube connects the 2nd PMOS after being connected with the grid of third NMOS tube
The drain electrode of pipe, the source electrode ground connection of third NMOS tube, the grid connection signal input terminal of the 4th PMOS tube, the drain electrode of the 4th PMOS tube
The source electrode of the 5th PMOS tube is connected, the drain electrode of the 5th PMOS tube and the 4th NMOS tube connects one end of capacitor, in the 5th PMOS tube
First voltage test point is drawn with the drain connections of the 4th NMOS tube, and the 5th PMOS tube connects the with the grid of the 4th NMOS tube
The drain electrode of two NMOS tubes, the grid junction of the 5th PMOS tube and the 4th NMOS tube draw second voltage test point, the 4th
The source electrode of NMOS tube is connected with the drain electrode of the 5th NMOS tube, the source electrode ground connection of the 5th NMOS tube, the grid connection of the 5th NMOS tube
Signal input part, the input terminal connection signal input terminal of phase inverter, the first of the output end connection voltage lock circuit of phase inverter
Input terminal, the second input terminal connection signal output end of voltage lock circuit, the second electricity of output end connection of voltage lock circuit
Press test point；Voltage lock circuit can lock the voltage of second voltage test point, to stably keep signal output
Hold the logic level of output signal.
2. a kind of digital signal processing circuit for resisting ground and power bounce noise as described in claim 1, which is characterized in that
The voltage lock circuit include the first metal-oxide-semiconductor and the second metal-oxide-semiconductor, the grid connection signal output end of the first metal-oxide-semiconductor, first
The drain electrode of metal-oxide-semiconductor connects second voltage test point, and the source electrode of the first metal-oxide-semiconductor connects the drain electrode of the second metal-oxide-semiconductor, the second metal-oxide-semiconductor
Grid connects the output end of phase inverter, the source electrode ground connection of the second metal-oxide-semiconductor.
3. a kind of digital signal processing circuit for resisting ground and power bounce noise as claimed in claim 1 or 2, feature exist
In the phase inverter is realized using NOT gate, the input terminal connection signal input terminal of NOT gate, and the output end of NOT gate connects voltage lockout
The first input end of circuit.
4. a kind of digital signal processing circuit for resisting ground and power bounce noise as claimed in claim 3, which is characterized in that
First metal-oxide-semiconductor and the second metal-oxide-semiconductor are all made of NMOS tube.
5. a kind of digital signal processing circuit for resisting ground and power bounce noise as claimed in claim 4, which is characterized in that
The breadth length ratio W/L of first NMOS tube is designed as 0.01-0.1.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910400515.3A CN110048711B (en) | 2019-05-15 | 2019-05-15 | Digital signal processing circuit for resisting ground and power supply rebound noise |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910400515.3A CN110048711B (en) | 2019-05-15 | 2019-05-15 | Digital signal processing circuit for resisting ground and power supply rebound noise |
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| CN110048711B CN110048711B (en) | 2023-11-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116346084A (en) * | 2023-03-14 | 2023-06-27 | 瑶芯微电子科技(上海)有限公司 | High-frequency noise suppression circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116346084A (en) * | 2023-03-14 | 2023-06-27 | 瑶芯微电子科技(上海)有限公司 | High-frequency noise suppression circuit |
| CN116346084B (en) * | 2023-03-14 | 2023-10-20 | 瑶芯微电子科技(上海)有限公司 | High-frequency noise suppression circuit |
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