CN110048711B - Digital signal processing circuit for resisting ground and power supply rebound noise - Google Patents
Digital signal processing circuit for resisting ground and power supply rebound noise Download PDFInfo
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- CN110048711B CN110048711B CN201910400515.3A CN201910400515A CN110048711B CN 110048711 B CN110048711 B CN 110048711B CN 201910400515 A CN201910400515 A CN 201910400515A CN 110048711 B CN110048711 B CN 110048711B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
Abstract
The invention relates to a digital signal processing circuit for resisting ground and power supply rebound noise, which comprises a first current source, a second current source, a first PMOS tube, a first NMOS tube, a capacitor, a second PMOS tube, a second NMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, an inverter and a voltage locking circuit, wherein the input end of the inverter is connected with a signal input end, the output end of the inverter is connected with a first input end of the voltage locking circuit, the second input end of the voltage locking circuit is connected with a signal output end, and the output end of the voltage locking circuit is connected with a second voltage detection point; the voltage locking circuit can lock the voltage of the second voltage detection point to stably maintain the logic level of the signal output by the signal output end, the circuit can not only eliminate channel transmission noise transmitted from the signal input end, but also effectively resist rebound noise of positive and negative level pulses generated on the ground wire and the power wire, and has low circuit cost and stable and reliable performance.
Description
Technical Field
The present invention relates to digital signal processing circuits, and more particularly, to a digital signal processing circuit capable of resisting ground and power bounce noise.
Background
Currently, in the design process of digital integrated circuits, transmission and processing of digital signals are completed through "1" represented by high level and "0" represented by low level, and noise in a circuit may enter into the transmission process of signals, resulting in an error state of the digital signals, so that a processing circuit for resisting the noise needs to be added in the circuit.
As shown IN fig. 1, the signal waveforms of the nodes of the circuit are shown IN fig. 2, when an input signal (IN) is input into a rising edge, a current source Id2 slowly discharges the capacitor at point a, when the voltage at point a is lower than a threshold voltage, the voltage at point B is inverted, a delay time difference of t1 exists between the input signal IN and the signal at point B, and the circuit can eliminate the positive pulse noise IN the signal transmission channel as long as the time width of the positive pulse noise is smaller than t 1. When an input signal (IN) is input into a falling edge, the current source Id1 slowly charges the capacitor at the point a, when the voltage at the point a is higher than the threshold voltage, the voltage at the point B is inverted, the delay time difference from the input signal IN to the signal at the point B is t2, and the circuit can eliminate the negative pulse noise as long as the time width of the negative pulse noise IN the signal transmission channel is smaller than t 2.
In the process of slowly changing the voltage at the point A in the circuit, in order to prevent the situation that a large through current from power supply to ground is generated when the PMOS tube P1 and the NMOS tube N1 are simultaneously conducted, the P1 or N1 (or the N1 and the P1) can be designed into a MOS tube with a long channel, namely, the width-to-length ratio W/L can be designed to be very small, and the size of the channel length L can be designed to be very large. The large on-resistance value is used for limiting the through current from the power supply to the ground when the P1 and the N1 are conducted simultaneously.
Taking N1 as a long channel as an example, when the bounce noise (Ground noise) on the local line is a negative pulse, if the input signal IN is at a low level at this time, the waveform diagram of each section IN the circuit is shown IN fig. 3. Because the on-resistance of the NMOS transistor N1 is relatively large, the voltage at the point B in the circuit cannot quickly respond to negative pulse noise on the Ground (GND), a voltage difference of a delay time is generated between the point B and the ground, and in this time difference, the NMOS transistor N2 will have a short-time conduction process, so that an erroneous low-level signal output will occur in the output signal OUT of the circuit. The existing noise cancellation circuit is therefore unable to resist negative pulse bounce noise on ground.
Disclosure of Invention
The invention aims to provide a digital signal processing circuit which has a simple and reliable structure and can effectively resist the ground and power supply rebound noise of positive and negative pulse rebound noise on a ground and power supply line.
In order to achieve the above objective, the present invention adopts the technical scheme that the digital signal processing circuit for resisting ground and power bounce noise comprises a first current source, a second current source, a first PMOS tube, a first NMOS tube, a capacitor, a second PMOS tube, a second NMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, an inverter and a voltage locking circuit, wherein the input end of the first current source is connected with a power supply, the output end of the first current source is connected with the source electrode of the first PMOS tube, the gate electrodes of the first PMOS tube and the first NMOS tube are connected and then used as the signal input end of the digital signal processing circuit, the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube are connected, the source electrode of the first NMOS tube is connected with the input end of the second current source, the output end of the second current source is grounded, one end of the capacitor is connected with the drain electrode of the first NMOS tube, and the other end of the capacitor is grounded, the source electrodes of the second PMOS tube, the third PMOS tube and the fourth PMOS tube are all connected with a power supply, the drain electrodes of the second PMOS tube and the fourth NMOS tube are connected, the gate electrodes of the second PMOS tube and the second NMOS tube are connected and then connected with one end of a capacitor, the source electrodes of the second NMOS tube are grounded, the drain electrodes of the third PMOS tube and the third NMOS tube are connected and then connected with the drain electrodes of the second PMOS tube, the source electrodes of the third NMOS tube are grounded, the gate electrodes of the fourth PMOS tube are connected with a signal input end, the drain electrodes of the fourth PMOS tube are connected with the source electrodes of the fifth PMOS tube, one end of the capacitor is connected with the drain electrodes of the fifth PMOS tube and the fourth NMOS tube, a first voltage detection point is led out at the connection position of the drain electrodes of the fifth PMOS tube and the fourth NMOS tube, a second voltage detection point is led out at the connection position of the gate electrodes of the fifth PMOS tube and the fourth NMOS tube, the source electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the source electrode of the fifth NMOS tube is grounded, the grid electrode of the fifth NMOS tube is connected with the signal input end, the input end of the inverter is connected with the signal input end, the output end of the inverter is connected with the first input end of the voltage locking circuit, the second input end of the voltage locking circuit is connected with the signal output end, and the output end of the voltage locking circuit is connected with the second voltage detection point; the voltage locking circuit can lock the voltage of the second voltage detection point so as to stably maintain the logic level of the output signal of the signal output end.
As an improvement of the invention, the voltage locking circuit comprises a first MOS tube and a second MOS tube, wherein the grid electrode of the first MOS tube is connected with the signal output end, the drain electrode of the first MOS tube is connected with the second voltage detection point, the source electrode of the first MOS tube is connected with the drain electrode of the second MOS tube, the grid electrode of the second MOS tube is connected with the output end of the inverter, and the source electrode of the second MOS tube is grounded.
As an improvement of the invention, the inverter is realized by adopting a NOT gate, the input end of the NOT gate is connected with the signal input end, and the output end of the NOT gate is connected with the first input end of the voltage locking circuit.
As an improvement of the invention, the first MOS tube and the second MOS tube are NMOS tubes.
As an improvement of the invention, the width-to-length ratio W/L of the first NMOS tube is designed to be 0.01-0.1.
Compared with the prior art, the circuit has the advantages of ingenious overall structural design, simple and reasonable structure, low realization cost and stable and reliable performance, and can well resist the rebound noise generated on the ground wire and the power wire by using the circuit structural design of the rebound noise resistance formed by combining the inverter and the voltage locking circuit, and the logic level of the signal output by the signal output end is always stably and reliably maintained no matter the rebound noise is positive level pulse or negative level pulse signal, so that the signal processing accuracy of the digital signal processing circuit is effectively improved.
Drawings
Fig. 1 is a circuit diagram of a conventional noise-resistant digital signal processing circuit.
Fig. 2 is a signal waveform diagram of each node of a conventional noise-resistant digital signal processing circuit.
Fig. 3 is a signal waveform diagram of each node when negative pulse rebound noise is generated on the ground of the conventional noise-resistant digital signal processing circuit.
Fig. 4 is a circuit diagram of a digital signal processing circuit that resists ground and power bounce noise in accordance with a preferred embodiment of the present invention.
Fig. 5 is a signal waveform diagram of each node of the digital signal processing circuit for resisting ground and power bounce noise according to the preferred embodiment of the present invention.
FIG. 6 is a signal waveform diagram of nodes when negative pulse bounce noise is generated on the ground of the digital signal processing circuit that is resistant to ground and power bounce noise according to the preferred embodiment of the present invention.
Detailed Description
The present invention is further described and illustrated below in conjunction with the accompanying drawings in order to enhance the understanding and appreciation of the invention.
As shown IN fig. 4, a digital signal processing circuit for resisting ground and power supply bounce noise according to a preferred embodiment of the present invention includes a first current source Id1, a second current source Id2, a first PMOS transistor P0, a first NMOS transistor N0, a capacitor C1, a second PMOS transistor P1, a second NMOS transistor N1, a third PMOS transistor P2, a fourth PMOS transistor P3, a fifth PMOS transistor P4, a third NMOS transistor N2, a fourth NMOS transistor N3, a fifth NMOS transistor N4, an inverter, and a voltage locking circuit, wherein an input terminal of the first current source Id1 is connected to a power supply, an output terminal of the first current source Id1 is connected to a source terminal of the first PMOS transistor P0, gates of the first PMOS transistor P0 and the first NMOS transistor N0 are connected to each other and then serve as a signal input terminal IN of the digital signal processing circuit, the first PMOS transistor P0 is connected to a drain terminal of the first NMOS transistor N0, a source terminal of the first NMOS transistor N0 is connected to an input terminal of the second current source Id2, an output terminal of the second current source Id2 is grounded, one terminal of the second current source Id1 is connected to a drain terminal of the capacitor C1, the other end of the capacitor C1 is grounded, the sources of the second PMOS tube P1, the third PMOS tube P2 and the fourth PMOS tube P3 are all connected with a power supply, the second PMOS tube P1 is connected with the drain electrode of the second NMOS tube N1, the grid electrode of the second PMOS tube P1 is connected with the grid electrode of the second NMOS tube N1 and then is connected with the input end of the capacitor C1, the source electrode of the second NMOS tube N1 is grounded, the drain electrodes of the third PMOS tube P2 and the third NMOS tube N2 are connected and then are used as the signal output end OUT of the digital signal processing circuit, the grid electrodes of the third PMOS tube P2 and the third NMOS tube N2 are connected with the drain electrode of the second PMOS tube P1, the source electrode of the third NMOS tube N2 is grounded, the grid electrode of the fourth PMOS tube P3 is connected with the signal input end IN, the drain electrode of the fourth PMOS tube P3 is connected with the source electrode of the fifth PMOS tube P4, the drain electrode of the fifth PMOS tube P4 and the drain electrode of the fourth NMOS tube N3 are connected with the input end of the capacitor C1, a first voltage detection point A is led OUT from the drain electrode connection position of the fifth PMOS tube P4 and the fourth NMOS tube N3, the grid electrodes of the fifth PMOS tube P4 and the fourth NMOS tube N3 are connected with the drain electrode of the second NMOS tube N1, a second voltage detection point B is led OUT from the joint of the grid electrodes of the fifth PMOS tube P4 and the fourth NMOS tube N3, the source electrode of the fourth NMOS tube N3 is connected with the drain electrode of the fifth NMOS tube N4, the source electrode of the fifth NMOS tube N4 is grounded, the grid electrode of the fifth NMOS tube N4 is connected with a signal input end IN, the input end of the inverter is connected with the signal input end IN, the output end of the inverter is connected with the first input end of the voltage locking circuit, the second input end of the voltage locking circuit is connected with a signal output end OUT, and the output end of the voltage locking circuit is connected with the second voltage detection point B; the voltage locking circuit can lock the voltage of the second voltage detecting point B to stably maintain the logic level of the signal output terminal OUT output signal.
The inverter adopts an NOT gate INV1 to realize the function of signal inversion, the input end of the NOT gate INV1 is connected with the signal input end IN, and the output end of the NOT gate INV1 is connected with the first input end of the voltage locking circuit. The voltage locking circuit is composed of a first MOS tube N5 and a second MOS tube N6, wherein a grid electrode of the first MOS tube N5 is connected with a signal output end OUT, a drain electrode of the first MOS tube N5 is connected with a second voltage detection point B, a source electrode of the first MOS tube N5 is connected with a drain electrode of the second MOS tube N6, a grid electrode of the second MOS tube N6 is connected with an output end of an inverter, and a source electrode of the second MOS tube N6 is grounded.
In addition, the first MOS tube N5 and the second MOS tube N6 are NMOS tubes.
In addition, the width-to-length ratio W/L of the first NMOS tube is designed to be 0.01-0.1, so that the second PMOS tube P1 and the second NMOS tube N1 are prevented from generating through high current from power supply to ground when being simultaneously conducted. The time length of the delay times t1 and t2 is larger than the pulse width of the channel transmission noise, meanwhile, the time length of the delay times t1 and t2 is smaller than the pulse width of the signal input end IN input signal, and the time length of the delay times t1 and t2 can be adjusted by adjusting the size of the capacitor C1, the first current source Id1 and the second current source Id 2.
As shown IN fig. 5, when the signal input terminal IN inputs a rising edge, the second current source Id2 slowly discharges the capacitor C1 at the first voltage detection point a, when the voltage at the first voltage detection point a is lower than the threshold voltage, the voltage at the second voltage detection point B will be inverted, and the signal from the signal input terminal IN to the second voltage detection point B will have a delay time difference of t1, so long as the time width of the positive pulse noise IN the signal transmission channel is smaller than t1, the circuit can eliminate the noise. When the signal input end IN inputs a falling edge, the first current source Id1 slowly charges the capacitor C1 at the first voltage detection point a, when the voltage of the first voltage detection point a is higher than the threshold voltage, the voltage of the second voltage detection point B is turned over, the signal from the signal input end IN to the second voltage detection point B has a delay time difference of t2, and the circuit can eliminate the negative pulse noise as long as the time width of the noise is smaller than t 2. The circuit still has a good cancellation of channel transmission noise transmitted from the signal input IN.
When the rebound noise of a negative pulse is generated IN the ground line, when the input signal of the signal input end IN is at a low level, the output signal of the signal output end OUT is at a high level, so that the first MOS tube N5 and the second MOS tube N6 are kept IN an on state, the voltage of the second voltage detection point B IN the circuit is locked at the low level, and when the negative pulse rebound noise appears on the ground line, the voltage of the second voltage detection point B can quickly follow the response.
As shown in fig. 6, when negative pulse rebound noise occurs on the ground, the present circuit can well resist the influence of the ground rebound noise, and the output signal of the signal output terminal OUT is always kept at a high level.
When the input signal of the signal input terminal IN is at a high level and the output signal of the signal output terminal OUT is at a low level, the second PMOS transistor P1 is turned on because the first voltage detecting point a IN the circuit is at a low level, the voltage of the second voltage detecting point B IN the circuit is locked at the high level of the power supply voltage, and the third NMOS transistor N2 is kept at an on state, so that the output signal of the signal output terminal OUT will be at a low level following the fluctuation of the ground line GND.
Similarly, the influence of the positive and negative level pulse rebound noise generated on the power line on the logic level of the output signal of the signal output end OUT of the circuit can be analyzed in the same way, and the circuit of the preferred embodiment can well resist the rebound noise generated on the ground line and the power line through analysis, and the logic level of the output signal of the signal output end OUT can be stably and reliably maintained through the circuit structure which is formed by combining the inverter and the voltage locking circuit and resists the rebound noise no matter whether the rebound noise is a positive level pulse or a negative level pulse signal. The circuit has the advantages of simple structure, easy realization, low realization cost and stable and reliable performance of resisting rebound noise generated on the ground wire and the power wire.
The technical means disclosed by the scheme of the invention is not limited to the technical means disclosed by the embodiment, and also comprises the technical scheme formed by any combination of the technical features. It should be noted that modifications and adaptations to the invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.
Claims (5)
1. A digital signal processing circuit that is resistant to ground and power bounce noise, characterized by: the DC power supply comprises a first current source, a second current source, a first PMOS tube, a first NMOS tube, a capacitor, a second PMOS tube, a second NMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, an inverter and a voltage locking circuit, wherein the input end of the first current source is connected with a power supply, the output end of the first current source is connected with the source electrode of the first PMOS tube, the grid electrodes of the first PMOS tube and the first NMOS tube are connected and then used as the signal input end of the digital signal processing circuit, the drain electrodes of the first PMOS tube and the first NMOS tube are connected, the source electrode of the first NMOS tube is connected with the input end of the second current source, the output end of the second current source is grounded, one end of the capacitor is connected with the drain electrode of the first NMOS tube, the source electrodes of the second PMOS tube, the third PMOS tube and the fourth PMOS tube are all connected with the power supply, the drain electrodes of the second PMOS tube and the second NMOS tube are connected, the grid electrode of the second PMOS tube is connected with one end of the capacitor, the source electrode of the second NMOS tube is grounded, the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube to be used as a signal output end of the digital signal processing circuit, the grid electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube, the source electrode of the third NMOS tube is grounded, the grid electrode of the fourth PMOS tube is connected with the signal input end, the drain electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube, the drain electrodes of the fifth PMOS tube and the fourth NMOS tube are connected with one end of the capacitor, a first voltage detection point is led out at the junction of the drain electrodes of the fifth PMOS tube and the fourth NMOS tube, a second voltage detection point is led out at the junction of the grid electrodes of the fifth PMOS tube and the fourth NMOS tube, the source electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the source electrode of the fifth NMOS tube is grounded, the grid electrode of the fifth NMOS tube is connected with the signal input end, the input end of the inverter is connected with the signal input end, the output end of the inverter is connected with the first input end of the voltage locking circuit, the second input end of the voltage locking circuit is connected with the signal output end, and the output end of the voltage locking circuit is connected with the second voltage detection point; the voltage locking circuit can lock the voltage of the second voltage detection point so as to stably maintain the logic level of the output signal of the signal output end.
2. The digital signal processing circuit for resisting ground and power bounce noise according to claim 1, wherein the voltage locking circuit comprises a first MOS tube and a second MOS tube, wherein a grid electrode of the first MOS tube is connected with the signal output end, a drain electrode of the first MOS tube is connected with the second voltage detection point, a source electrode of the first MOS tube is connected with a drain electrode of the second MOS tube, a grid electrode of the second MOS tube is connected with an output end of the inverter, and a source electrode of the second MOS tube is grounded.
3. A digital signal processing circuit as claimed in claim 2, characterized in that the inverter is implemented as a not gate, the input of the not gate being connected to the signal input, the output of the not gate being connected to the first input of the voltage lock circuit.
4. A digital signal processing circuit for resisting ground and power bounce noise according to claim 3, wherein said first MOS transistor and said second MOS transistor are NMOS transistors.
5. The digital signal processing circuit of claim 4, wherein the first NMOS transistor has a W/L design of 0.01-0.1.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910400515.3A CN110048711B (en) | 2019-05-15 | 2019-05-15 | Digital signal processing circuit for resisting ground and power supply rebound noise |
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| CN201910400515.3A CN110048711B (en) | 2019-05-15 | 2019-05-15 | Digital signal processing circuit for resisting ground and power supply rebound noise |
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| CN110048711B true CN110048711B (en) | 2023-11-21 |
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| CN116346084B (en) * | 2023-03-14 | 2023-10-20 | 瑶芯微电子科技(上海)有限公司 | High-frequency noise suppression circuit |
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| CN110048711A (en) | 2019-07-23 |
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